Search

This article presents a cost-effective and efficient methodology to evaluate and compare parametric degradation of FPGA performance induced by total ionizing dose (TID). At the component level, TID causes increased power consumption and an altered propagation delay of the logic elements. These parametric deviations must be evaluated to be properly considered in the design margins. Dedicated benchmarking structures have been developed to evaluate the propagation delay evolution of logical resources and routing elements of the FPGA. An embedded system based on the reprogrammable feature of embedded PLLs has been implemented to continuously measure in situ the propagation delay evolution during radiation experiments with limited instrumentation. Particular attention was paid to the decoupling of thermal effects and direct TID effects. The effectiveness and benefits of this methodology are demonstrated through X-ray radiation tests. Test results on three FPGA families: Xilinx Spartan7, Artix7, and Intel Cyclone10LP are presented, compared, and discussed. [ABSTRACT FROM AUTHOR]

A high-frequency multibiased multiphase voltage-controlled oscillator (MBM-VCO) for clock and data recovery is proposed. The operating frequency of the voltage-controlled oscillator (VCO) ranges from 2.1 to 5.5 GHz. The sensitivity of the VCO to bias is reduced through multibias technology and interleaving bias, while the ability to single-event transient (SET) tolerance of the ring oscillator is improved through layout hardening. Laser experiments show that the threshold value of the proposed MBM-VCO is greatly improved. Ion experiments further show a SET tolerance under linear energy transfers (LETs) of 83.7 MeV $\,\cdot $ cm2/mg. [ABSTRACT FROM AUTHOR]

This article proposes a dual injection locking technique to significantly enhance the locking range (LR) of the injection-locked frequency tripler (ILFT). Compared with the conventional circuit topology that typically suffers from limited LR due to $G_{m}$ degeneration, the proposed technique employs drain injection and source injection together to increase the LR, with power consumption increased only a little. Fabricated in standard CMOS 65-nm technology, the ILFT prototype measures a 39.4% LR at 0-dBm input power while consuming 8.16 mW from a 1-V supply. The chip area is 0.32 mm2 including the pads. The proposed ILFT is applicable for local oscillation generation in the 5G transceiver. [ABSTRACT FROM AUTHOR]

This article presents a fully integrated low-intermediate frequency (IF) receiver, Dhruva, for global navigation satellite system (GNSS). The compact receiver uniquely features a fully programmable IP with no external components and no change in the on- chip hardware for various GNSS signals (civilian and precise positioning). The receiver bandwidth is programmable from 2 to 24 MHz for signals around $L1$ , $L2$ , $L5$ , and $S$ frequency bands from Navigation with Indian Constellation (NavIC), global positioning system (GPS), Galileo, and BeiDou. A single-to-differential wideband input-matched noise-canceling low-noise amplifier (LNA) is proposed to avoid the external balun and matching components. An on- chip fractional- $N$ phase-locked loop (PLL) with a single voltage-controlled oscillator (VCO) generates the required local oscillator (LO) frequencies. A dc offset correction circuit is proposed in the variable gain amplifier (VGA) to avoid signal saturation. Fabricated in 65-nm CMOS technology, the receiver draws a current of 38.35 mA from a 1.2-V supply while providing a maximum gain of 101.72 dB with a programmable gain of 53.53 dB and a minimum noise figure (NF) of 3.8 dB. The receiver occupies an active die area of 1.96 mm2, including the I/O padring with ESD protection. [ABSTRACT FROM AUTHOR]

Considering that the traditional linearization method cannot accurately analyze the grid-tied inverter (GTI) system with nonlinear nature, in the single-phase case, a novel nonlinear model for the GTI system considering nonlinear factors, including synchronous reference frame phase-locked loop (PLL) and duty-cycle saturation in pulsewidth modulation, is proposed, and the corresponding global asymptotic stability condition is given. Specifically, some system nonlinear factors, e.g., duty-cycle saturation phenomenon and Park (dq) transformation and cosine operation in second-order generalized integrator-based PLL (SOGI-PLL), are investigated, and their sector-bounded conditions are derived. In order to seek less conservative results, the system state of the SOGI-PLL is restructured such that the linear part of the PLL system can be stabilized. Then, the nonlinear state-space model with sector bounded for the whole GTI system is formulated. Furthermore, the deduced sector conditions are introduced into the derivation of the Lyapunov function by using the S-procedure lemma, and the global asymptotic stability condition of the inverter system is, thus, obtained. The system stability regions under different grid impedances, current references, and control parameters are further analyzed. Finally, the effectiveness of the proposed theories is fully supported by transient experimental results. [ABSTRACT FROM AUTHOR]

Suppressing the negative effects of grid voltage harmonics on the estimated frequency of a phase-locked loop (PLL) is a challenge in literature. This article proposes an easy-to-implement quadrature signal generator (QSG) to attenuate the oscillations on the estimated frequency in single-phase grid-connected inverters, which use second-order generalized integrator (SOGI)-PLL. It is shown that SOGI exerts a stronger filtering effect in generating the quadrature signal than the in-phase signal. Against this background, in this work, a modified integrator is introduced into the path of the in-quadrature signal to generate another in-phase component with much lower harmonic content. The proposed method imposes only a small computational burden on the existing SOGI-PLL compared to the previously presented methods that address the input voltage harmonic problem. Moreover, this method can work properly within the allowable range of grid voltage frequency deviations. The proposed integrator benefits from an error-decaying mechanism to overcome dc drift in pure integrators. The integrator has been designed based on theoretical equations. The validity of the proposed QSG and theoretical equations is evaluated using simulations and experimental studies. A fixed-point representation of the proposed QSG is also provided for implementation on low-cost microcontrollers. [ABSTRACT FROM AUTHOR]

The wide bandwidth of phase-locked loop (PLL) will increase the negative real part of the output impedance of the grid-connected inverter (GCI), thus destroying the stability of the weak grids. This article proposes a novel method to improve the system stability through decoupling the PLL and grid impedance. Initially, the coupling relationship between PLL and grid impedance is revealed. It can explain why the choice of PLL bandwidth and the grid impedance magnitude is limited. Then, the decoupling method is proposed where the primary control structure of GCI does not need to change and uses the structured voltage, the product of PCC voltage and grid admittance, as the improved input of PLL. The proposed method can achieve the full-frequency passive of the output impedance of GCI even if the PLL has high bandwidth and the impedance measurement error is up to 60%, which means the adverse stability effect of PLL on the system is eliminated. The theoretical analysis is verified by simulations and experiments. [ABSTRACT FROM AUTHOR]

This article proposes a 3.2-GHz subsampling phase-locked loop (SSPLL)-based injection-locked clock multiplier (ILCM) using a subsampling delay-locked loop (SSDLL). The proposed ILCM achieves a superior noise reduction effect at low offset frequency because of the high feedback gain of SSPLL. Also, SSDLL is proposed for background phase calibration between SSPLL and injection. Since SSPLL and SSDLL use identical SSCP, the power consumption of the frequency and phase calibration is only 1.32 mW. This work is fabricated in a 65-nm CMOS process, and the 10-kHz phase noise is improved by 8.6 dB. The rms jitter from 10 kHz to 30 MHz is 178 fs. The chip-to-chip variations (20 chips) are 17 and 169 fs with/without SSDLL, respectively. The measured results show that FoM1, FoM2, and total power consumption are −245.1, −260.1 dB, and 9.85 mW, respectively. [ABSTRACT FROM AUTHOR]

A frequency multiplier by six (sextupler) for local oscillation (LO) generation in $E$ -band is presented. It comprises a tripler, a doubler, and an output buffer. A detailed analysis is proposed to discuss the optimal order of the multiplication stages to minimize the unwanted harmonics of the input. Moreover, novel circuit topologies for the tripler and doubler are introduced. The tripler core is devised to reproduce the transcharacteristic of a third-order polynomial that ideally generates only the third harmonic of a sinusoidal input signal. By leveraging an envelope detector for adaptive biasing, the circuit maintains excellent suppression of the driving signal and unwanted harmonics over wide variations of the input power. The proposed topology improves output signal purity and current conversion efficiency against classical triplers based on the transistors biased in class C. The cascaded frequency doubler is based on a novel push–push configuration that provides a differential output and excellent odd-order harmonic rejection due to an enhanced robustness to amplitude and phase unbalances of the driving signal. The sextupler is fabricated in a 55-nm SiGe-BiCMOS technology. Driven with a 0-dBm input signal and consuming 63.1 mW of dc power, it delivers $P_{\mathrm {out}}$ up to 5.6 dBm at 72 GHz. $P_{\mathrm {out}}$ is above 0 dBm over 20-GHz bandwidth (BW), while undesired harmonics of the input are suppressed by more than 35 dB. Compared to previously reported millimeter-wave frequency multipliers, the sextupler demonstrates improved harmonic rejection, conversion gain, and efficiency, without compromising the operation BW and output power. [ABSTRACT FROM AUTHOR]

A 24 GHz self-calibrated all-digital frequency-modulated continuous-wave (FMCW) synthesizer is presented in this article. A multi-bank digitally controlled oscillator (DCO) is employed to provide adequate frequency tuning range and high frequency resolution. A full background self-calibration scheme is proposed to linearize the DCO tuning curve for highly linear and fast chirp generation. An overlap compensator based on an adaptive lookup table (LUT) is utilized to eliminate the frequency overlaps between adjacent DCO tuning bands. The compensation words in the LUT are altered by least-mean-square (LMS) algorithm for robust and precise matching. A ramp tracker, which features real-time ramp tracking with zero steady-state phase error, is employed to estimate and stabilize the frequency ramp. Implemented in 40 nm bulk CMOS, the FMCW synthesizer prototype consumes 28 mW with a 0.26 mm2 core area. The maximum chirp bandwidth is 3.2 GHz, corresponding to 13.33% of the center frequency. Measurement results show that the root-mean-square (RMS) frequency error is reduced by 1/10 with self-calibration after 2 ms convergence time. The maximum chirp slope is up to 320 MHz/ $\mu \text{s}$ with 309 kHz RMS frequency error. The minimum RMS frequency error is 7.35 kHz under 5 MHz/ $\mu \text{s}$ chirp slope, corresponding to 0.0002% of the chirp bandwidth. [ABSTRACT FROM AUTHOR]

This paper proposes a supplementary controller to damp out the power and frequency oscillations of inverter-based resources (IBRs) connected to weak power grids. The proposed supplementary controller is integrated into the commonly used Proportional Integral (PI) controllers in the synchronous reference frame (SRF). It does not change the conventional basic control loops and only injects two additional control commands to the basic controller loops of IBRs to improve the transient response of the controllers without affecting their regulation performances. The dynamic of phase locked loop (PLL) is considered in the design of the proposed controller, which enables the proposed supplementary controller to have an effective performance in weak power grids. The proposed supplementary controller is designed based on the interconnection damping assignment passivity based (IDA-PB) control strategy with the capability of injecting damping to both relative-degree-one (RD1) and higher-relative-degree (HRD) states of IBRs. The effectiveness of the proposed supplementary controller is verified using a set of time-domain simulations on a sample multisource weak power grid. [ABSTRACT FROM AUTHOR]

In this tutorial brief, we introduce a unified wideband phase-noise theory framework of frequency synthesis based on a multirate timestamp modeling with “two $z$ -variables”. We apply it to model and analyze two types of ultra-low jitter (i.e., sub-50fs) phase-locking techniques: 1) high-bandwidth PLLs with high phase-detector gain (with emphasis on all-digital PLLs), and 2) injection locking (IL) or recently proposed charge-sharing locking (CSL), serving as a unified guide on achieving the sub-50 fs jitter. All analytical results are numerically verified through time-domain behavioral simulations, demonstrating that the theoretically maximum bandwidths are around 30% and 44% of the reference frequency in PLLs and IL, respectively. [ABSTRACT FROM AUTHOR]

In recent years, the doubly fed induction generator (DFIG)-based wind power generation and high-voltage direct-current (HVDC) transmission are widely utilized in practice. The stability issues of sending AC grid, which is composed of line-commutated converter (LCC)-based HVDC and DFIG system, is worthy of attention. Commutation is an important factor in the impedance model of LCC-HVDC rectifier, due to the nonnegligible leakage inductance of transformer. However, it was overlooked in previous studies because there are many difficulties in modeling commutation overlap characteristic. In this paper, the spectral models of voltage and current mapping functions are proposed by 3-D Fourier series method, in which the commutation overlap angle is considered. Then, based on the concept of harmonic linearization, an analytical model that describes the commutation process is established and validated by simulations. The mechanism that the commutation overlap characteristic affects the impedance model of LCC-HVDC is investigated, and the simplified modeling method in different frequency bands is studied. The stability of sending AC grid is analyzed applying the Generalized Nyquist Criterion (GNC). The results of stability analysis show that the effect of commutation overlap cannot be ignored. The simulation results confirm the correctness of the obtained conclusion. [ABSTRACT FROM AUTHOR]

In this paper a second order generalized integrator (SOGI) based quadrature signal generator (QSG) is proposed with the improved DC offset compensation parameter tuning procedure. Namely, for the conventional DC rejection technique, which comprises an integrator (I) included in the SOGI, the modified parameter tuning procedure is proposed based on the set QSG response damping factor value. In this way, when compared to existing QSG tuning techniques based on empirical trial-and-error approach, simplified parameter tuning procedure is proposed based on proposed parametric equations, which enable improved QSG performance verified by simulation and experimental runs by a single-phase phase-locked loop PLL. In this way the increased SOGI based QSG DC offset compensation speed can be achieved, which is critical in various types of single phase PLL applications.

With widespread application of voltage source converter (VSC) as a key energy-conversion power electronic device by using the phase-locked loop (PLL) technique for synchronization, the system dynamics has become much complicated. In this paper, the nonlinear dynamics and transient stability of the PLL-based VSC system are investigated, within a unified framework of the (normalized) generalized swing equation. It is found that there are three different types of bifurcation, including the generalized saddle-node, Hopf, and homoclinic bifurcations. Within the coexistence parameter region, the basin boundary of the stable equilibrium point shows either a closed-loop or a fish-like pattern. With the help of the equal area criterion (EAC), the transient stabilities under different transient disturbances including short circuit, voltage dip, and power rise are analyzed. Because the equivalent damping of the VSC is state-dependent, the theoretical results based on the EAC are examined. Furthermore, based on the analytical results from the generalized swing equation, the principle for all major transient stability enhancement methods is uncovered. All these findings are well verified by extensive electromagnetic transient simulations. Therefore, the generalized swing equation provides a deeper physical insight and plays a crucial role in transient stability problems in power-electronic-dominated power systems, similar to the swing equation in traditional power systems. [ABSTRACT FROM AUTHOR]

Out of various moving average filter (MAF)-based phase-locked-loop (PLL), quasi type-1 PLL (QT1-PLL) is widely adopted due to its fast dynamic performance, implementation simplicity, and harmonics rejection abilities. However, the performance of QT1-PLL deteriorates in the presence of an off-nominal frequency unbalanced grid voltage component. Moreover, the sensitivity towards the fundamental frequency negative sequence (FFNS) component is high. Hence, this paper proposes a novel enhanced QT1-PLL solution that is insensitive to unbalance in the grid voltage signal during off-nominal frequency conditions. The proposed adaptive phase detector makes it possible to estimate both the fundamental frequency positive sequence (FFPS) and FFNS components with a high degree of immunity against harmonics. Notably, the pre-loop separation of the FFPS and the FFNS components helps suppress the second harmonic oscillations for improving the parameter estimation accuracy. The loop-filter design of QT1-PLL remains unaffected and requires a proportional gain to estimate the fundamental phase and frequency information. To address the DC offset issue, a modified delayed signal cancellation method is also proposed, which can theoretically eliminate the DC offset for any arbitrary delay length. A small-signal model of the proposed PLL is developed for the sake of stability analysis. Comparative numerical simulation and experimental results are provided with various variants of QT1-PLLs to demonstrate the performance improvement achieved with the proposed technique. [ABSTRACT FROM AUTHOR]

In this paper, the transient stability for dc-link voltage of doubly-fed induction generator (DFIG)-based wind turbine (WT) is studied in detail during low voltage ride-through (LVRT). Firstly, referring to the rotor swing equation of synchronous generator (SG), the nonlinear large-signal model of dc-link voltage is established. In addition, the damping power, static slip power, and dynamic slip power are derived. Consequently, the transient performance of dc-link voltage under the different operation conditions of DFIG is revealed during LVRT. Furthermore, the instability form of dc-link voltage with the moving process of equivalent power angle is analyzed by the energy function of dc-link voltage. In addition, the impacts of dc voltage control loop's parameter, the active current of the stator, and the slip on the stabilization process of dc-link voltage are studied. Analysis result indicates that the insufficient damping and large unbalanced power would deteriorate the transient behavior and steady-state level of dc-link voltage. Therefore, an additional damping and slip power feedforward control strategy is proposed, which can make the transition process of dc-link voltage smoother and significantly improve the voltage steady-state level. Finally, simulation and experimental results validate the effectiveness of theoretical analysis. [ABSTRACT FROM AUTHOR]

A phase-locked loop or phase lock loop (PLL) is, essentially, a closed loop control system, where its output signal (regulated) maintains a direct (chosen) relationship to the input signal (unregulated). If the phases of the input and output signals remain the same, their frequencies will also match. In its usual way, a PLL is an electronic circuit with filters and controllers that must be tuned each time, according to the input signal parameters. As a contribution and novelty, this paper introduces a new, easy, fast and highly efficient PLL algorithm, that it does not need to adjust every time the input signal changes. This makes it independent of the input signal it receives and, therefore, and in a certain way, universally applicable. In addition, the proposal is implemented exclusively by software, housed in a microcontroller, which also represents another novelty. As another remarkable feature, the proposed algorithm is very simple, with a very low computational cost, which makes it very stable, practically insensitive to noise, and very fast. These characteristics and the performance shown over a wide range of input signal frequencies, make the proposed algorithm suitable for use in different applications, from the electricity grid synchronization to the demodulation of frequency modulation, DC motor drives, etc. In addition to frequency and phase tracking, the developed algorithm generates the signal corresponding to the fundamental frequency of the input signal. Furthermore, the algorithm behavior is not affected by the input signal distortion and is independent of its initial phase. The performance and excellent behavior of the developed algorithm are evaluated through simulations and experimental tests. [ABSTRACT FROM AUTHOR]

Flux linkage estimation based on the voltage model has been widely employed in surface-mounted permanent magnet synchronous machine (SPMSM) sensorless drives due to its simple implementation. To deal with dc-offset and dc-drift problems, the pure integrator is modified as a programmable low pass filter (LPF)in practice. However, the estimation accuracy of the rotor position is affected by the adopted filter. Although the position deviation is compensated in steady-state based on the frequency characteristics of the filter, the compensation effect deteriorates during a dynamic process which severely degrades the sensorless control performance. In order to effectively tackle this problem, a novel compensation strategy based on the linear extended state observer (LESO) is proposed in this paper. With the constructed LESO in the estimated synchronous rotating reference frame, the position estimation error can be detected and compensated both in the steady and dynamic state. Moreover, the observer is enhanced to improve the estimation accuracy in linear acceleration and deceleration. Finally, the feasibility of the proposed method is verified under various operating conditions with a 5.5 kW SPMSM drive system. [ABSTRACT FROM AUTHOR]

Blocking the grid voltage imbalance through the $\alpha \beta$ -frame delayed signal cancellation ($\alpha \beta$ DSC) operator requires a relatively high delay value of $1/4$ cycle. Since the dynamic behavior of the $\alpha \beta$ -frame cascaded delayed signal cancellation based phase-locked loop ($\alpha \beta$ CDSC-PLL) depends on the total delay length of the cascaded operators, this value can slow down the dynamic response. In this paper, however, inspired by the delayed signal cancelation (DSC) concept, an enhanced $\alpha \beta$ -frame DSC operator, which removes the grid voltage imbalance with a delay length of only $1/12$ cycle, is proposed. The small-signal model of the suggested frequency adaptive operator is derived, making the tuning procedure and stability analysis easy yet effective. Due to the shorter delay length, using the proposed operator in the $\alpha \beta$ CDSC-PLL structure leads to a higher speed-of-response and, therefore, a less phase-angle error during grid voltage scenarios. Moreover, when the total delay length decreases, the filtering capability will be improved using more operators at the chain of the cascaded DSC operators. The performance of the $\alpha \beta$ CDSC-PLL and its suggested enhanced structure, benefiting from the proposed operator, are compared through theoretical analysis and experimental tests, which verify that the proposed structure offers a better dynamic response and filtering capability. [ABSTRACT FROM AUTHOR]

This article focuses on the modeling and stability analysis of the typical single-phase phase-locked loop (PLL) based on second-order generalized integrator (SOGI). Traditionally, SOGI-based PLL (SOGI-PLL) is linearized as the linear time-invariant (LTI) model for the stability analysis and parameter design. Yet, the PLL has periodical nature due to the periodical variation of the grid voltage. The traditional LTI model for PLL thereby reduces the precision of stability analysis. For addressing this problem, an accurate linear time-periodic (LTP) model of the single-phase SOGI-PLL is proposed in this article. The proposed model can precisely characterize the coupling nature of phase, frequency, and amplitude estimated by SOGI-PLL. A precise stability region of SOGI-PLL, thereby, can be derived from the proposed LTP model. The effectiveness of the proposed LTP model for SOGI-PLL is verified by simulation and experimental tests. [ABSTRACT FROM AUTHOR]

In this article, we analyze the negative impact of phase-locked loop (PLL) on the stability of the doubly fed induction generators system. The small-signal disturbance of PLL mainly affects the coordinate transformation of the rotor current and introduces a negative resistance within PLL bandwidth. Two impedance reshaping methods are carried out to weaken this negative resistance. A virtual impedance in the conventional current control is added to the first reshaping method. The second reshaping method completely removes the coordinate transformation of the rotor current by switching the control target from current to power. The difference between these two reshaping methods is analyzed based on the equivalent single-input single-output impedance model. The experimental results validate the effectiveness of these two reshaping methods and the superiority of the second reshaping method at a lower short-circuit ratio. [ABSTRACT FROM AUTHOR]

This article presents an improved Gaussian filter with phase-locked loop based grid monitoring and seamless transfer control for solar photovoltaic-battery energy storage (PV-BES) based microgrid with improved power quality. The PV-BES microgrid comprises of a PV array and a battery, interfaced to the utility through a voltage source converter, and performs multiple tasks. In grid-connected mode, the improved Gaussian filter with quadrature signal generator-based second-order generalized integrator based prefiltering provides solar PV power to the nonlinear loads and the utility grid, along with providing reactive power compensation and power quality improvement at the point of common coupling. To regulate the power absorbed or discharged by the BES, a bidirectional converter is used. The PV feed-forward term enables PV power injection and also improves the dynamic performance of the system. On grid outage, the controller transits the PV-BES microgrid to standalone mode of operation ensuring uninterrupted supply to the load. The effectiveness of the controller is tested in various scenarios and is verified through experimentation. The controller has satisfied the specifications set by the IEEE 519-2014 power quality standard and IEEE 1547-2018 (revised) standard for interconnection and interoperability of distributed energy resources. [ABSTRACT FROM AUTHOR]

The stability of the grid-connected inverter (GCI) system in weak grids is deteriorated due to the asymmetric positive-feedback loops (APFLs) introduced by the phase-locked loop (PLL) structure. Under the same main circuit parameters and control loop parameters, the small-signal models of the GCI controlled in dq domain and αβ domain are constructed, respectively. Compared with the small-signal model of the GCI controlled in dq domain, the number of APFLs introduced by the PLL of GCI controlled in αβ domain is one less. Moreover, the mechanism why the stability of the GCI controlled in αβ domain is stronger than that controlled in dq domain is analyzed. Meanwhile, the influence degree and mechanism of the APFLs in different paths of the small-signal models for the stability of GCI are revealed for the first time. This lays a theoretical foundation for the analysis and design of asymmetric control strategies used to improve the stability of GCI in weak grids. Finally, simulations and experiments verify the correctness of the theoretical analysis. [ABSTRACT FROM AUTHOR]

Large scale renewable energy systems interfaced with voltage source converters (VSCs) experience several challenging issues when integrated to weak grids. One of the specific issue i.e. control loop interaction of vector-controlled VSC under high grid impedance leads to several instability mechanism ultimately resulting in unwanted tripping of the VSC unit. As a countermeasure, a unique nonlinear adaptive stabilizing control (NASC) technique has been proposed in this paper to enhance the dynamic stability of the VSC during such scenarios. A small-signal model is developed first to examine the instability mechanism of VSC connected to weak grids under abnormal operating conditions and varying set points of the power controller. The dominant modes are identified from the analysis and a stabilizing controller is developed based on adaptive dynamic surface control philosophy for enhancing its stability. The proposed controller has been proved to be uniformly ultimately bounded using Lyapunov analysis. Besides, the stabilizing mechanism of VSC is analyzed with the proposed controller by performing small-signal stability analysis of the entire system. The efficacy of the proposed control scheme is demonstrated by performing numerical simulations in MATLAB 2017a and conducting experimental validations in controller-hardware-in-the Loop (CHIL) platform. [ABSTRACT FROM AUTHOR]

This paper addresses the interactions among the control loops of voltage-sourced converters (VSCs) embedded in high-voltage direct current (HVDC) systems and the impact of these interactions on the performance of individual control loops. Furthermore, this paper proposes a method to design the individual control loops, rather than the interconnected control system, such that the overall system stability is ensured in the presence of interactions. This paper addresses three aspects of the impact of control loop interactions on the overall control system of the VSC including stability, transient response, and steady-state response. To illustrate the impact of interactions on the VSC small-signal stability, stability regions of the interconnected control loops are obtained and compared against those of the various individual control loops. Then, a novel formulation of the VSC stability criterion is presented, and the small-gain theorem is utilized to determine a range of stabilizing gains for the interconnected control system. Moreover, new indices using the infinity norm are introduced to evaluate the impact of interactions on the transient response of the VSC. Finally, the DC gain of a certain set of transfer functions is used to assess the impact of control loops interactions on the set-point tracking capability of the VSC. The introduced indices along with time-domain simulations show that the transient response of the d-axis control loops is not impacted by the interactions, whereas that of the q-axis control loops is significantly impacted by the interactions. The set-point tracking capability is proved to be independent of interactions. [ABSTRACT FROM AUTHOR]

The Type-II synchronous-reference-frame (SRF) phase locked loop (PLL) fails to precisely keep tracking on phase of input signals when the frequency of input signals is under ramp state, whereas the type-III SRF-PLL addresses the above issue but stability problem arises. In this letter, a forward compensation (FC) module is introduced to the Type-II SRF-PLL to minimize the dc phase error due to the ramp frequency of input signals, named as FCSRF-PLL, which features low computational burden, simple structure, noise immunity, and high robustness. More importantly, the parameter tuning in the proposed method will not cause stability problem. The effectiveness of the proposed FCSRF-PLL is verified through experiments based on dSPACE. [ABSTRACT FROM AUTHOR]

In this article, an improved grid synchronization method for three-phase grid-feeding converters using a dual enhanced second-order generalized integrator (eSOGI) frequency-locked loop (FLL) is proposed. The eSOGI, of which gains can be adjusted based on the positive-sequence component of the grid voltage, is designed to estimate the grid voltage accurately. Moreover, to improve the grid frequency estimation under grid voltage sags, frequency rate limits is suggested in the FLL structure. The selection of the eSOGI-FLL parameters is described as well. After the estimated grid voltages are obtained using the dual eSOGI-FLL, they are used to synthesize the references in the dual-current controllers for positive- and negative-sequence components. Through the simulation and experimental results under grid voltage sags and distorted grid conditions, the improved power control performance of the proposed method has been demonstrated in comparison with those of the existing methods. [ABSTRACT FROM AUTHOR]

The grid-tied cascaded H-bridge (CHB) converter may become unstable, especially for the traction onboard application where the grid impedance may gradually vary as the train moves. In order to overcome this weakness, a small-signal stability-based adaptive control strategy is proposed in this article, where the parameter of the current-inner-loop controller is adaptively regulated according to the online grid inductance identification (GII) result. In the proposed control structure, there is only one control parameter needed to be regulated online, which is based on the estimated value of the grid inductance. In this article, the grid inductance is estimated by injecting the specific harmonic current. With the corresponding harmonic current regulator, stable and sustained harmonic current can be injected, which is beneficial to mitigate the fierce fluctuation of the GII result. The GII algorithm is made up of three parts, including the analog low-pass filter, the sliding discrete Fourier transform, and the digital composite filter, which can suppress the switching noise, the low-frequency grid harmonics, and the grid frequency deviation. With the proposed adaptive control strategy, the CHB can ensure small-signal stability wherever it is connected. All these theoretical analyses are verified by the experiment. [ABSTRACT FROM AUTHOR]

Accurate, and low phase noise RF synthesis is crucial for various applications. The phase-locked loop (PLL) is the common architecture to synthesize high spectral purity RF carriers with desired frequencies. However, the phase noise is limited by the electrical voltage-controlled oscillators (VCOs). Optoelectronic oscillator (OEO) is an alternative of RF oscillator that allows overcoming the phase noise limitation of electrical oscillator. Here, we propose a novel photonic RF synthesizer by using a voltage-controlled optically tunable OEO as VCO in a PLL. By phase-locking OEO to a tunable RF reference, tunable RF carrier with precise frequency can be synthesized. The OEO incorporates a RF photonic filter as the mode selector harnessing the light-sound interaction in a fiber, namely the stimulated Brillouin scattering. Due to the low dissipation rate of the confined acoustic wave, a narrowband anti-Stokes loss spectrum is formed, which can be transformed into a high quality factor tunable RF bandpass filter with the aid of a phase modulated optical probe wave. It facilitates the removal of the supermodes and enables the frequency tuning of OEO. Experimentally, we attain a RF synthesizer with frequency synthesis tuning range from 6 GHz to 12 GHz. The minimum tuning step is 8 Hz. At 8.4 GHz, the phase noise is −125 dBc/Hz at 10 kHz offset. The phase-locking dynamics, frequency tunability, and phase noise are thoroughly investigated. Our approach offers the prospects of low phase noise RF synthesis with wide frequency range. [ABSTRACT FROM AUTHOR]

High-order modulation formats with high symbol rates are promising candidates for meeting the growing traffic requirements of digital coherent transmission. In using these modulation formats, the impact of transceiver impairment on the signal quality becomes significant. In this paper, we propose an 8×2 widely linear (WL) multiple-input multiple-output (MIMO) equalizer with independent complex filtering on IQ signals to mitigate linear transceiver impairments. Furthermore, we extend the equalizer for digital subcarrier (SC) multiplexing. Accordingly, a 16×4 WL MIMO equalizer is also proposed to mitigate linear transceiver impairments, through application to a pair of SC inputs. Experimental results show that, for transmission of a 58-GBaud polarization-multiplexing 64 quadrature amplitude modulation (PM-64QAM) single-carrier signal, the proposed method effectively compensates for various receiver impairments and also mitigates transmitter (Tx) impairments. Q-penalties of 0.1 dB up to a 10-ps skew, 2.5-dB gain imbalance, 7.2-degree phase error, and –15-dB crosstalk in Tx were achieved for 100-km standard single-mode fiber transmission. Moreover, for a 29-GBaud PM-64QAM dual-SC signal, the proposed 16 × 4 WL MIMO equalizer shows transceiver impairment mitigation performance similar to that in the single-carrier case, even though dual-SC transmission is less tolerant of laser phase noise. [ABSTRACT FROM AUTHOR]

This article presents an injection-locked (IL) ring-oscillator-based fractional- ${N}$ digital phase locked loop (DPLL) supporting Bluetooth low energy (BLE) frequency modulation with an frequency-shift keying (FSK) error between 2.4% and 3.3%. As the fractional spur cannot be suppressed by IL-DPLL, this work proposes a random edge injection (REI) to reduce the spur. This technique also speeds up the convergence time of gain calibration of the digital-to-time converter (DTC). Furthermore, the proposed background calibration schemes allow the DPLL to achieve stable performance across all BLE channels, including both integer- ${N}$ and fractional- ${N}$ channels. This work was fabricated in the 40-nm CMOS technology occupying a 0.09-mm2 area. A fractional spur of −44 dBc and a reference spur of are achieved while consuming 2.76 mW when REI is activated. The background calibrations also ensure stable performance across BLE channels. [ABSTRACT FROM AUTHOR]

This article presents a ring oscillator (RO)-based all-digital phase-locked loop (ADPLL) that is implemented with a high-gain analog closed loop for supply noise compensation (ACSC). The ACSC not only allows high-frequency oscillation of the RO but also is robust over process, voltage, and temperature (PVT) variations thanks to its replica-based configuration. Moreover, a comprehensive analysis of the noise contribution of the ACSC is conducted for the ADPLL to retain its low-jitter output. Implemented in 40-nm CMOS technology, the ADPLL, with a 1.1-V supply, achieves an rms jitter of 289 fs at 8 GHz without any injected supply noise. Under a 20- $\text{m}\textrm {V}_{\textrm {rms}}$ white supply noise, the ADPLL gives rms jitters of 8.7 and 0.63 ps at 8 GHz when the ACSC is disabled and enabled, respectively. The overall power consumption and the area of the presented ADPLL are 9.48 mW and 0.055 $\textrm {mm} {^{\mathrm{ 2}}}$ , respectively. [ABSTRACT FROM AUTHOR]

This article presents a 23.9–29.4 GHz digital LC-phase-locked loop (PLL) architecture with a low phase noise (PN) and power-efficient coupled frequency doubler for 224 Gb/s PAM-4 transmitter clocking. The proposed frequency doubler is designed with two oscillators running at 14 and 28 GHz which are coupled by a transformer. Compared to a conventional frequency doubler or a two-way coupled oscillator, the coupling between the 14 and 28 GHz oscillators provides extra PN reduction as the 14 GHz oscillator can achieve lower PN than the 28 GHz one. In addition, by stacking the two oscillators through the transformer, the current is reused and hence power consumption is reduced. To optimize the PN performance across process, voltage, and temperature (PVT), a compact and power-efficient frequency-tracking loop (FTL) is implemented. The 14 GHz oscillator output is fed to the PLL feedback divider rather than the doubled output, which enables power saving in the prescaler divider in the feedback path. The proposed PLL is fabricated in 10 nm FinFET technology and the PLL achieves a 65 fs random jitter at the transmitter output after a 1st-order 4 MHz-BW CDR filtering which enables the industry’s first 224 Gb/s PAM-4 transmitter. Compared with a reference NMOS-GM LC-digitally controlled oscillator (DCO) implemented on the same die, the proposed coupled frequency doubler achieves 4.75 dB lower PN with only a 25% power consumption increase. The LC-PLL consumes 17.1 mW from a 0.8/1.0 V regulated supply and occupies an area of 0.088 mm2. [ABSTRACT FROM AUTHOR]

In this article, we present a 4.5–5.1-GHz fractional- $N$ digitally intensive phase-locked loop (DPLL) capable of maintaining its performance in face of a large supply ripple, thus enabling a direct connection to a switched-mode dc–dc converter. Supply pushing of its inductor–capacitor ($LC$) oscillator is suppressed by properly replicating the supply ripple onto the gate of its tail current transistor, while the optimum replication gain is determined by a new on- chip calibration loop tolerant of supply variations. A proposed configuration of cascading a supply-insensitive slope generator with an output of a current digital-to-analog converter (DAC) linearly converts the phase error timing into a corresponding voltage, which is then quantized by a successive approximation register (SAR) analog-to-digital converter (ADC) to generate a digital phase error. We also introduce a low-power ripple pattern estimation and cancellation algorithm to remove the phase error component due to the supply-induced delay variations of loop components. Implemented in 40-nm CMOS, the DPLL prototype achieves the performance of 428-fs rms jitter, <−55-dBc fractional spur, and <−54-dBc maximum spur while consuming 3.25 mW and being subjugated to a sinusoidal or sawtooth supply ripple of 50 mVpp at 50-MHz reference divided by 3, 6, or 12. [ABSTRACT FROM AUTHOR]

This study presents a design of a 94-GHz high-performance and highly compact frequency-modulated continuous-wave radar sensor. In this sensor, an $X$ -band CMOS-based all-digital phase-locked loop chip, $W$ -band SiGe-based transceiver monolithic microwave integrated circuit (MMIC), and $W$ -band GaN-based MMIC power amplifier (PA) are heterogeneously integrated (HI). Each part of the 130-nm bipolar complementary metal-oxide-semiconductor (BiCMOS) SiGe-based transceiver MMIC is designed to include a low-noise amplifier, PA, octupler, mixer, and lange coupler. The fabrication process of our in-house silicon-based MEMS photosensitive composite film is developed to provide very high-density integration and very low insertion loss of interconnections between chips. The HI front end of the radar sensor is measured on-wafer with a high output power of 22 dBm. Moreover, a low double-sideband noise figure (NF) of 10.2 dB is obtained. Bonding–substrate integrated waveguide (SIW)–WG transitions between the heterogeneously integrated front end and the antenna are specially designed and verified. A 2.3-dB degradation is observed, where 19.7 dBm is measured at the transmitter WG WR-10-flange. Thus, the sensor offers a 55-dB dynamic range at a 2-m position with an expectation of a long-distance target-detection range. The radar sensor has an 11.7-cm range resolution and is only $60\times 40\times $ 8 mm3 in size, with a weight of only 78 g. [ABSTRACT FROM AUTHOR]

This work introduces a bang-bang fractional- $N$ phase-locked loop with quantization noise shaping that overcomes the classical noise limit of a standard bang-bang phase detector. An adaptive algorithm, working in the background of the main system, guarantees optimal noise shaping across process and environmental variations. The prototype, implemented in a standard 28-nm CMOS process, has a core area of 0.21 mm2 and achieves an rms jitter (integrated from 1 kHz to 100 MHz) of 69.5 fs for integer- $N$ synthesized channels, 79.7 fs for typical fractional- $N$ channels, and 99.6 fs for near-integer fractional channels with a worst case fractional spur of −51.1 dBc. The power consumption is 10.8 mW, leading to a jitter-power figure of merit of −252.8 dB and −251.6 dB for integer- $N$ and fractional- $N$ channels, respectively. [ABSTRACT FROM AUTHOR]

Satisfying fault ride-through requirements, solar photovoltaic (PV) plant remains connected to the grid even during a fault. With current limiting feature, the plant current during a fault becomes comparable to its rated current. This imposes challenges to conventional local data-based protection methods employed in the relay on PV-side. In such a situation, the selectivity of a protection scheme is crucial for maintaining an uninterrupted supply to customers. In this article, a q-axis component-based protection scheme is proposed for the distribution system with a PV plant. The method extracts the second-order harmonic components of q-axis voltage and current at relaying point for fault detection and direction identification. Using this direction information at both ends of a line segment to be protected, internal and external faults are discriminated. The performance of the proposed method is tested on 14-bus distribution system for various fault cases. A comparative analysis with existing techniques shows the strength of the proposed method. Hardware-in-loop testing using OPAL-RT simulator as system and Arduino NANO microcontroller as relay validates the performance of the proposed method in real-time. [ABSTRACT FROM AUTHOR]

This paper proposes a nonadaptive error demodulation technique with which to track the amplitude, the phase and the frequency information of the grid voltage for single-phase applications. A nonadaptive comb filter, Lyapunov’s estimation law, and half-cycle moving average filters are exploited in order to reconstruct the fundamental orthogonal components. The proposed nonadaptive Lyapunov filter has good bandpass filtering characteristics, thus allowing the rapid rejection of the dc-offset and the harmonics. The proposed open-loop phase angle deviation algorithm is, moreover, a rescuer as regards estimating the fundamental frequency deviation, signifying that it correctly compensates the estimated amplitude and the phase angle information through the use of a mathematical regression approach under off-nominal frequency conditions. [ABSTRACT FROM AUTHOR]

Insufficient inertia is the paramount challenge in power system transition toward $ 100\%$ converter-based generation. A promising solution to this issue is utilizing distributed virtual inertia (DVI) concept, i.e., releasing energy stored in the dc-link capacitors of power converters employed in the grid following a frequency disturbance. Nevertheless, this method has two drawbacks: $ 1$) the dc-link voltage is not reverted to its reference value after the power mismatch between generation and demand, and $ 2$) it yields instability of a local mode associated with the control system when the converter operates in weak grids. To overcome the aforesaid problems, the conventional DVI loop is modified so as not to affect the outer loop voltage regulator after transient. Moreover, an efficient compensator is presented in this article which eliminates the adverse impact of DVI technique on the converter stability in weak grid connections. The efficacy of proposed control scheme is depicted by simulations in MATLAB. The results illustrate that an improvement of $ 23\%$ is evident in the grid frequency rate of change following a frequency contingency collated with the case in which the DVI loop staying nullified. [ABSTRACT FROM AUTHOR]

This brief presents a low-power, time-to-voltage converter (TVC)-based auto-frequency calibration (AFC) technology for phase-locked loops (PLLs). Instead of using power-hungry counters and finite-state machine (FSM), the proposed AFC uses TVC and comparator circuits to get the frequency information. Relying on a simple digital operable divide-by-3 (O-Div3) circuit, sampling procedure of TVCs is easy to be realized, which avoids the accumulation of multiple reference periods. Meanwhile, reference frequency is reused, that reduces the cost of extra clock. Beyond that, a binary-like search algorithm is proposed without frequency error. The 4.7-6.8-GHz PLL is implemented in 65-nm CMOS process. The total AFC setting time is less than 750 ns under 20-MHz reference, and consumes below 0.1 mW. Simultaneously, the adopted PLL achieves −116.2-dBc/Hz@1MHz phase noise when generating 4.89-GHz output. [ABSTRACT FROM AUTHOR]

Fractional- $N$ frequency synthesizers are characterized by unwanted periodic components in their frequency spectra called spurs. In communications applications, spurs reduce the signal to noise ratio of the system; in clocking they add jitter; in radar and imaging, they can present ghost targets. Some spurs are due to parasitic electromagnetic coupling between components and can be mitigated by careful circuit layout. Others are inherent in the mathematics that describe the system and are best tackled using mathematical approaches. This brief considers spurs that are introduced directly by the divider controller and those that result from distortion of the control signal by nonlinearity in the synthesizer. It summarizes the state of the art in terms of divider controllers that are themselves spur-free and divider controllers that do not produce spurs when used in synthesizers with memoryless polynomial nonlinearities. [ABSTRACT FROM AUTHOR]

The impact of dc-bus voltage control (DVC) on transient synchronization stability of grid-tied inverters operating in grid-feeding mode has been assessed in this brief. A nonlinear quasi-static model magnifying the dynamics of phase-locked loop (PLL) and DVC of grid-tied inverter has been developed first. Following this, the steady-state and transient stability boundaries of the model are analytically characterized and numerically evaluated. The proposed model and the stability assessment method eliminates the inaccuracies associated with the previously developed model which considers the dynamics of PLL alone. [ABSTRACT FROM AUTHOR]

It is well known that grid-feeding converters that synchronize to the grid through a Phase-Locked Loop (PLL) can become unstable after a fault. An often-neglected element that plays an important role in the converter synchronization stability is the PLL frequency limiter. While it slows down the phase change during the fault, the frequency limiter also constrains the error of the PLL input, thus leading to a longer settling time. This letter investigates the mechanism of the converter synchronization stability caused by the frequency limiter and provides a taxonomy to evaluate its impact on the overall system dynamic response. [ABSTRACT FROM AUTHOR]

As the crucial interface of renewable energy integration, the grid-tied inverter is a complicated system with a multi-timescale feature, containing both fast dynamics and slow dynamics that determine the system stability. However, previous researches on stability analysis mainly focus on the slow dynamics without considering the impact of fast dynamics, which may bring to inaccurate stability prediction. In this paper, the impact of fast dynamics on stability is investigated for grid-tied inverter from a physical perspective. Considering the dynamics of the current control loop and network, a two degrees-of-freedom oscillator model is firstly established to extract the fast dynamics separately. The damping torque analysis is then applied to analyze the impact of the extracted fast dynamics on the damping and spring coefficients of slow dynamics. Moreover, based on the fast dynamic analysis, a novel reduced-order model is proposed with the consideration of the dominant characteristics of fast dynamics, which improves the model accuracy without increasing the complexity. Eventually, both numerical evaluations and experiments are performed to validate the proposed analysis method. [ABSTRACT FROM AUTHOR]

An inevitable consequence of the power system transition towards nearly 100% inverter-based resources is the loss of synchronous generators with their associated inertia, frequency, and voltage control mechanisms. Battery energy storage with different converter technologies, due to their fast-ramping capabilities, are expected to address these challenges and replicate functionalities that so far have been provided by conventional generators. This article presents an in-depth dynamic analysis for the impact of grid forming and grid following battery energy storage locations on the frequency metrics. Performance comparisons that account for the interactions between storage technologies and the decrease of regional inertia are also investigated via dynamic simulations for the projected 90% inverter-based generations in Ireland in 2030. The analysis is conducted using a high-fidelity model of the 39 bus system, which was modified in DIgSILENT, to best replicate a real frequency event that occurred in the Irish power system. Finally, the empirical findings provide a new understanding of the optimal placement of grid-scale fast storage technologies to maintain power system security at high renewables. [ABSTRACT FROM AUTHOR]

This article reports a 320-GHz low-jitter and low-reference-spur signal source consisting of an 80-GHz integer- $N$ phase-locked loop (PLL) and a 320-GHz frequency quadrupler. The 80-GHz PLL features a novel dual-path quadrature exclusive-OR (QXOR) technique to cancel the spurs at the reference frequency and its harmonics, enabling low-spur and low-noise phase locking. The proposed phase detector (PD) also enables frequency detection and lock detection (LD), rendering the band-searching to be decoupled from the loop components. Implemented in a 0.13- $\mu \text{m}$ SiGe BiCMOS technology, the proposed signal source shows a −73.1-dBc reference spur, −113.7-dB/Hz phase noise at 1-MHz offset at 40.96 GHz, and −90.3-dB/Hz phase noise at 1-MHz offset at 311.8 GHz. It achieves an integrated jitter of 66.9 fsrms at 40.96 GHz and 122 fsrms (both integrated from 10 kHz to 100 MHz) beyond 300 GHz, with a total division ratio of 512. The LD time is at the microsecond level. The maximum output power is −3.24 dBm, and the power consumption is 372 mW. [ABSTRACT FROM AUTHOR]

This article presents a systematic control design procedure for an active front-end (AFE) converter connected to a power electronics embedded grid. A parametric model of the grid is first identified using the AFE itself to excite the system. This model is then integrated with the AFE one in order to obtain a global system representation. Subsequently, a globally optimized local controller is synthesized for the AFE keeping in consideration the interaction between the converter and the grid. The proposed method is finally tested experimentally, and its performance is compared with a traditional proportional–integral controller in a $dq$ synchronous reference frame. [ABSTRACT FROM AUTHOR]