Search

A theoretical analysis is presented involving electrical characteristics of ferroelectric memory field-effect transistors (FeMFET).

The presence of a space chargein a ferroelectric thin film, in the presence of Schottkey barriers at two electrode/film interfaces, are investigated. Numerical simulation, using Landau-Khalatnikov, theory, is employed.

Strategies are investigated for mapping complete trees, accessed by fixed templates, onto parallel memory systems. Strategies are evaluated with regard to the following criteria: 1) the number of memory conflicts that can occur when a parallel access is performed, 2) the number of elements that can be accessed in parallel, and 3) the complexity of the addressing scheme.

We describe an active optical system that both measures and corrects the aberrations introduced when writing three-dimensional bit-oriented optical memory by a two-photon absorption process. The system uses a ferroelectric liquid-crystal spatial light modulator (FLCSLM) configured as an arbitrary wave-front generator that is reconfigurable at speeds as great as 2.5 kHz. A method of aberration measurement by the FLCSLM wave-front generator is described. The same device is also used to correct the induced aberrations by preshaping the wave fronts with the conjugate phase aberration as well as to scan the focal spot in three dimensions. Experimental results show the correction of both on- and off-axis aberrations, allowing the writing of data at depths as great as 1 mm inside a LiNb[O.sub.3] crystal. OCIS codes: 210.4680, 210.2860, 010.1080, 220.1000, 230.6120.

An procedure is proposed that obtains a minimal average schedule length under three levels of memory hierarchy. The procedure explores instruction-level parallelism (ILP) among instructions, using retiming techniques, combining it with data prefetching in first- and second-level memories.

Basic constraints for feasibility of multilevel (ML) flash memories are examined, with reference to devices programmed by channel hot electron injection.

A new field-effect transistor (FET)-type memory cell with a one-transistor, and two-capacitor (1T2C) is described. Generation of depolarization field in ferroelectric film during data retention is suppressed by polarizing ferroelectric capacitors in opposite directions.

An experimental and theoretical investigation of memory-cell structures that use either natural nitride traps or semiconductor nano-crystals is proposed. Charging/discharging phenomena are examined, and an interpretation of experimental results is presented.

A 2.4Fsquared memory cell technology with a self-aligned-type stacked-surrounding gate transistor (S-SGT) dynamic random access memory (DRAM) is proposed. Why the S-SGT DRAM is a candidate for future ultra-high-density DRAMs is explained.

Research is presented concerning the investigation of the relationships which exist between the dielectric and microstructure properties of epitaxial films of ferroelectric barium titanate.

Among the many features that are implemented in today's microprocessors there are some that have the capability of reducing the execution time via overlapping of different operations. Overlapping of instructions with other instructions, and overlapping of computation with memory activities are the main way in which execution time is reduced. In this paper we will introduce a notion of overlap and its definition, and a few different ways to capture its effects. We will characterize some of the ASCI benchmarks using the overlap and some other quantities related to it. Also, we will present a characterization of the overlap effects using a lower bound derived empirically from measured data. We will conclude by using the lower bound to estimate other components of the overall execution time. Keywords: Performance evaluation; Instruction overlapping; Benchmarking

This research investigates memory latency of cluster-based cache-coherent multiprocessor systems with different interconnection topologies. Each node in a cluster includes a small number of processors and a portion of the shared-memory, which are all connected through a split transaction bus. Each processor has two levels of caches. As the number of processors in a node is small, a snoopy cache coherence protocol is used. Inter-nodes cache coherence is maintained using a directory scheme. Nodes of the cluster are connected through an interconnection network - three networks have been chosen for this work, namely, ring, mesh and hypercube. Trace-driven simulation, driven by application traces from the Stanford SPLASH2 suite, has been developed to evaluate the overall memory latency of this architecture with the selected network topologies. Simulation results show that, the cluster-based multiprocessor system with hypercube topology outperforms those with mesh and ring topologies. Keywords: Memory latency; Cache coherence; Multipressors; Interconnection networks

In this paper, we present a new neural network based cache replacement algorithm called KORA (Khalid Obaidat Replacement Algorithm). The proposed algorithm uses neural network(s) as a kind of directory in order to identify and distinguish between active and inactive cache lines. Such a classification helps to guide the line replacement decisions. This allows our algorithm to provide better cache performance as compared to the conventional LRU (Least Recently Used), MRU (Most Recently Used), and FIFO (First In First Out) replacement policies (Khalid H, Obaidat MS. A novel cache memory controller: algorithm and simulation, Proceedings of the Summer Computer Simulation Conference (SCSC '95), Canada, July, 1995. p. 767-772; Khalid H, Obaidat MS. Near-optimal cache replacement policy for high performance computer systems, revised version. IEEE Transactions On Computers, 1997 (submitted for publication); Khalid H, Obaidat MS. High performance cache memory replacement schemes. Proceedings of the 1995 IEEE International Conference on Electronics, Circuits, and Systems, December, 1995, p. 1-7). Extensive trace-driven simulations were performed for a wide variety of cache configurations using different SPEC92 (Standard Performance Evaluation Corporation) benchmark programs. Simulation results illustrate that KORA can provide substantial improvement in the miss ratio over the conventional algorithms. Our work opens a new dimension for research in the development of new and improved page replacement schemes for virtual memory systems and disk caches. Keywords: Cache memory; Neural networks; Performance evaluation; High performance computing/computers

We revisit memory hierarchy design viewing memory as an inter-operation communication mechanism. We show how dynamically collected information about inter-operation memory communication can be used to improve memory latency. We propose two techniques: (1) Speculative Memory Cloaking, and (2) Speculative Memory Bypassing. In the first technique, we use memory dependence prediction to speculatively identify dependent loads and stores early in the pipeline. These instructions may then communicate prior to address calculation and disambiguation via a fast communication mechanism. In the second technique, we use memory dependence prediction to speculatively transform DEF-store-load-USE dependence chains within the instruction window into DEF-USE ones. As a result, dependent stores and loads are taken off the communication path resulting in further reduction in communication latency. Experimental analysis shows that our methods, on the average, correctly handle 40% (integer) and 19% (floating point) of all memory loads. Moreover, our techniques result in performance improvements of 4.28 % (integer) and 3.20% (floating point) over a highly aggressive, dynamically scheduled processor implementing, naive memory dependence speculation. We also study the value and address locality characteristics of the values our methods correctly handle. We demonstrate that our methods are orthogonal to both address and value prediction.