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As the minimum feature size on an integrated circuit continues to shrink aggressively toward deep submicrometer, the radiation-induced single-event (SE) upset (SEU) has become a prominent concern. Various radiation-hardening-by-design (RHBD) techniques have been developed to achieve a satisfactory SE tolerance for flip-flop (FF) designs. To enable low supply voltage for ICs and overcome the “power wall,” the lowest power consumption of different RHBD techniques to meet the target SEU cross section is studied in this paper. A comparative analysis of three representative RHBD FFs and an unhardened FF fabricated at the 14-/16-nm bulk FinFET CMOS technology generation shows that at least $2\times $ power dissipation reduction may be achieved by using RHBD FFs at appropriate supply voltage without degrading SE tolerance. [ABSTRACT FROM AUTHOR]

A combinational logic family, termed dual-interlocked logic (DIL), designed for single-event transient (SET) mitigation has been fabricated at a 16nm/14nm bulk FinFET technology generation and irradiated with heavy ions. Through both simulation and heavy-ion irradiation, DIL is shown to be robust to both single- and dual-node strikes. Results are compared to cascode voltage switch and standard logic to show the effectiveness of the logic family in mitigating SETs at the gate level. Three exemplar radiation-hardened-by-design synchronous systems using DIL, spatial triple modular redundancy (TMR), and temporal TMR are compared across area, power, delay, and hardness relative to an unhardened baseline system. The system utilizing DIL exhibits desirable tradeoffs compared to spatial and temporal TMRs. [ABSTRACT FROM AUTHOR]

Total-ionizing-dose (TID) irradiation affects the single-event (SE) vulnerability of electronics by changing transistor leakage currents and/or effective threshold voltages ($\text{V}_{T}$). Characterization of SE response of flip-flop (FF) designs in a 14-/16-nm bulk FinFET technology after TID exposure has been carried out with alpha particle irradiations. Results show that SE cross section (SECS) first increase with total dose and then start to decrease after certain dose levels. These transition dose levels for SECS trend depend on supply voltage and FF design due to competing mechanisms associated with n-hit and p-hit SE transient (SET) pulse-widths and feedback loop delay. Similar trends were observed for SET-induced logic errors at high-frequency operations after TID exposure. [ABSTRACT FROM AUTHOR]

Muon-induced single-event upset cross sections are estimated for a 28-nm static random access memory (SRAM) using Monte Carlo simulations informed by ion test results. As an exercise in modeling with limited information, details of the 28-nm SRAM’s cell structure were not used (and not available) to inform choices of device model parameters such as sensitive volume dimensions and efficiencies. Instead, inferences were made based on heavy-ion and proton single event upset data. Volume dimensions were sufficiently small to resolve the charge collection profile resulting from highly localized low linear energy transfer particle strikes. Results are compared to muon experimental data taken at TRIUMF for validation. Rate predictions are made for the 28-nm SRAM using the calibrated model and compared to expected neutron rates. Muon-induced upset rates at sea level for both marginally reduced and significantly reduced electrical biases, as well as rates at 39 000 feet, are predicted to be significantly less than neutron rates in all these environments. This result is consistent with other authors’ efforts in similarly scaled bulk CMOS SRAMs, indicating that the modeling method used is reliable. [ABSTRACT FROM PUBLISHER]

Measured single-event (SE) heavy-ion data for comparable silicon on insulator (SOI) and bulk silicon FinFET D flip-flop (DFF) designs demonstrate a notably greater difference between the SOI and bulk responses, which has commonly been observed. Data show greater than $30\times $ in SE upset (SEU) LET threshold and 3 orders of magnitude decrease in saturated SE cross section for SOI FinFETs when compared to bulk FinFETs. The difference in SEU threshold is shown to be due to the saturation of SE transient (SET) pulsewidths at values that are comparable to feedback-loop delays of DFF design in the SOI technology. The feedback-loop delays in FinFET technologies are significantly impacted by the inherent parasitic capacitance. For the bulk technology, SET pulsewidths do not saturate due to charge collection from the substrate region. [ABSTRACT FROM PUBLISHER]

Novel design techniques for efficient testability are developed and have been implemented in a 14-/16-nm bulk FinFET node technology characterization vehicle. The result of this paper was the measurement of over 300 000 SETs across 12 combinational logic variants and 415 000 SEUs in three D-flip-flop designs over a large test matrix of heavy-ion linear energy transfer, angle of incidence, and supply voltage in only 319 test runs with a total test time of 108 h. A similar-sized data set with equivalent technology coverage, using the traditional serial testing approach as used in previous work, would typically require thousands of test runs and a significant number of additional hours of testing. The methodologies developed in this paper are technology agnostic and have provided the capability to efficiently characterize the radiation-induced response of the 14-/16-nm FinFET technology generation and yielded insights for assessing the feasibility for incorporation in systems requiring radiation resiliency. [ABSTRACT FROM PUBLISHER]

At the gigahertz range of frequencies, contribution of combinational logic upsets has increased significantly to the overall single-event (SE) upset rate (SER) of sequential circuits. Most approaches for modeling and/or predicting logic SER are either pure simulation based or pure experiment based. Simulation-based approaches need a lot of computing power. Experiment-based approaches require fabrication of actual circuits. This paper presents an empirical method that uses experimental data from simple test structures for estimating SE vulnerability of any combinational logic circuit. Estimated logic SEU cross section matches well with the measured logic SEU cross section. Estimated logic SEU cross section results obtained with the proposed method are within $2\times $ average error when compared to the experimentally measured logic SEU cross section. This method only needs to be calibrated once for use at a given technology node. [ABSTRACT FROM PUBLISHER]

Single-event transients (SETs) in 16-/14-nm bulk fin field effect transistor (finFET) logic chains have been measured using a custom-designed test IC. A variety of logic gate chains were designed, and SET pulse widths were obtained across a wide range of supply voltages. In light of the increased SET response at reduced supply voltages, the efficacy of filter-based mitigation is assessed by analyzing the voltage dependence of SET duration against the characteristic electrical inverter delay. [ABSTRACT FROM PUBLISHER]

Integrated circuits fabricated at advanced technology nodes are expected to operate in gigahertz range of frequencies. At these frequencies, single-event transient (SET)-induced errors result in significant increases in single-event (SE) cross section for flip-flop (FF) designs. For FinFET transistors, the physical structure has changed significantly from planar structure. These changes have resulted in significantly less collected charge than that for planar technologies for the same ion strike, leading to shorter SET pulse generation. These results have necessitated the evaluation of SE cross section for FF designs as a function of frequency for accurate SE predictive capability. Circuit-level simulations and heavy-ion experiments were carried out to investigate frequency dependence of SE cross section for a hardened dual-interlocked cell-based FF design with different spacing options in a 16-nm bulk FinFET technology. [ABSTRACT FROM PUBLISHER]

A 20.4 GHz VCO with a tuning range of 610 MHz (3%) was designed and fabricated in a 32 nm CMOS silicon-on-insulator technology. At 36 °C, the VCO achieves an output power of 0.1 dBm and a phase noise of −99 dBc/Hz at 1 MHz offset from the center frequency. TID experiments on the VCO operating at 36 °C, 75 °C, and 100 °C show degradation in frequency, output power, and phase noise. At 100 °C and 500 krad(SiO2), the VCO shows a worst-case degradation of 630 MHz, 4.3 dBm, and 6.1 dBc/Hz in center frequency, output power, and phase noise, respectively. At 36 °C and up to 500 krad(SiO2), the VCO can be retuned to operate at the required center frequency of 20.4 GHz. However, at 100 °C, the combined effects of temperature and TID result in specification failure. The system-level impact of TID-induced degradation on VCO performance is discussed using a phase-locked loop (PLL) as an example application. Measured performance corroborates previous predictions and highlights the importance of combined effects testing for advanced RF design characterization and qualification. [ABSTRACT FROM PUBLISHER]

Total ionizing dose results are provided, showing the effects of different threshold adjust implant processes and irradiation bias conditions of 14-nm FinFETs. Minimal radiation-induced threshold voltage shift across a variety of transistor types is observed. Off-state leakage current of nMOSFET transistors exhibits a strong gate bias dependence, indicating electrostatic gate control of the sub-fin region and the corresponding parasitic conduction path are the largest concern for radiation hardness in FinFET technology. The high- V\textit {th} transistors exhibit the best irradiation performance across all bias conditions, showing a reasonably small change in off-state leakage current and V\textit {th} , while the low- V\textit {th} transistors exhibit a larger change in off-state leakage current. The “ worst-case” bias condition during irradiation for both pull-down and pass-gate nMOSFETs in static random access memory is determined to be the on-state ( V\textit {gs}=V\textit {dd} ). We find the nMOSFET pull-down and pass-gate transistors of the SRAM bit-cell show less radiation-induced degradation due to transistor geometry and channel doping differences than the low- V\textit {th} transistor. Near-threshold operation is presented as a methodology for reducing radiation-induced increases in off-state device leakage current. In a 14-nm FinFET technology, the modeling indicates devices with high channel stop doping show the most robust response to TID allowing stable operation of ring oscillators and the SRAM bit-cell with minimal shift in critical operating characteristics. [ABSTRACT FROM PUBLISHER]

The increasing need for high-speed logic circuits is causing the conventional flip-flop (FF) designs to migrate to differential FF designs. With the small magnitude of input voltages (and the resulting small noise margins) needed for proper operation, sense-amplifier based FF designs (SAFF) are susceptible to single-event effects (SEE). Single event upset (SEU) performance of high-speed SAFF designs is investigated in this paper for 16-nm bulk FinFET CMOS technology. SEU cross-sections for SAFF are evaluated over particle LET, temperature, and operating frequency. Results show significant increases in cross-sections as a function of frequency, but not so for temperature. Results presented in this work can guide designers to harden the SAFF that satisfies their specific circuit SEU error rate constraints. [ABSTRACT FROM PUBLISHER]

In this paper, a variety of flip-flop (FF) designs fabricated in a commercial 28-nm Fully-Depleted Silicon on Insulator (FDSOI) technology are evaluated for their single-event upset performance with ions and pulsed laser experiments. These FF designs consist of unhardened DFF, hardened DFF with stacked transistors in the inverters, and the layout-optimized DFFs. These DFFs were exposed to alpha particles and heavy ions (HIs). None of the hardened DFFs exhibit any errors up to a Linear Energy Transfer (LET) of 50 MeV*cm2/mg under normal irradiation, and a layout-based hardened DFF started to see errors at a LET of 50 MeV*cm2/mg with the tilt angle of 600. The testing data substantiates effective SEU reduction of these hardened designs. Two-photon absorption (TPA) laser experiments were carried to test these DFF designs, and the results showed that pulsed laser may not be a valid tool to evaluate the FFs designed with nano-scale SOI stacked structures. This brings new challenges in laser hardness assurance for RHBD designs. [ABSTRACT FROM PUBLISHER]

A persistent loss-of-lock error was experimentally observed in a 20 nm charge-pump phase-locked loop (PLL). Through circuit modeling and simulation, the observed error was attributed to a non-recoverable off-state leakage increase resulted from two-photon absorption (TPA) laser-induced damage. The laser-induced damage is consistent with results from 28 nm bulk transistors. [ABSTRACT FROM PUBLISHER]

Flip-flop soft errors caused due to direct strikes on flip-flops as well as soft errors caused due to latched transients from combinational logic show frequency dependence. This frequency dependence in the case of high-speed sequential circuits can derate the soft error rate by as much as 5X. Circuit variables, such as voltage, frequency, logic delay, as well as environmental factors, such as particle type and linear energy transfer that affect the frequency dependence are studied. Heavy-ion irradiation of 28-nm sequential circuits shows that the cross-section decreases with frequency for low-LET particles and increases with frequency for higher-LET particles. Competing trends involving combinational logic and flip-flops are shown to be the reason. The voltage dependence of this trend is evaluated. The key insight that emerges from this work is that at sufficiently high frequencies, the cross-section of certain sequential circuits can be lower than that at lower frequencies. Similarly, lowering voltage may not always result in increased soft error rate at certain frequencies. [ABSTRACT FROM PUBLISHER]

Isotropic alpha particle single-event upsets (SEU) in flip-flops are characterized over temperature and voltage supply variations in a 20-nm bulk planar complementary metal-oxide semiconductor (CMOS) process. The decrease of the MOSFET drain current in saturation with respect to increased temperature and reduced supply voltage explains the increased SEU sensitivity of the flip-flop designs. Experimental SEU cross sections from isotropic Americium-241, 5.4-MeV alpha particle show irradiation increases by 30\times on average, and up to orders of magnitude, as a result of increased device temperature and reduced supply voltage. [ABSTRACT FROM PUBLISHER]

The ambipolar-diffusion-with-cutoff (ADC) model is extended to estimate the single-event-induced collected charge for multiple transistors for circuits simulation. The proposed improvement in the model includes both parasitic-bipolar and charge-sharing effects for a given technology. Simulation results indicate excellent agreement between the proposed model and published TCAD data for 130, 90, 65, and 40 nm technology nodes. A comparison between ADC and both rectangular parallelepiped (RPP) and integral rectangular parallelepiped (IRPP) models indicates a 2.7\times and 2.5\times lower error in estimating collected charge when compared with TCAD data. The ADC average error was estimated to be 7.1 fC and for the RPP and IRPP about 19.1 fC and 17.5 fC, respectively, across the technologies for particles with the linear energy transfer range from 1 - 30~\MeV-cm^2/\mg. [ABSTRACT FROM PUBLISHER]

A technique for enhancing the precision of voltage references in an ionizing radiation environment is presented. Radiation-induced mismatch is identified as a fundamental source of error in voltage reference topologies, and chopper offset cancellation is used to mitigate the effect. The efficacy of the proposed technique is demonstrated by irradiating test chips fabricated in a commercial 180-nm process. [ABSTRACT FROM PUBLISHER]

A neural network IC based on a dynamic charge injection is described. The hardware design is space and power efficient, and achieves massive parallelism of analog inner products via charge-based multipliers and spatially distributed summing buses. Basic synaptic cells are constructed of exponential pulse-decay modulation (EPDM) dynamic injection multipliers operating sequentially on propagating signal vectors and locally stored analog weights. Individually adjustable gain controls on each neutron reduce the effects of limited weight dynamic range. A hardware simulator/trainer has been developed which incorporates the physical (nonideal) characteristics of actual circuit components into the training process, thus absorbing nonlinearities and parametric deviations into the macroscopic performance of the network. Results show that charge-based techniques may achieve a high degree of neural density and throughput using standard CMOS processes.

Results are presented from a preliminary study on the effects of weight decay and resolution on the performance of typical three-layer, feedforward neural networks. Two types of decay are investigated, unilateral decay toward the most negative weight (unipolar) and bilateral decay toward the median or zero weight value (bipolar), and compared with Gaussian weight perturbations. This analysis is pertinent to the area of VLSI-based network implementations with analog weight storage. The results show that, if weight decay is unavoidable, bipolar decay achieves an order-of-magnitude better performance than unipolar and that the weight resolution required in actual implementations of feedforward, connectionist hardware is higher than predicted by computer simulations of network responses to random or Gaussian weight perturbations.