Search

A novel silicon carbide (SiC) on silicon (Si) heterojunction lateral double-diffused metal–oxide semiconductor field-effect transistor with p-type buried layer (PBL Si/SiC LDMOS) is proposed in this paper for the first time. The heterojunction has breakdown point transfer (BPT) characteristics, and the BPT terminal technology is used to increase the breakdown voltage (BV) of Si/SiC LDMOS with the deep drain region. In order to further optimize the surface lateral electric field distribution of Si/SiC LDMOS with the deep drain region, the p-type buried layer is introduced in PBL Si/SiC LDMOS. The vertical electric field is optimized by Si/SiC heterojunction and the surface lateral electric field is optimized by the p-type buried layer, which greatly improves the BV of device and alleviates the relationship between BV and specific on-resistance (Ron,sp). Through TCAD simulation, when the drift region length is 20 μm, the BV is significantly improved from 249 V for the conventional Si LDMOS to 440 V for PBL Si/SiC LDMOS, increased by 77%; And the BV is improved from 384 V for Si/SiC LDMOS with the deep drain region to 440 V for the proposed structure, increased by 15%. The figure-of-merit (FOM) of the Si/SiC LDMOS with the deep drain region and PBL Si/SiC LDMOS are 4.26 MW/cm2 and 6.37 MW/cm2, respectively. For the PBL Si/SiC LDMOS with the drift length of 20 μm, the maximum FOM is 6.86 MW/cm2. The PBL Si/SiC LDMOS breaks conventional silicon limit. [ABSTRACT FROM AUTHOR]

In this paper, dual-material dual-gate nanotube TFET (DMDG-NTTFET) is proposed. Dual gates in this regard are of the core–shell type, and dual-gate materials (GM1 and GM2) are used as control gate having work functions of φ tunnel and φ Auxiliary , respectively. The device is further explored with source pocket and various underlap gate lengths. When device characteristics are compared with the conventional NWTFET, significant improvements in ION, IOFF, ION/IOFF, transconductance (gm), recombination rate, and transconductance factor (gm/Id) are observed. The proposed structure also results in improved linearity and tunnelling in the device. The effects of the device variables, such as φ tunnel , φ Auxiliary , source pocket length (L1), gate underlap length (L2), and molar concentration in Si1-xGex (x), on various analog performance indicators, such as transconductance factor (gm/Id), transconductance (gm), unity gain cut-off frequency (fT), intrinsic device delay (τ ), transconductance frequency product ( g m / I d ∗ f T ), and gain–bandwidth product (GBWP), have been investigated. The ION and ION/IOFF in source pocket dual-material dual-gate nanotube TFET (SPDMDG NTTFET) is improved by a factor of 21.11 and 846.12, respectively. The subthreshold slope achieved using the proposed structure is 18.28 mV/decade. [ABSTRACT FROM AUTHOR]

In this work, 100, 200, and 400 nm SiO2 films are deposited on the electrode surface by magnetron sputtering, and the effect of film thickness on the insulation performance of propylene carbonate is studied. We use the Weibull distribution to calculate the breakdown voltage of propylene carbonate under different conditions. Space charge distribution of the liquid is measured based on the Kerr effect. Test results show that the breakdown voltage of propylene carbonate increases from 8.4 to 18.7% with increasing film thickness compared with the case where the SiO2 film is not deposited. Bipolar injection mode of space charge is not affected by the increase of SiO2 film thickness, but the amount of space charge injection is significantly reduced. The thicker the SiO2 film deposited on the electrode surface, the higher the ratio of increasing the breakdown voltage of propylene carbonate, but the smaller the magnitude of the increase. [ABSTRACT FROM AUTHOR]

We report a processing technique to form a surface reinforcement layer (SRL) in GaN metal-insulator-semiconductor high-electron mobility transistors (MIS-HEMTs) with the aim to suppress device dynamic on-resistance (RON) degradation caused by long-term hot-electron stress. The SRL is a crystalline (Al)GaON layer formed by reconstruction of the heterojunction surface through plasma oxidation and high temperature annealing. MIS-HEMTs with SRL exhibit substantially suppressed dynamic RON degradation than the conventional devices without SRL, after long-term hot-electron stress. The (Al)GaON SRL exhibits substantially enhanced thermal stability and strong immunity to energetic carriers. The SRL-enabled suppression of hot-electron-induced degradation is further verified by the electroluminescence characterizations. [ABSTRACT FROM AUTHOR]

The aim of this paper is to bring forward a novel hetero-material electrically doped (ED) GAA TFET for high-performing and power efficient mixed signal applications. A number of low and high band gap III–V semiconductors were considered at source and drain channel regions, and their electrical characteristics were compared to identify the best alternative. To that end, DC/RF/linearity properties of AlGaSb/GaAsP, Ge/GaAs, Si/GaAs, Si/Ge, Silicon and SiGe/Si based ED GAA TFETs were analyzed. We found that the AlGaSb/GaAs-ED-TFET provides 16 μ A ON current at 25 mV/decade subthreshold swing and 1e13 I ON / I OFF ratio with exceptional analog and linearity characteristics. Also, we found that interface trap charges (ITC) in AlGaSb/GaAs-ED-TFET present negligible impact and have no effect on system performance. Further, improvisation is possible through mole fraction optimization of A l x G a 1 - x S b . Finally, the mixed signal components that are widely available in system architectures are implemented using AlGaSb/GaAs-ED-TFET and their performance criteria are measured. All device simulations were performed using the TCAD Silvaco tool, and look-up based Verilog-A technique was used for circuit simulation in Cadence. [ABSTRACT FROM AUTHOR]

A recessed-source (RS) negative capacitance (NC) gate-all-around (GAA) tunneling field effect transistor (RS-NCGAATFET) was proposed to achieve low power consumption and high performance. An additional RS allowed easy control of the operation of the NCGAATFET by both lateral and vertical band-to-band tunneling. Furthermore, the RS enhanced the driving ability and capacitance characteristics of the transistor. A silicon–germanium (Si/Ge) heterojunction was used to further improve the driving ability. The direct current (DC) and capacitance characteristics of the RS-NCGAATFET were regulated and optimized by adjusting the volume of RS and the thickness of the ferroelectric layer. Sentaurus technology computer-aided (TCAD) design simulations demonstrated that at a subthreshold slope of 31.37 mV/decade, the RS-NCGAATFET achieved a switching current ratio of 107, along with a driving current of 8.31 μA, a transconductance of 3.76 × 10−5 S, and a threshold voltage of 0.30 V. [ABSTRACT FROM AUTHOR]

Hysteresis-free and steep subthreshold swing (SS) are essential for low-power reliable electronics. Herein, MoS2 metal semiconductor field-effect transistors are fabricated with GeSe/MoS2 van der Waals Schottky junction as a local gate, in which the rectification behavior of the heterojunction offers the modulation of channel carriers. The trap-free gate interface enables the hysteresis-free characteristics of the transistors, and promises an ideal SS of 64 mV/dec at room temperature. All the devices operate with a low threshold voltage less than −1 V with desirable saturation behavior. An OR logic gate is constructed with the dual-gated MoS2 transistors by varying the back and top gate voltage. The strategy present here is promising for the design of low-power digital electronics based on 2D materials. [ABSTRACT FROM AUTHOR]

In this study, a novel van der Waals (vdW) heterostructure field‐effect transistor (FET) using vdW stacking as next‐generation device architecture is demonstrated. The MoS2/WS2 heterostructure FET exhibits a large improvement in the drain current and field‐effect mobility (from 43.3 to 62.4 cm2 V−1 s−1) compared with single MoS2 FET. Such significant enhancement is mainly due to the charge‐transfer effect. The vdW self‐encapsulation effect in the device channel also helps to reduce the Schottky barrier height from 120 to 52 meV at the contact interface. Finally, the WS2/MoS2/WS2 double heterostructure FETs further boosts the mobility up to 102.5 cm2 V−1 s−1 at room temperature (25 °C) and 169.7 cm2 V−1 s−1 at 30 K. The much higher mobility exhibited at the lower temperature indicates the suppression of Coulomb scattering. Thus the electrical performance of the double‐heterostructure FETs can be further enhanced. [ABSTRACT FROM AUTHOR]

A predictive algorithm for accurately determining the crosstalk peaks caused by SiC MOSFETs is proposed in this article, which is very important to better design the drive and protect circuits of SiC MOSFETs. Compared to the conventional algorithm of crosstalk peaks, the nonlinearity of gate-drain capacitance (Cgd) is first considered in the proposed algorithm. In detail, the differential expression of the crosstalk peaks is deduced, in which, the main factors affecting crosstalk peaks are all included. Following, the execution flow of the predictive algorithm is provided according to the differential expression. To verify the accuracy of the proposed algorithm with considering the nonlinearity of Cgd, the simulation and experiment platforms are established and verified by using Kelvin packaged SiC MOSFET IMZ120R045M1 (1200 V/52 A). The calculation results of the proposed algorithm are compared with the conventional algorithm without considering the nonlinearity of Cgd under different working conditions of SiC MOSFET. Finally, the calculation results, the simulation, and experiment results show that the proposed algorithm is effective and has better accuracy. Therefore, the predictive algorithm proposed in this article provides a theoretical reference to better design the drive and protect circuits of SiC MOSFETs. [ABSTRACT FROM AUTHOR]

This paper reports on the fabrication of an enhancement-mode AlGaN/GaN metal-insulator-semiconductor-high electron mobility transistor with a new barrier epi-layer design based on double Al0.2Ga0.8N barrier layers separated by a thin GaN layer. Normally-off transistors are achieved with good performances by using digital etching (DE) process for the gate recess. The gate insulator is deposited using two technics: plasma enhance chemical vapour deposition (sample A) and atomic layer deposition (sample B). Indeed, the two devices present a threshold voltage (Vth) of +0.4 V and +0.9 V respectively with ΔVth about 0.1 V and 0.05 V extracted from the hysteresis gate capacitance measurement, a gate leakage current below 2 × 10−10 A mm−1, an ION/IOFF about 108 and a breakdown voltage of VBR = 150 V and 200 V respectively with 1.5 µm thick buffer layer. All these results are indicating a good barrier surface quality after the gate recess. The DE mechanism is based on chemical dissolution of oxides formed during the first step of DE. Consequently, the process is relatively soft with very low induced physical damages at the barrier layer surface. [ABSTRACT FROM AUTHOR]

Improving material quality is essential for obtaining a high-power device. Surface trapping effects have been present in all HEMT devices, and have significantly impacted the problem of drain-current collapse. In this paper, performance of intentionally non-doped AlGaN|GaN|Si (HEMTs) before and after passivation with SiO2|SiN is investigated. Capacitance-voltage at various temperatures (C–V–T), a drain current–voltage at various gate voltages (Ids–Vds–Vgs), the gate leakage current with various temperatures (Igs–Vgs–T), and the maximum extrinsic transconductance Gmax are measured; all of these measurements show the impact of SiO2|SiN passivation on the performances of AlGaN|GaN|Si HEMTs. [ABSTRACT FROM AUTHOR]

In this article, we demonstrate normally-OFF p-GaN gate high electron mobility transistors (HEMTs) on Si with an ultrahigh breakdown voltage (VBR) and excellent saturation drain current. Benefiting from the optimized material growth of high-resistivity buffer, effective Al2O3 surface passivation with suppressed OFF-state leakage current, and proper management of the electric field on the p-GaN gate edge, the device with a gate–drain distance of 18.5 μm exhibits a VBR of 1344 V at ID of 1 μA/mm with grounded substrates, the highest among all the reported normally-OFF GaN-on-Si transistors. Well-restored high-density 2-D electron gas and efficient gate modulation enable the device with a high IDS,max of 450 mA/mm and a low specific ON-resistance of 3.92 mΩ·cm2. Moreover, a large threshold voltage of 1.6 V (at ID of 10 μA/mm) and a steep subthreshold slope of 66 mV/dec have been achieved, with negligible threshold voltage shift upon long-term forward gate stress at 150 °C. These results illustrate the great potential of p-GaN gate HEMTs on Si for beyond 600-V applications. [ABSTRACT FROM AUTHOR]

The subthreshold swing (SS) of a field-effect transistor (FET) is given by the body factor multiplied by the transport factor and has a limit of 60 mV ⋅ dec−1 at room temperature in the case of the MOSFET. To break this SS limit, the negative-capacitance FET (NC-FET) lowers the body factor by using a ferroelectric film in the gate stack, whereas the cold source FET (CS-FET) and the Dirac source FET (DS-FET) lower the transport factor by introducing an electronic bandgap or manipulating the density of states in the injecting source. In this work, we theoretically and computationally investigate the possibility of FETs with both NC and CS/DS so that both the body and transport factors are lowered simultaneously. The new device physics of the negative-capacitance CS-FET (NCCS-FET) is numerically investigated for 2-D monolayer black phosphorus (ML-BP) FETs with the Hf0.5Zr0.5O3 ferroelectric material in the gate stack. The device characteristics of six different FETs, the conventional MOSFET, CS-FET, DS-FET, NC-FET, NCCS-FET, and NCDS-FET are calculated and compared. Overall, the NCCS-FET achieves an average SS of 30.1 mV ⋅ dec−1 and a minimum SS as low as 7.21 mV⋅ dec−1; its ON–OFF ratio is about four orders of magnitude higher than that of a conventional MOSFET. The combined effects of NC and CS more efficiently decrease power dissipation. [ABSTRACT FROM AUTHOR]

A novel silicon-on-insulator lateral insulated gate bipolar transistor (SOI LIGBT) is proposed in this paper. The proposed device has a P-type buried layer and a partial-SOI layer, which is called the BPSOI-LIGBT. Due to the electric field modulation effect generated by the P-type buried layer and the partial-SOI layer, the proposed structure generates two new peaks in the surface electric field distribution, which can achieve a smaller device size with a higher breakdown voltage. The smaller size of the device is beneficial to the fast switching. The simulation shows that under the same size, the breakdown voltage of the BPSOI LIGBT is 26% higher than that of the conventional partial-SOI LIGBT (PSOI LIGBT), and 84% higher than the traditional SOI LIGBT. When the forward voltage drop is 2.05 V, the turn-off time of the BPSOI LIGBT is 71% shorter than that of the traditional SOI LIGBT. Therefore, the proposed BPSOI LIGBT has a better forward voltage drop and turn-off time trade-off than the traditional SOI LIGBT. In addition, the BPSOI LIGBT effectively relieves the self-heating effect of the traditional SOI LIGBT. [ABSTRACT FROM AUTHOR]

This paper investigates the reliability of a dual metal gate-hetero-material junctionless tunnel FET (DMG-HJLTFET), by using a novel combination of III–V compound semiconducting materials, InAs (lower bandgap) in the source region and GaAs (higher bandgap) in the channel and drain regions. We applied bandgap engineering and dual material gate engineering to improve the linearity metrics and distortion parameters by optimizing an appropriate lower work function tunnel gate toward the source and higher work function supplementary gate toward the drain and compared all the results with SMG (single metal gate)-HJLTFET and Si-JLTFET. The DMG-HJLTFET showed marked improvements in terms of ION, ION/IOFF, SS, g m , g m 3 , VIP2, VIP3, and 1-dB compression point. The input power, IIP3 of DMG-HJLTFET, is 158% greater than SMG-HJLTFET and is 154.7% greater than Si-JLTFET. The distortion power, IMD3 of DMG-HJLTFET, is 171.8% and 20.5% lower than SMG-HJLTFET and Si-JLTFET, respectively, thereby making it suitable for low-power distortion-free wireless communication systems. [ABSTRACT FROM AUTHOR]

Organic electrochemical transistors (OECTs) operate at very low voltages, transduce ions into electronic signals, and reach extremely large transconductance values, making them ideally suited for bio‐sensing applications. However, despite their promising performance, the dependence of their maximum transconductance on device geometry and applied voltages are not correctly captured by current capacitive device models. Here, current scaling laws are revised in the light of a recently developed 2D device model that adequately accounts for drift and diffusion of ions inside the polymer channel. It is shown that the maximum transconductance of the devices is found at the transition between the depletion and accumulation region of the transistors, which as well provides an explanation for the observed shift of the transconductance peak with geometric dimensions and the drain potential. Overall, the results provide a better understanding of the working mechanisms of OECTs, and facilitate design rules to optimize OECT performance further. [ABSTRACT FROM AUTHOR]

Biological environments use ions in charge transport for information transmission. The properties of mixed electronic and ionic conductivity in organic materials make them ideal candidates to transduce physiological information into electronically processable signals. A device proven to be highly successful in measuring such information is the organic electrochemical transistor (OECT). Previous electrophysiological measurements performed using OECTs show superior signal‐to‐noise ratios than electrodes at low frequencies. Subsequent development has significantly improved critical performance parameters such as transconductance and response time. Here, interdigitated‐electrode OECTs are fabricated on flexible substrates, with one such state‐of‐the‐art device achieving a peak transconductance of 139 mS with a 138 µs response time. The devices are implemented into an array with interconnects suitable for micro‐electrocorticographic application and eight architecture variations are compared. The two best‐performing arrays are subject to the full electrophysiological spectrum using prerecorded signals. With frequency filtering, kHz‐scale frequencies with 10 µV‐scale voltages are resolved. This is supported by a novel quantification of the noise, which compares the gate voltage input and drain current output. These results demonstrate that high‐performance OECTs can resolve the full electrophysiological spectrum and suggest that superior signal‐to‐noise ratios could be achieved in high frequency measurements of multiunit activity. [ABSTRACT FROM AUTHOR]

A Ka-band AlGaN/GaN metal–insulator–semiconductor high-electron-mobility transistor (MIS-HEMT) with SiN gate dielectric grown by plasma-enhanced atomic layer deposition (PEALD) is demonstrated. The gate reverse leakage current in a controlled HEMT is reduced by about three orders of magnitude by the PEALD-SiN, contributing to an improved breakdown voltage of 92.5 V (source–drain separation of 2.0~μm) in the fabricated MIS-HEMTs. The MIS-HEMTs also feature small threshold voltage hysteresis in dc transfer and capacitance–voltage characterizations, suggesting a good PEALD-SiN/AlGaN interface. The fabricated MIS-HEMTs deliver a high output power density of 7.16 W/mm and a peak power-added efficiency of 60.3%, respectively, at VDS = 30 V and VDS = 10 V in pulse mode at 28 GHz. PEALD-SiN could be a compelling gate dielectric for fabrication of high-power and high-efficiency MIS-HEMTs. [ABSTRACT FROM AUTHOR]

The performance of ultra-wide bandgap semiconductors like β-Ga2O3 is critically dependent on achieving high average electric fields within the active region of the device. In this article, we show that dielectrics like BaTiO3 with extremely high dielectric constant can provide an efficient field management strategy by improving the uniformity of electric field profile within the gate–drain region of lateral field-effect transistors. Using this strategy, we achieved high average breakdown field of 1.5 and 4 MV/cm at gate–drain spacing (Lgd) of 6 and 0.5~μm, respectively in β-Ga2O3, at a high channel sheet charge density of 1.6 × 1013 cm−2. The high channel charge density along with the high breakdown field enabled a record power figure of merit (Vbr2/RON) of 376 MW/cm2 at a gate–drain spacing of 3~μm. [ABSTRACT FROM AUTHOR]

In this article, we present a computational investigation on nanoscale coaxial-gate negative-capacitance carbon nanotube field-effect transistor (NC CNTFET). The proposed nanodevice is endowed with metal–ferroelectric–metal–insulator–semiconductor (MFMIS) structure. The simulation approach is based on solving self-consistently the nonequilibrium Green’s function formalism with the NC FET electrostatics considering ballistic transport conditions. The computational assessment includes the switching performance and short-channel effects (SCEs) in NC CNTFETs. The negative capacitance behavior of the ferroelectric has been found efficient in boosting the performance of nanoscale CNTFETs in terms of subthreshold swing (SS), drain-induced barrier lowering (DIBL), ON-current, current ratio, and intrinsic delay. In addition, we show the capability of MFMIS configuration in improving the current ratio and SS of CNTFETs with ultrascaled gate lengths. The role of the ferroelectric layer thickness in enhancing the NC CNTFET performance is also studied, where improved performance has been recorded using thicker ferroelectric layer. Achieving high ION/IOFF current ratio, sub-kT SS, and improved immunity against SCEs makes the NC CNTFET as a potential candidate for modern CNT-based nanoelectronics. [ABSTRACT FROM AUTHOR]

Summary: CMOS technology faces fundamental challenges such as frequency and power consumption due to the impossibility of further reducing dimensions. For these reasons, researchers have been thinking replacement of this technology with other technologies such as quantum‐dot cellular automata (QCA) technology. Many studies have been done to design digital circuits using QCA technology. Phase‐frequency detector (PFD) is one of the main blocks in electrical and communication circuits. In this paper, a novel structure for PFDs in QCA technology is proposed. In the proposed design, the novel D flip‐flop (D‐FF) with reset ability is used. The D‐FF is designed by the proposed D latch which is based on nand‐nor‐inverter (NNI) and an inverter gate. This proposed D latch has 22 cells and 0.5 clock cycle latency and 0.018‐μm2 area. The inverter gate of the D‐FF has output signal with high polarization level and lower area than previous inverters, and the NNI gate of the D‐FF is a universal gate. The proposed PFD has 141 cells, 0.17‐μm2 occupied area, and two clock cycle latency that is smaller compared with PFD and is based on common inverter and majority gates. [ABSTRACT FROM AUTHOR]

A SrSnO3 high-frequency field-effect transistor (FET) is demonstrated. The device structure consists of a recessed Schottky-gate FET with a heavily doped cap layer. DC measurements on devices with 0.5- $\mu \text{m}$ gate length and 4- $\mu \text{m}$ source/drain spacing show a maximum drain current of 53 mA/mm and a maximum transconductance of 43.2 mS/mm. Radio frequency (RF) characterization reveals a cut-off frequency, ${f} _{\text {T}}$ , of 1.31 GHz (0.97 GHz) and a maximum oscillation frequency, ${f} _{\text {max}}$ , of 3.25 (3.25) GHz, after (before) de-embedding. These results represent an important advancement in developing perovskite materials for RF applications. [ABSTRACT FROM AUTHOR]

This paper focuses on the effects occurring due to the inclusion of multi-channel titanium nitride (TiN) material in a dual metal gate (DMG) junctionless (JL) thin film transistor. Two nanosheets have been implemented in a JL tri-gate transistor, which is separated by the gate oxide layer and surrounded by the gate layer. The thickness of TiN material placed in between the gate oxide and gate layer helps in tuning the work function of the gate. The comparison has been done between single channel with single metal gate, double channel with single metal gate, double channel with DMG and double channel with DMG and TiN. Strains have been created in the devices by implementing TiN and DMG. An improvement of 31 % in the output current has been obtained using DMG double channel device when compared with single gate single channel device. The comparison has been carried out in Sentaurus technology computer aided design (TCAD). The drift diffusion model, the mobility model, which includes the effects of doping concentration and electric field, the bandgap narrowing model and the Shockley-Read-Hall recombination model have been used to calculate outputs. The proposed structure acquires higher transconductance values than normal tri-gate devices. It has been verified that when varying the TiN thickness, the potential has been tuned. Due to the tuning of the work function, the performance of the device has been improved. [ABSTRACT FROM AUTHOR]

This paper describes a pioneering methodology to design, optimize, and reduce the total gate area of robust Operational Transconductance Amplifiers (OTAs). The Single-Ended Single-Stage (SESS) OTA has been chosen to validate the proposed technique by using the 180 nm planar Complementary Metal-Oxide-Semiconductor (CMOS) Integrated Circuits (ICs) technology. The Electronic Design Automationtool, named iMTGSPICE, was used to design and optimize the SESS OTA. There are several heuristics optimization techniques of Artificial Intelligence to optimize analog and radio-frequency CMOS ICs, but we have selected to use the Genetic Algorithm because it presents the best optimization performance among the other algorithms previously studied. This paper also describes a procedure of converting the Conventional planar MOSFETs (rectangular gate shape) into the Diamond MOSFETs (hexagonal gate shape) with the same electrical performance. Furthermore, it is proposed a procedure to simulate the Diamond MOSFETs (DMs) in the Simulation Program with Integrated Circuit Emphasis (SPICE) because there is still no SPICE model to perform the DM. Additionally, this work proposes a methodology to layout OTAs with Diamond MOSFETs, regarding different values of aspect ratios. The main result of this work reveals a total gate area reduction of approximately 30% of a robust OTA implemented with Diamond MOSFETs, with an alpha angle (α) equal to 45°, with respect to the one observed in the robust OTA implemented with standard MOSFETs, maintaining practically the same electrical performance and robustness. [ABSTRACT FROM AUTHOR]

To investigation the phenomena of negative capacitance, we examined the capacitance–voltage (C–V), conductance–voltage (G/ω–V), and series resistance–voltage (RS–V) properties of Au/n-type GaAs metal–semiconductor (MS) structure in the different temperatures (80–415 K) and + 5 V and − 5 V voltages at 500 kHz. Because metal–semiconductor structures play a crucial role not only for compensating the electronic devices but also in determining different functionalities in nano-structure devices. In the forward bias region (after 1.50 V), capacitance–voltage curves show a negative capacitance behavior. The experimental results obtained showed that the C–V and G/ω–V curves are strong functions of temperature and bias voltage especially in the accumulation region, and also the strong negative capacitance behavior is always accompanied after + 1.5 voltage for capacitance–voltage curves at all temperatures. That is, C–V characteristics are exhibited a behavior transition from the positive to negative value after 1.5 V. As the C values decreases, G/ω increases in the positive voltage region. This negative behavior for C–V curves in the forward bias regions is explainable by considering the losses of interface charge at occupied regions below Fermi level due to impact ionization processes. Also, these behavior values can also be attributed to the increase in the polarization particularly at low temperatures and the introduction of more carriers in the structure. [ABSTRACT FROM AUTHOR]

A generalized transmission line model (TLM) and a compatible numerical method have been proposed to characterize metal-semiconductor contacts that exhibit nonlinear properties. This model and method have been applied to the analysis of Au/Sn/p-HgCdTe contact and have realized determination of related physical parameters by fitting experimental data. Our model's merit of avoiding the overestimation of barrier height active contact area encountered in other methods without TLM scheme is discussed. In addition, only by using this model, the transfer length can be credibly determined in the case of nonlinear contacts. [ABSTRACT FROM AUTHOR]

Infrared nanocrystals are promising building blocks for the design of low-cost infrared sensors. Vertical geometry diode is, among possible geometries, the one that has led to the best performance so far. However, this geometry suffers from a lack of tunability after its fabrication, slowing down possible improvements. Here, we demonstrate gate control on a vertical diode in which the active layer is made of HgTe NCs absorbing in the extended short-wave infrared (2.5 μm). To reach this goal, we take advantage of the electrostatic transparency of graphene, combined with the high capacitance LaF3 ionic glass to design a gate tunable photodiode. The latter behaves as a work function-tunable electrode which lets the gate-induced electric field tune the carrier density within the nanocrystal film. In particular, we show that the gate allows to tune the band profile leading to more efficient charge extraction and thus an enhanced photoresponse (×4 compared to the device with a floating gate). This work also demonstrates that photoelectron extraction can still be improved in the existing diode, by better controlling the doping profile of the stack. [ABSTRACT FROM AUTHOR]

We report on device physics modeling, assisted by experimental measurement results, for all-electronic transduction of resonant electromechanical motion of nanoscale β-Ga2O3 vibrating channel transistors (VCTs), including both direct readout of high frequency transmission current (without frequency down-conversion) and frequency modulation (FM) down-conversion techniques. The β-Ga2O3 VCTs under consideration have fundamental mode resonance frequencies at ∼25 MHz–1 GHz, with quality factors (Qs) of ∼100–5000 and transconductance gm at ∼0.2 nS–5 μS. In analysis of signal transduction with varying device parameters, the transistor's gate trench depth z0 and transconductance gm play key roles in improving the electromechanical coupling and device performance. Reduction of trench depth z0 can engender a major enhancement in readout current. Reducing channel thickness h and increasing channel length L can improve the readout current while downshifting the resonance frequency at the same time. We design β-Ga2O3 VCT with a suspended modulation doped field effect transistor structure for efficient operation in the GHz range. This study paves the way for future engineering of all-electronic transduction and integration of high frequency β-Ga2O3 resonators on chip with β-Ga2O3 electronics and optoelectronics. [ABSTRACT FROM AUTHOR]

We demonstrate industry’s first 300 mm GaN transistor technology and 3-D monolithic heterogeneous integration with Si transistors, enabled by 300 mm GaN metal–organic chemical vapor deposition (MOCVD) epitaxy and 300 mm 3-D layer transfer. The 300 mm GaN technology is a high-k dielectric enhancement-mode GaN nMOS transistor technology on Si(111) substrate. It is capable of excellent characteristics and figure-of-merits (FOM) for realizing energy-efficient, compact power-delivery and RF front-end components such as power-amplifiers, low-noise amplifiers, and RF-switches. Our GaN nMOS transistors show e-mode operation with: 1) high ID,max = 1.5 mA/ μm; 2) low RON of 610 Ω-μm (LG =50 nm); 3) low IOFF of 100 pA/μm (LG = 180 nm), which are significant improvements over GaN HEMT; 4) excellent RF performance: ƒT = 190 GHz, ƒMAX = 300 GHz, power-added efficiency (PAE) = 56% (LG = 50 nm) at mmwave frequency 28 GHz, and PAE = 77% at 5 GHz (LG =180$ nm), significantly better than industry-standard GaAs and Si RF transistors; 5) good RF-switch FOM, RONCOFF = 110 fs; and 6) low noise figure, NFmin = 1.36 dB (ƒ = 28 GHz) and 0.4 dB (ƒ=5$ GHz), all at SoC-compatible voltages. We further demonstrate GaN transistor innovations all integrated on 300 mm Si(111) wafer, including depletion-mode GaN nMOS transistor with high ID = 1.8 mA/μm ; GaN Schottky gate transistor producing high saturated power of 20 dBm ($80μm width) with peak PAE = 57% at 28 GHz; low leakage compact cascode and multigate GaN transistors; and GaN Schottky diodes with ultralow COFF for electrostatic discharge (ESD) protection. The layer-transferred Si transistors, monolithically stacked on top of the GaN transistors by 300 mm 3-D layer transfer, show high drive current performance: 1.0 mA/μm (Si nMOS) and 0.5 mA/μm (Si pMOS). Such a monolithic 3-D Monolithic integration of GaN and Si transistors enables full integration of energy-efficient, truly compact power delivery and RF solutions with CMOS digital signal processing, logic computation and control, memory, and analog circuitries. [ABSTRACT FROM AUTHOR]

We demonstrate a high-performance normally-OFF AlGaN/GaN fin metal–insulator–semiconductor high electron mobility transistor (fin-MISHEMT) on silicon with a low work function metal-source contact ledge (LWFM-SCL). In order to realize the normally-OFF operation, an optimized gate-recessed fin structure is used. The fin structure inherently containing a gate-connected field plate (FP) design improves the breakdown voltage (VBD). Moreover, the LWFM-SCL can improve the device overall ON-resistance (RON) by lowering the gate–source access resistance (Ra). The proposed device with a gate–drain length (LGD) of 7 μm exhibits superior characteristics such as a threshold voltage (VTH) of +1.2 V, maximum drain current (ID, max) of 825 mA/mm, ON-state/OFF-state current (ION/IOFF) ratio of 109–1010, subthreshold swing (SS) of 76 mV/decade, VBD of 810 V, and specific RON (Ron, sp) of 0.63 mΩ ⋅ cm2. It also possesses excellent VTH hysteresis, temperature stability, and dynamic RON characteristics. These results suggest that the proposed device is very suitable for high power switching applications. [ABSTRACT FROM AUTHOR]

This article presents a high‐linearity Ka‐band complementary metal–oxide–semiconductor (CMOS) down‐conversion mixer. The mixer comprises an RF transconductance stage, switching stage, local oscillator buffer, and intermediate frequency (IF) buffer, and employs modified multiple gate transistors for high linearity. The intermodulation and gain characteristics are analyzed, revealing that the proposed IF buffer can enhance the linearity performance without a gain reduction. Implemented in 65‐nm CMOS technology, the proposed mixer consumes 23 mW and occupies a core chip area of 0.54 mm2. The mixer achieves a conversion gain of 9.3 to 11.1 dB, a noise figure of 8.4 to 9.2 dB, and an output third‐order intercept point of 15.6 to 23.6 dBm at an RF frequency of 37 to 41 GHz. [ABSTRACT FROM AUTHOR]

This paper deals with electrostatic behavior of triple-material gate-all-around hetero-junction tunneling field-effect transistors (TMGAA-HJTFET) device. The model is advantageous in apprehending a comparative study with the single-material gate-all-around hetero-junction tunneling field-effect transistors (SMGAA-HJTFET) in terms of surface potential, electric field, drain current, transconductance, and threshold voltage. The surface-potential distribution in partition regions along the channel is solved by using two-dimensional Poisson's equation. By using the drift and diffusion current, drain current is derived, and IOn/IOff ratio of 1011 is gained from analytical modeling and TCAD simulation. Transconductance and threshold voltage are derived from the tunneling current. The proposed model results are validated by the ATLAS TCAD simulation tool. [ABSTRACT FROM AUTHOR]

Diamond is a promising electronic semiconductor candidate that has recently attracted intense interest in the implementation of its superior physical properties in electronic devices. In particular, attention has been focused on the surface transfer doping of diamond, in which the hydrogen-terminated diamond (diamond:H) benefices of a unique conductive two-dimensional hole gas (2DHG) layer at the diamond's sub-surface upon coverage with a suitable surface acceptor. Several diamond:H transistors have been developed. However, their inherent architecture dependence on the diamond:H conductive surface sensitivity to harsh processing environments has been a major barrier to the realization of high-performance devices. Here, we report on a diamond:H transistor structure that incorporates a mutual diamond:H active channel into the hybrid model of a metal-semiconductor field-effect transistor (MESFET) and a self-aligned metal-insulator-semiconductor FET (MISFET) with a common gate connection. The resulting diamond:H hybrid transistor exhibits a beneficial symbiosis that includes the advantages of both the MISFET (a high ON current of 0.8 μA/μm and a low OFF current of ∼10−9 μA/μm) and MESFET (almost an ideal subthreshold swing of 67 mV/dec) performance operations in the same multilayered device. [ABSTRACT FROM AUTHOR]

Roll-to-roll (R2R) printing technologies have been widely adopted in a variety of engineering fields, e.g., organic photovoltaics and flexible electronics, owing to the advantages of cost and throughput. Although a minimum feature size of 100 nm has been demonstrated on R2R systems, the layer to layer registration accuracy (i.e., overlay accuracy) still remains as low as tens of microns, which prevents the fabrication of common electronic and functional devices, such as transistors. To realize the full potential of R2R technologies, the registration accuracy must be improved to match the printing resolution, i.e., 100s nm. To address the issue, we have developed a multi-layer R2R system with multiple-input multiple-output (MIMO) closed-loop control that achieves submicron level alignment precision for large-scale continuous printing processes. The enabling elements in the multi-layer R2R system include: (1) new vision-based alignment algorithm/method, which provides 100s nm position detection capability based on low-cost cameras; and (2) custom-built five-axis compliant roller positioner. Experimental results show that the compliant roller positioner has a ±1 mm range with 100s nm precision in X, Y, and Z axes respectively. For correcting in-plane web errors, the roller positioner can achieve a range of 1 mm with < 1 μm precision, realizing multi-layer R2R printing with submicron overlay accuracy. Based on the new methods, a gate/source-drain multi-layer electrode structure for field-effect transistors (FETs) has been designed and fabricated on a 4-inch PET web, demonstrating better than 1 μm overlay precision in fabricating flexible electronics on a R2R platform for the first time. • The first demonstration of a multi-layer R2R printing system that achieves better than 1 μm overlay accuracy. • The five-axis roller positioner actively corrects position errors with a precision of ±200 nm and ±2 μrad. • The new alignment solution achieves a large detection range (> 1 mm) with high-resolution (10s nm) based on low-cost cameras. • R2R printing of a multi-layer structure, i.e., FETs, was demonstrated on a 4-inch PET web with < 1 μm overlay precision. [ABSTRACT FROM AUTHOR]

This article reports the demonstration and fabrication of 400–600 V, 4H-SiC lateral MOSFETs on 6-in, N+ substrates. The P-top was implanted on an N-drift region to create a single reduced surface field (RESURF) structure to alleviate the electric field on the surface. The different layout methodologies (source-centered and drain-centered) for making lateral MOSFETs are discussed. The process and design split, such as rapid thermal anneal (RTA) temperatures (900 °C and 1000 °C), different channel designs [accumulation-mode (ACCU) and inversion-mode (INV)], and channel lengths were varied and experimentally analyzed to optimize the device performance. It was confirmed that channel components (channel design and channel length) and RTA temperature are the key ingredients to improve the forward characteristic of the lateral MOSFETs. With the gate to drain length (Lgd) of 5~μm , the breakdown voltage of 600 V was achieved with a voltage supporting capability of 120 V/μm. On the other hand, a lateral MOSFET with Lgd of 2.5~μm and with a further reduced channel length (Lch = {0.3 μm), a record specific ON-resistance of 7.7 m Ω-cm21 00.21a0nd breakdown voltage of 450 V were achieved. Device design, layout, fabrication, and electrical characteristics of the 400–600 V, 4H-SiC lateral MOSFETs are discussed and reported. [ABSTRACT FROM AUTHOR]

In this article, we have studied the drain current and transconductance of nMOS fully depleted silicon-on-insulator (FDSOI) transistors operating at low temperature (typically < 20 K) when back gate is forward biased. Humps appear in the current, leading to oscillations of the transconductance with gate voltage, owing to mobility discontinuity due to intersubband scattering, in relation with the 2-D subband structure. The conditions for which these specific features appear in thin-film silicon-on-insulator (SOI) devices have been analyzed, by varying the temperature, drain voltage, silicon channel thickness, and gate length. [ABSTRACT FROM AUTHOR]

In this work, we demonstrate suspended two- and four-terminal field emission devices for high-temperature operation. The planar structures were fabricated with tungsten on a 200-nm silicon nitride membrane. The insulator in the vicinity of the terminals was removed to minimize undesirable Frenkel–Poole emission and increase the resistance of leakage current pathways. The effects of temperatures up to 450 °C on Fowler–Nordheim emission characteristics and parasitic leakage resistance were studied. Turn-on voltages with magnitudes under 15 V that further decreased as a function of increasing temperature for the two-terminal device were reported. Gating at temperatures of 150 °C and 300 °C was shown for the four-terminal device, and corresponding transconductance and cutoff frequency values were computed. [ABSTRACT FROM AUTHOR]

This article presents a simulation study of the impact of variation in temperature on the transfer characteristics and the RF/analog performance like transconductance (${g}_{m}$), gate capacitance (${C}_{gg}$), cutoff frequency (${f}_{t}$), and transconductance frequency product (TFP) of the ferroelectric FinFET (Fe-FinFET). In addition, the impact of temperature on the linearity parameters such as higher order harmonics (${g}_{m2}$ and ${g}_{m3}$), second- and third-order voltage intercept points (VIP2 and VIP3), third-order power-intercept point (IIP3), third-order intermodulation distortion (IMD3), and 1-dB compression point is estimated for wide variation of temperature in the Fe-FinFET. It is seen that temperature has a significant impact on the RF/analog and linearity parameters, and these figure of merits (FoMs) are the functions of temperature. Analysis reports that RF/analog parameters are suppressed, whereas the linearity FoMs are improved as temperature changed from 250 to 350 K. [ABSTRACT FROM AUTHOR]

This study systematically investigates the properties of (i) conductive Si-doped α-(AlxGa1−x)2O3 thin films grown via a third generation mist chemical vapor deposition system and (ii) Schottky diodes (SDs) and metal semiconductor field-effect transistors (MESFETs) fabricated on them. The use of chloro(3-cyanopropyl)dimethylsilane as the Si dopant resulted in conductive thin films in a wide range of Al contents x from 0 to 0.3. The resistivity fluctuated in the range from 0.14 Ω cm to 0.35 Ω cm at x ≤ 0.05 and abruptly increased as x exceeded 0.05. Nevertheless, a resistivity of 1.2 kΩ cm was measurable in an (Al0.3Ga0.7)2O3 film, whose bandgap of 6.22 eV was comparable to that of AlN. All the silver oxide SDs fabricated on these films functioned properly with the rectification ratios up to 105, while the MESFETs showed clear field-effect even in the α-(Al0.3Ga0.7)2O3 film. Interestingly, a linear dependence of barrier heights on ideality factors was obtained in diodes formed between the source and gate electrodes of these transistors despite the differences in the bandgaps. This plot yielded the average or "homogeneous" barrier height of ∼2.0 eV, suggesting that the Fermi level on the AgOy/Si:α-(AlxGa1−x)2O3 interface was pinned at ∼Ec −2.0 eV regardless of the Al content x. [ABSTRACT FROM AUTHOR]

Two-dimensional (2D) semiconductor crystals can be applied to further increase the efficiency and speed of field-effect transistors. Such transistors are free from some of the adverse effects present in the traditional MOS transistors when their size is reduced. In this study, the model of the transistor MOS structure with the channel made of a 2D-crystal is proposed and its charge properties are investigated. The numerical simulation of such characteristics is carried out within the range of variations of the electrophysical properties of 2D-crystals representative of MoSe2, WS2, WSe2, ZrSe2, HfSe2, and PtTe2. The self-consistent correlation between electrophysical parameters of the structure via the chemical potential is found, and the effect of the potential of the field electrode and the gate insulator's capacitance on them is demonstrated. The calculations of the steepness of the transfer characteristic and the voltage gain of such a transistor structure demonstrate that, for the channel made from transition metal dichalcogenides (TMD) with the forbidden gap band falling in the range 0.25–2.1 eV, the magnitudes of these parameters can attain 0.1 mA/V and 1000, respectively. [ABSTRACT FROM AUTHOR]

In this Letter, we report and investigate the temperature dependency of various radio frequency (RF) parameters for a fabricated reconfigurable bandstop filter with vanadium dioxide (VO2) switches measured up to 55 GHz. Here, the insulator-to-metal (ITM) and metal-to-insulator transition (MIT) hysteresis of the VO2 thin film influence on the RF characteristics of the filters is analyzed from 25 °C and 120 °C in heating and cooling. The resonance frequency and maximum insertion loss (IL) stability and sensitivity with temperature variations are explored. It is noticed that increasing the temperature to 50 °C from 25 °C (or decreasing it to 50 °C from 120 °C) will result in a less than 1% fractional frequency shift with respect to the off and on resonance frequencies. The sharp DC conductivity level variations of the VO2 thin film around the transition temperatures translate into sharp effects on the resonance characteristics of the filters. On the contrary, the maximum IL levels are less sensitive to the sharp conductivity changes of DC films around the VO2 transition temperature. A unique behavior is reported when successively heating-up and cooling-down, over and below, respectively, the transition temperature of VO2: the fabricated filter exhibits completely different resonance frequencies. This suggests that in the temperature dependence of the VO2 RF design, the practical use of reconfigurable RF functions has to take into account the history of thermal effects and increase or decrease in the device temperature when crossing the IMT/MIT transition point. [ABSTRACT FROM AUTHOR]

The restacking of stripped two-dimensional material into a van der Waals heterojunction provides a promising technology for high-performance optoelectronic devices. This paper presents a self-driven photodetector composed of p-GaSe/n-MoSe2. The hybrid contact is directly formed between the electrode and the heterojunction, which considerably improves the photovoltaic effect. In addition, the Schottky barrier between the semiconductor and metal electrodes creates a built-in electric field, which enhances the self-driven performance of the device. The as-fabricated photodetector has the high responsivity of 0.169 A W−1 at zero bias and the specific detectivity of 6.6 × 1011 Jones. When bias was applied, a responsivity of 6.81 A W−1 and a specific detectivity of 2.8 × 1013 Jones have also been obtained. This work demonstrates that selenide van der Waals heterojunctions based on two-dimensional materials have great potential for future electronic and optoelectronic applications. [ABSTRACT FROM AUTHOR]

Normally-off AlGaN channel heterostructure field effect transistors (HFETs) have been proposed and investigated numerically by taking advantage of the polarization engineering perspective in III-nitrides. The utilization of polarization-matched InAlN/AlGaN heterostructures shifted the threshold voltage to approximately 1.1 V for an Al0.3Ga0.7N channel HFET. Compared to the AlGaN/GaN HFEF with a low breakdown voltage, the normally-off InAlN/AlGaN HFETs show substantially enhanced breakdown characteristics. Besides, the two-dimensional electron gas (2DEG) mobility in the InAlN/AlGaN HFETs exhibits much less reduction with the increasing temperature than that in the AlGaN/GaN HFET, according to the calculation of electron mobility dominated by alloy disorder scattering and polar optical phonon scattering. As a result, the temperature dependences of the power figures of merit based on the conduction loss consideration in terms of 2DEG mobility variation and Johnson figure of merit show superior potential for polarization-matched InAlN/AlGaN HFETs in high-power and high-frequency electronics applications particularly operating at elevated temperatures. This work provides a useful way for demonstration of normally-off AlGaN channel HFETs and is also helpful for design of future devices, which can be beneficially exploited from polarized III-nitride heterostructures. [ABSTRACT FROM AUTHOR]

In this article, an ultrathin-barrier (UTB) AlGaN/GaN diode featuring metal–insulator–semiconductor (MIS)-gated hybrid anode (MG-HAD) and in situ Si3N4 cap passivation is demonstrated. The intrinsic turn-on voltage (VON) as low as 0.31 V determined by the as-grown AlGaN-barrier thickness (4.9 nm) is obtained and the VON exhibits excellent uniformity. More importantly, benefit from the MIS-gated hybrid anode structure, the UTB MG-HAD features good thermal stability in reverse blocking capability. The device delivers a substantially low leakage less than 1~μm/mm at −300 V at high temperature (HT) up to 200 °C, which is more than 100 × lower than that in the reference device w/o gate dielectric. Besides, the device exhibits respectably improved dynamic characteristics due to the incorporation of in situ Si3N4-cap passivation layer and remote plasma pretreatment (RPP) prior to Al2O3 gate dielectric deposition. The UTB MG-HAD featuring precisely VON modulation and low reverse leakage is of great interest for power electronic applications. [ABSTRACT FROM AUTHOR]

This article reports the first comprehensive analysis of the reliability of hydrogen-terminated diamond metal semiconductor field-effect transistors (MESFETs) submitted to OFF-state stress. We demonstrate that stress induces an increase in ON-resistance and a shift in the threshold voltage, along with a decrease in the transconductance peak value. These effects are ascribed to the generation of defects at the diamond surface and/or in the upper semiconductor layers. The defects are generated both in the access regions and under the gate, and their activation energy is 0.30 eV. [ABSTRACT FROM AUTHOR]

Schottky-barrier field-effect transistors (SBF-ETs) based on 2-D semiconductors had been investigated as a substitute for a conventional metal–oxide–semiconductor field-effect transistor (MOSFET) based on bulk silicon in the field of high-performance (HP) device. Especially, the monolayer SiC has been studied because it has a large band gap, which results in reducing the short-channel effect. In this article, the gate–source/drain underlap-dependent characteristics of HP SBFETs based on monolayer SiC with 5.1- and 4.6-nm gate lengths are investigated through ab initio simulations. The performances of the 5.1-nm monolayer SiC SBFET are degraded by the gate–source/drain underlap. The gate–source/drain underlap, however, shows the different improved performances for the 4.6-nm monolayer SiC SBFET. The gate–source underlap could enhance the ON-current to 2792~μA/μm and the gate–drain underlap can enhance the ON-current to 1754~μA/μm, which all far exceed the International Technology Roadmap for Semiconductors (ITRS) requirement. [ABSTRACT FROM AUTHOR]

The anomalous RF inductive effect in which S21- and S22-parameters rotate clockwise in the lower and upper half-circles, respectively, with increasing the frequency at the high VDS region has been investigated in body contact (BCT) high-resistivity (HR) partially depleted (PD) silicon-on-insulator (SOI) nMOSFETs with a very high aspect ratio of gate finger. The negative output capacitance generated from a substrate current-induced body effect (SCBE) is physically identified for the first time as the origin of the RF inductive effect by deriving the output admittance equation of a body transconductance source in RF equivalent circuit model considering SCBE. The bias-dependent frequency effect that the drain–source conductance and negative capacitance converted from measured S-parameters are largely reduced by higher pole frequency with increasing VDS is clearly explained by admittance equations derived from the SCBE output equivalent circuit. The bias-dependencies of inductive effect parameters related to SCBE are accurately extracted using small-signal equivalent circuit modeling of BCT PD-SOI nMOSFETs. Based on this result, the bias-dependence of S21- and S22-parameters is analyzed in detail. [ABSTRACT FROM AUTHOR]