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We proposed a wide SOA and high reliability 0.35 µm CMOS compatible 100 V dual RESURF LDMOS transistor with low switching loss and low specific on-resistance for automotive applications. This paper describes how much production tolerances for the mask alignment and the net dose of the gate-side P-type buried layer for dual RESURF of the proposed device affect electrical characteristics. TCAD simulations verified that the mask alignment tolerance is ± 50 nm, and the net dose tolerance is ± 40 %, which are possible enough in mass production. Within the range of the tolerances, the device maintains top level characteristics (breakdown voltage BV DS = 132 V and specific on-resistance R on,sp = 150 mΩmm2) with keeping high hot carrier endurance and wide SOA.

In this study, we present a tunable THz band pass filter design, using photo-excited low-loss slotted waveguide in a integrated CMOS compatible technology. The results show a tunable THz-filter capable of 48% of bandwidth dynamic range operation, in a spectral range from 0.55 to 0.90 THz.

We present a concept for a resonant absorber structure featuring high compatibility with CMOS technology in a slab design, which is suitable for integration with slab waveguides. Finite-element simulations were used together with the Transfer-Matrix Method and genetic-algorithm optimization in order to model the optical resonators. These absorbers are based on so-called slab Tamm plasmon (STP) structures. Depending on the slab thickness relative absoptances up to 70 % were achieved for an incident guided slab waveguide mode. Only silicon based materials are used in the design of the STP absorbers. This facilitates the fabrication process, as metals are omitted in the components of the structure.

For the first time, we conduct theoretical and experimental analysis on the z-axis (out-of-plane direction) acceleration detection of the micro thermal convective accelerometer (MTCA). Instead of using the complex assembling method to make an out-of-plane detection structure, an indirect way to measure the z-axis acceleration is proposed. The mechanism is proposed with the evidence that the sum of the upstream and downstream detectors’ temperature keeps the same under in-plane acceleration, while their differential output keeps constant with the out-of-plane (z-axis) acceleration. By means of monitoring the variation of temperature of in-plane detectors under out-of-plane acceleration, the z-axis acceleration could be indirectly sensed. Theoretically, the coupling error on z-axis induced by x-axis is quite small (less than 1%). Through this method, it could be easy to convert a single-axis (X) MTCA to a two-axis (X-Z) MTCA, which is also promising to improve the two-axis (X-Y) MTCA to a tri-axis (X-Y-Z) accelerometer. In addition, an MTCA is fabricated based on a CMOS compatible fabrication method and demonstrate the proposed detection mechanism with high sensitivity for both x-axis (1211μV/g) and z-axis (402μV/g).

We report the first demonstration of the O-band quantum dot semiconductor optical amplifier (QD-SOA) that is directly grown on CMOS compatible on-axis silicon substrate. The QD-SOA has a length of 3600 μm, tapered from 4 μm to 5.5 μm, which can offer 29 dB on-chip gain and 22.8 dBm saturation output power with a minimum 7 dB fiber to fiber noise figure.

Highlights from Silicon Device Physics, material sciences and electrical engineering are among the first results to be presented from GFs subcontracts in the IPCEI-project, namely a reconfigurable FET compatible with 22-FDX-technology, a CMOS compatible new material Si doped HfO 2 for electrocaloric/ pyroelectric effects on chip, modelling of the 22FDX devices in the higher GHz range and first 5G Dual Band transceiver blocks designed in 22FDX

In this work, we describe our recent work on hybrid Photonic Crystal lasers. By combining high performance gain chips with silicon-based nanostructures, lasers can be created which have properties that cannot be realized using monolithic devices. Laser cavities that are comprised of very different materials can be realized and are suitable for the implementation of cost-effective light sources that exhibit high side-mode suppression ratios and output powers in the milliwatt range. As an illustration of the potential of this architecture, examples are presented that show an athermal wavelength response can be achieved at a range of operating temperatures with the use of active cooling.

Integrated optical isolators to date have relied on bonded magnetic materials for isolation > 30 dB. However, such materials are incompatible with CMOS processes. We propose a tandem ring modulators to achieve high-isolation and a small footprint. It uses plasma dispersion effect, thus achieving low-insertion loss and high-speed modulation.

CMOS compatible silicon-rich-nitride (SRN) with high reflective index is deposited by plasma enhanced chemical vapor deposition. The Kerr nonlinearity n2 of SRN waveguide is measured and extracted with a value of 2.8×10−17 m2W−1, which is one order of magnitude higher than Si waveguides.

We demonstrate the first integrated photonic physical unclonable function in CMOS compatible highly nonlinear hydrogenated amorphous silicon. We characterize the unclonability of our devices using spectrally-encoded optical pulses for challenge-response authentication.

Electrical properties of CMOS-compatible titanium contacts on n-InP and p-In0.53Ga0.47As using 300 mm tools, in the scope of integrating them on III-V / Si hybrid lasers, are presented. Electrical behaviors after i) processing, ii) integration and back-end sequences, and iii) several simulated laser uses were investigated.

With CMOS device scaling slowing down, exploring new devices' working principles becomes paramount. The electron spin, as a complement to the charge, attracts much attention. The electron spin is characterized by the two well-defined projections on a given axis and is suitable for digital applications. Magnetic tunnel junctions (MTJs) feature different resistances in parallel and antiparallel magnetization configuration and enable spin-based types of non-volatile magnetic memories. MTJs are quite CMOS compatible as they are fabricated with a CMOS-friendly process. The relative magnetization configuration is manipulated by means of a spin-transfer torque (STT) acting on the free layer. The electrically addressable non-volatile STT memory is nearing mass production for stand-alone and embedded applications. The current status and modeling approaches of state-of-the art STT and spin-orbit torque memory are briefly reviewed.

Memristive systems are among the emerging technologies that hold a great promise. They are compact, CMOS compatible, easy to fabricate and can serve for storage as well as computation purposes. Adders are one of the most basic and critical building blocks of any computing system. One of the main application areas of memristors is in Material Implication (IMPLY) based logic. IMPLY-based adders are implemented either in serial, which has a compact implementation but needs many steps for calculation, or in parallel, which is fast, however, requires a large number of memristors. In this paper we propose an IMPLY-based adder topology and its respective addition algorithm which is 54-to-65% faster than serial adders and requires 46-to-76% less memristors than parallel adders. This topology is a favorable candidate for applications where neither speed, nor cost (i.e., area or number of memristors) could be compromised to gain the required performance.

Silicon nanowires (SiNWs) represent new opportunities for developing electrical biosensors due to their inherent properties, including large surface-to-volume ratio, rapid signal response and nanoscale footprint comparable to biomolecular and subcellular structures. Still, fabrication of nanosized electrodes is time-consuming, pricey and might be only scarcely compatible with the Complementary-Metal-Oxide-Semiconductor integrated circuits (CMOS-IC) technology. To take a step forward, we introduced an innovative approach to fabricate small, high-density SiNWs with a low-temperature (200 °C) and CMOS-compatible method. In this work, the fabrication process and the preliminary results showing biocompatibility and neutrality of SiNWs used as seeding substrate for cultured cells are presented.

The insatiable demand for digital information has led to the introduction and increasing adaptation of Silicon Photonics in digital communications to replace the much slower copper wires wherever possible. While most of today’s Silicon Photonics solutions are being manufactured using hybrid (no CMOS devices) integration, there is an increasing need to offer full integrated solutions (CMOS and Photonics) to improve system level performance and drive overall costs down. In this paper we’ll describe the challenges and innovative solutions used to develop and ultimately integrate a high performance Germanium (Ge) photodiode (PD) into a 90nm CMOS compatible process flow to provide a full monolithic Silicon Photonics solution.

In this work we demonstrate InGaAs-on-Insulator FinFETs monolithically integrated on silicon substrate using selective epitaxy in oxide cavities. Scaled FinFETs, with a gate length down to 20 nm, are fabricated following a CMOS compatible process scheme including replacement meta gate (RMG). The difference between RMG and gate-first (GF) process flows on device performance is discussed. The implementation of an RMG scheme enabled improved off-state behavior, with a 50% reduction of the subthreshold slope. RMG FinFETs with L G = 90 nm and WFIN = 40 nm, show competitive performance, and on-current of 100 µA/µm at fixed off-current of 100 nA/µm.

We investigate titanium nitride (TiN) thin film coatings on silicon for CMOS-compatible sub-bandgap charge separation upon incident illumination, which is a key feature in the vast field of on-chip photodetection and related integrated photonic devices. Titanium nitride of tunable oxidation distributions serves as an adjustable broadband light absorber with high mechanical robustness and strong chemical resistivity. Backside-illuminated TiN on p-type Si (pSi) constitutes a self-powered and refractory alternative for photodetection, providing a photoresponsivity of about ∼1 mA/W at 1250 nm and zero bias while outperforming conventional metal coatings such as gold (Au). Our study discloses that the enhanced photoresponse of TiN/pSi in the near-infrared spectral range is directly linked to trap states in an ultrathin TiO2–x interfacial interlayer that forms between TiN and Si. We show that a pSi substrate in conjunction with a few nanometer thick amorphous TiO2–x film can serve as a platform for photocurrent enhancement of various other metals such as Au and Ti. Moreover, the photoresponse of Au on a TiO2–x/pSi platform can be increased to about 4 mA/W under 0.45 V reverse bias at 1250 nm, allowing for controlled photoswitching. A clear deviation from the typically assumed Fowler-like response is observed, and an alternative mechanism is proposed to account for the metal/semiconductor TiO2–x interlayer, capable of facilitating hole transport.

The ICs for Artificial Intelligence and Internet of Things (AI/IoT) as strong driving force for future IC industry need massive capabilities as well as rapid development/manufacturing cycles. Thus, the IC development for AI/IoT shall have systematic methodology for concurrent engineering and multi-level co-optimization among process/design/system in order to achieve high performance, good yield, reliability, and fast time-to-market. Most BEOL based specialty devices/process and 3DIC/SIP are CMOS compatible; thus, they are highly preferred to be integrated with CMOS FEOL platform for fast IC development in AI/IoT era. Further, traditional IDMs or Foundries (“virtual-IDM”) are increasingly incapable of providing effective environment for co-optimization among logic platforms (i.e. CMOS, SOI, FinFET) and concurrent design among IPs and circuit designers. Instead, product focused foundry (referred to as Commune-IDM, or “C-IDM”) with Process, Design, System partners closely together in organization can effectively share resources and data in “cloud” platform can be much more effective and superior (than IDM or “virtual-IDM”) toward fast development and manufacturing of IC in AI/IoT era.

In this paper we introduce a field diagnostic device based on the combination of advanced bio-sensing and photonics technologies, to tackle emerging and endemic viruses causing swine epidemics, and consequently significant economic damage in farms. The device is based on the use of microring resonators fabricated in silicon nitride with CMOS compatible techniques. In the paper, the designed and fabricated photonic integrated circuit (PIC) sensors are presented and characterized, showing an optimized performance in terms of optical losses (30 dB per ring) and extinction ration for ring resonances (15 dB). Furthermore, the results of an experiment for porcine circovirus 2 (PCV2) detection by using the developed biosensors are presented. Positive detection for different virus concentrations has been obtained. The device is currently under development in the framework of the EU Commission co-funded project SWINOSTICS.

This paper presents, a 16 x 16 programmable analog vector matrix multiplier (VMM) with CMOS compatible floating gate device that used as nonvolatile storage for the weight matrix values. Each weight matrix value is stored in single-poly floating gate, changes p-type MOSFET gate voltage. Current summation method is used for sum of vector calculation, that correlation between input and weight. The vector matrix multiplier simulated based on 180-nm CMOS fabrication successfully.

Odor sensing has been applied in many fields, such as environmental monitoring, health care, and medical diagnosis. However, traditional gas-sensing systems have critical drawbacks, particularly regarding their miniaturization. An electronic nose system is a suitable alternative to traditional gas-sensing systems because the nose system employs a gas sensor array to detect and identify different odors. Accordingly, this study designed a nose-on-a-chip by using the electronic nose concept through complementary metal–oxide–semiconductor (CMOS) technology for minimizing the device size and reducing power consumption. The chip incorporates a CMOS-compatible gas sensor array along with other electronic components that are used for signal processing and data analysis. Assessment results revealed the ability of the proposed nose-on-a-chip in executing various processes such as diagnosing ventilator-associated pneumonia. Hence, the CMOS-compatible miniature gas-sensing system is a promising candidate for use in devices intended for personal use.

The integration of both second and third order nonlinearities in CMOS compatible platform can open new opportunities for integrated nonlinear optics. In this talk, we will cover recent work on optically inducing second order nonlinearity in silicon nitride waveguides and the characterization of the effect.

We demonstrate RF-compatible quantum well InGaAs MOSFETs integrated on Si substrates, with $L_{\mathrm{G}}$ down to 14 nm and a Si CMOS compatible RMG fabrication flow. Devices exhibit simultaneously extrapolated $f_{\mathrm{t}}$ and $f_{\max}$ of 370 and 310 GHz, respectively, the highest reported combined $f_{\mathrm{t}}/f_{\max}$ for III-V MOSFETs on Si. This is enabled by the scaled $L_{\mathrm{G}},\ g_{\mathrm{m}}$ of $1.75\ \text{mS}/\mu \mathrm{n}$ , 8 nm source and drain spacers and raised source and drain extensions maintaining low access resistance. The use of the InP/In 0.75 Ga 0.25 As/InP quantum well offers three times higher electron mobility and a 60% increase of $g_{\mathrm{m}}$ , compared to reference devices.

We report a novel way of fabricating a large area dielectric metasurface on a flexible substrate using template stripped technique. The dielectric metasurface which consisted of high index Si nanoparticle arrays, exhibits strong narrow optical resonances in near IR (~ 830 nm) with a Q-factor as large as 100. The dielectric material platform is low loss and CMOS compatible which together could be promising for applications in the field of integrated flexible opto-electronics and adaptive photonic systems.

A high-K/metal gate (HKMG)-stack (TiN/Al-doped-HfO x /SiO2/Si)-based bipolar resistive random access memory (RRAM) cell is proposed and fabricated by 28/20-nm HKMG CMOS compatible technology. Robust reliability behaviors (retention at $200~ {^{\circ }}\text {C} > 4 \times 10^{4}$ s and endurance $> 10^{{{5^{\vphantom {\frac {}{,}}}}}}$ cycles) and ultralow switching current ( $ for RESET and $ for SET) are both demonstrated. The sub- $\mu \text{A}$ switching current and self-selection nonlinear $I$ – $V$ characteristics are attributed to the SiO2 interfacial layer rather than the decrease of conductive filament size and oxygen vacancy ( $V_{O}$ ) density, which can be verified by HRTEM and measured conduction behavior. Therefore, robust reliability property is also achieved. The demonstrated excellent memory characteristics of HKMG stacked RRAM cell enable constituting 1-Mb workable crosspoint array even though the feature size scales down to 10 nm according to the HSPICE simulation.

Sources of single photons are one of the key building blocks for quantum photonic technologies such as quantum secure communication and powerful quantum computing. To bring the proof-of-principle demonstration of these technologies from the laboratory to the real world, complementary metal–oxide–semiconductor (CMOS)-compatible photonic chips are highly desirable for photon generation, manipulation, processing and even detection because of their compactness, scalability, robustness, and the potential for integration with electronics. In this paper, we review the development of photonic devices made from materials (e.g., silicon) and processes that are compatible with CMOS fabrication facilities for the generation of single photons.

Novel materials are being aggressively researched for integration in high-k/metal gate CMOS technology, as innovations in the gate stacks are necessary to sustain scaling toward the end of the roadmap. In this paper, we discuss thulium silicate as a candidate dielectric for integration as interfacial layer, focusing on compatibility with the requirements in terms of both process integration and effects on electrical device characteristics. In particular, we demonstrate that thulium silicate provides advantages over conventional chemical oxide interfacial layers in terms of scalability and channel mobility.

We report CMOS-compatible $n$ -channel InGaAs-on-insulator FinFETs obtained using a replacement metal gate fabrication flow. The fabricated devices feature 12-nm-thick SiNx spacers, a scaled high- $k$ /metal gate (capacitance equivalent thickness of $\sim 1.5$ nm), raised source and drain doped to $\sim 6\times 10^{19}$ /cm3, and fin width scaled down to 15 nm. Very good control of short-channel effects is demonstrated down to a gate length of 50 nm with a minimum subthreshold swing of 92 mV/decade at $V_{DS}=0.5$ V and a drain-induced barrier lowering of 57 mV/V. An ON-state current ( $I_{{\textit {ON}}})$ of 156 $\mu \text{A}/\mu \text{m}$ is also reported for a supply voltage of 0.5 V and a fixed OFF-state current of 100 nA/ $\mu \text{m}$ . This $I_{ON}$ value is the highest reported to date for CMOS-compatible InGaAs devices integrated on Si.

Heterogeneous integration of gallium nitride (GaN) film on complementary metal-oxide-semiconductor (CMOS)-compatible Si(100) substrate provides a material platform for future high-performance chips with multiple functions. In this work, a 2 inch wafer-scale single-crystalline GaN film is transferred from commercialized bulk GaN wafer onto Si(100) substrate by combining ion-slicing and modified surface-activated bonding with a sputtering-deposited Si nanolayer. The H+ implantation fluence for the exfoliation of GaN film is as low as 2.5 × 1017 cm−2 and the full width at half maximum of the (0002) x-ray rocking curve of GaN film is 203 arcsec. The sliced bulk GaN wafer is recycled, which is beneficial to reduce the cost and to enhance the mass application of the ion-cutting technique to GaN. The exfoliation mechanism of H-implanted GaN is investigated. The activation energy for slicing GaN is only 2.08 eV owing to the high quality of the GaN wafer, while the wide residual damage band is still an obstacle to improving the quality of the GaN film. The successful demonstration of wafer-scale single-crystalline GaN film on Si(100) substrate will be of great benefit to the integration of high-performance GaN devices and Si CMOS integrated circuits with mature processing technology.

Self-catalyzed horizontal nanowires (NWs) can greatly simplify the CMOS integration processing compared with the regular vertical counterparts. However, self-catalyzed growth mode poses challenges in manipulating the droplets to produce single-crystalline horizontal NWs with a uniform diameter. Here, we demonstrated a novel method to manipulate the droplet through altering the droplet surface energy. Ga-droplet was successfully moved from top to sidewalls in GaAsP NWs by introducing Be and lowering the surface energy, and pinned at the tip despite the absence of planar defects. This can switch the growth direction, with a successful rate of 100 %, from vertical to horizontal through the assistance of few sparse twins. The produced NWs tend to be bounded by low energy facets, which leads to the self-catalysed growth of horizontal NWs with a greatly improved diameter uniformity along the axis. Besides, the lowered surface energy can effectively suppress the wurtzite nucleation, producing pure zinc blende single-crystalline horizontal NWs. This study establishes an essential step toward the efficient integration of NWs into CMOS compatible devices. (C) 2020 Elsevier Ltd. All rights reserved.

For many years the computer industry has relied for progress on the stellar rate of scaling of MOSFETs in integrated circuits. The usual expectation, based on Moore's law, is that the number of transistors packed on a chip doubles every eighteen months. Sustaining this pace requires aggressive research into the numerous bottlenecks that threaten to slow it down. In the past decade, an issue has emerged that threatens to impose an absolute limit on how many transistors can be packed onto a die. This is the issue of heat dissipation. The persistent down-scaling of nanostructures, electronic devices, sensors, and NEMS increases the surface-to-volume ratio and introduces atomic-scale disorder at boundaries and interfaces, which scatters heat carriers (phonons) and increases thermal resistance. In this invited talk, I will present my recent work on numerical simulation and modeling of heat dissipation and phonon transport in a broad range of nanostructures, focusing primarily on extrinsic and disorder effects such as grain/sample boundaries, interfaces, edges, and alloy mass disorder. The talk revolves around the phonon Boltzmann transport equation (pBTE), while the salient feature of the work is that it employs a full phonon dispersion computed from first principles and combined with a momentum-dependent model of electron and phonon scattering. I will show that the thermoelectric response of SOI and Si-membrane-based nanostructures can be improved by employing the anisotropy of the lattice thermal conductivity, revealed in ultrathin SOI nanostructures due to the interplay between the anisotropy of the phonon dispersion and the strong boundary scattering. Next, I explore the consequences of nanostructuring on silicon/germanium and Si/Si-Ge alloy superlattices, and show that the drastic reduction and high anisotropy of thermal conductivity comes from the increased interaction of lattice waves with rough interfaces and boundaries. I will close the loop with applications of my phonon transport models to thermal effects in ultrascaled gate-all-around and junctionless MOS devices. Going beyond silicon CMOS, two-dimensional (2D) materials have tremendous potential for next-generation nano- and optoelectronics. However, heat dissipation and its removal from hot spots in the monolayer remains a critical concern to the design of 2D-based devices. When a 2D material is supported by a substrate, the interfacial area formed between it and the substrate is often far larger than the lateral source/drain contact area. Thus, the majority of heat is removed across the 2D-substrate interface and then via the substrate. Interfaces formed between 2D vdW materials and 3D substrates are fundamentally different than same-dimension 3D-3D and 2D-2D interfaces due to the presence of a vdW gap and the different dimensionalities of the phase spaces on either side of the interface. In this invited talk, I will review the progress in understanding lattice thermal transport, both in-plane and cross-plane, in 2D mono and few-layer materials. Several recent papers measured the TBC between various monolayers and mostly the silicon dioxide (SiO2) substrate, reporting a wide range of values due to inconsistent sample quality. Therefore, it is imperative to build predictive methods for quantifying the TBC between MLs and various substrates. Here, we use a combination of phonon dispersions from first-principles density functional perturbation theory simulations and our 2D-3D TBC model. We investigate the TBC between combinations of six atomic layers (h-BN, graphene, MoS2, MoSe2, WS2, and WSe2) and six substrates (SiO2, AlN, GaN, 6H-SiC, diamond, and Al2O3). We show that TBC is higher for softer substrates with smaller speed of sound, but of the 6 substrates we compared, amorphous SiO2 consistently produced higher TBC than crystalline substrates. Another route to improving mobility and boosting drive current in 2D devices is to replace the monolayer with few-layered (FL) TMDs. Despite recent advances on demonstrating improved electrical performance of FL TMD FETs, there has been less attention towards their thermal management, which is crucial for modern nanoelectronic devices. We study heat dissipation in FL-WSe2 stacks using a coupled electro-thermal model and Raman thermometry experiments. The resulting rise in temperature is obtained from a FL-TBC model to shed light on self-heating and heat dissipation in such devices. We find that the temperature rise in the top layers is significantly larger than the bottom layers because the bottom layers have higher TBC and conduct heat more efficiently to the substrate. The higher temperature of top layers, in turn, significantly reduces their mobility, causing the electrical current to reroute toward the bottom layers where the TBC is higher. This rerouting improves heat removal and limits mobility degradation. We conclude that the optimal number of layers is 6-9 and that FL TMD devices are inherently thermally resilient.

Atomic precision advanced manufacturing (APAM) is a technique for placing dopant atoms with single atomic-lattice site precision on silicon surfaces. APAM devices are created by patterning the placement of dopants into a two-dimensional sheet of phosphorus atoms on the silicon surface, incorporating the dopants into the lattice, and then capping the device in silicon. The dopant atoms are incorporated into the silicon lattice through a surface-activated chemical reaction, as opposed to a thermally activated bulk process, which allows for electrically active doping above the solubility limit for phosphorus in silicon. The two-order of magnitude higher doping levels and two-dimensional nature of the dopant sheet enable new device physics and the potential for new device types with superior performance under specific tasks. Atomic precision fabrication requires atomically clean surfaces. Historically the APAM technique has required temperatures in excess of 1200 °C to prepare device surfaces, which has severely limited the ability to combine APAM with other manufacturing techniques such as CMOS. Recent work by our group and others has shown that the surface preparation process can be achieved at temperatures near 800 °C, greatly improving integration possibilities with CMOS [1,2]. Once fabricated, APAM devices have low thermal budgets to minimize vertical diffusion of the phosphorus dopants out of the non-equilibrium two-dimensional sheet. Temperatures on the order of 450 °C have been shown to be permissible for long periods of time. In this talk we report on the initial development of a CMOS process flow that incorporates APAM device fabrication. Based on the thermal budget and processing constraints, our basic process flow involves building the APAM device between CMOS Front-end-of-line (FEOL) and the CMOS Back-end-of-line (BEOL) steps. This is a natural insertion point based upon both thermal budget limitations and the need to directly access the device silicon to build the APAM device. Borrowing from CMOS nomenclature, we introduce the concept of “APAM select” and “APAM active” to indicate where the window for APAM device patterning will be opened and the actual APAM device area, respectively. These are the only additional mask layers needed to introduce APAM into a CMOS layout cell. An APAM cell was created that has the appropriate source/drain placement and targeting reticle in poly-Si to enable alignment of the APAM lithography tool to the wafer. Two classes of challenges exist in developing a CMOS-APAM process flow. The first is related to the APAM process itself and limitations of current fabrication tools. The APAM surface preparation, patterning, dopant incorporation, and silicon capping all occur in a scanning tunneling microscope (STM). Devices must be processed at the die level to fit into the STM sample holders. Die level processing puts restrictions on the BEOL processing including minimum feature size and available processes, such as a lack of chemical-mechanical polish (CMP) to planarize metal layers. The second class of challenges is related to the impacts of the APAM process, such as surface preparation, on CMOS devices, which has not been previously explored. We discuss our strategy for integration with CMOS, by including test structures to mimic the APAM device, and sequential implementation and testing of the APAM fabrication steps with CMOS chips. We conclude with a discussion of future integration challenges such as wafer level processing of APAM devices in a CMOS foundry flow. Direct integration of APAM components into CMOS circuits opens the door for devices with enhanced functionality. ACKNOWLEDGMENT This work is supported by Sandia’s Lab Directed Research and Development Program, and was performed in part at the Center for Integrated Nanotechnologies, a U.S. DOE Office of Basic Energy Sciences user facility. Sandia National Laboratories is a multimission laboratory managed and operated by National Technology and Engineering Solutions of Sandia, LLC., a wholly owned subsidiary of Honeywell International, Inc., for the U.S. Department of Energy’s National Nuclear Security Administration under contract DE-NA0003525. References [1] T. Skeren, et al., “CMOS platform for atomic-scale device fabrication,” Nanotechnology, vol. 29, pp. 435302, 2018. [2] D. R. Ward, et al., “All-optical lithography process for contacting nanometer precision donor devices,” Appl. Phys. Lett., vol. 111, pp. 193101 (2017).

In this progress review, an overview of the CMOS-compatible contact technology developed at the CEA-Leti for Si photonics applications is proposed. The elaboration of III–V/Si hybrid lasers implies the development of ohmic contacts on n-InP and p-InGaAs III–V materials. In this way, a contact technology fully compatible with a Si-Fab line was developed. The results presented in this manuscript cover a wide scope: from surface preparation and solid-state reaction to electrical results and integration guidelines. The metallurgy of several systems including Ni/InGaAs, Ni/InP, Ti/InGaAs and Ti/InP was studied. The direct metallization of III–V materials using Ni2P was also introduced. Most of the studied metallizations provided efficient solutions for achieving ohmic contacts on n-InP and p-InGaAs. Finally, the contact technology developed in the framework of this study was successfully integrated on 200 mm CMOS-compatible III–V/Si hybrid lasers.

III–V quantum dot (QD) lasers monolithically grown on CMOS-compatible Si substrates are considered as essential components for integrated silicon photonic circuits. However, epitaxial growth of III–V materials on Si substrates encounters three obstacles: mismatch defects, antiphase boundaries (APBs), and thermal cracks. We study the evolution of the structures on U-shaped trench-patterned Si (001) substrates with various trench orientations by homoepitaxy and the subsequent heteroepitaxial growth of GaAs film. The results show that the formation of (111)-faceted hollow structures on patterned Si (001) substrates with trenches oriented along [110] direction can effectively reduce the defect density and thermal stress in the GaAs/Si epilayers. The (111)-faceted silicon hollow structure can act as a promising platform for the direct growth of III–V materials for silicon based optoelectronic applications.

In this work, we demonstrate the simple fabrication process of AlN-based piezoelectric energy harvesters (PEH), which are made of cantilevers consisting of a multilayer ion beam-assisted deposition. The preferentially (001) orientated AlN thin films possess exceptionally high piezoelectric coefficients d33 of (7.33 &plusmn, 0.08) pC∙N&minus, 1. The fabrication of PEH was completed using just three lithography steps, conventional silicon substrate with full control of the cantilever thickness, in addition to the thickness of the proof mass. As the AlN deposition was conducted at a temperature of &asymp, 330 &deg, C, the process can be implemented into standard complementary metal oxide semiconductor (CMOS) technology, as well as the CMOS wafer post-processing. The PEH cantilever deflection and efficiency were characterized using both laser interferometry, and a vibration shaker, respectively. This technology could become a core feature for future CMOS-based energy harvesters.