151. Assessment of distributed-cycling schemes on 45nm NOR flash memory arrays
- Author
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S. Beltrami, Andrea L. Lacaita, Christian Monzio Compagnoni, Luca Chiavarone, Angelo Visconti, Alessandro S. Spinelli, and Carmine Miccoli
- Subjects
Engineering ,sezele ,business.industry ,Semiconductor device modeling ,Electrical engineering ,Flash memory ,Threshold voltage ,Superposition principle ,Reliability (semiconductor) ,Nanoelectronics ,Logic gate ,Electronic engineering ,Node (circuits) ,business - Abstract
This paper investigates the validity of distributed-cycling schemes on scaled Flash memory technologies. These schemes rely on the possibility to emulate on-field device operation by increasing the cycling temperature according to an Arrhenius law, but the assessment of the activation energy that has to be used on scaled technologies requires a careful control of the experimental tests, preventing spurious second-order effects to emerge. In particular, long gate-stresses required to gather the array threshold voltage (V T ) map are shown to give rise to parasitic V T -drifts, which add to the V T -loss coming from damage recovery during post-cycling bake. When the superposition of the two phenomena is taken into account, the effectiveness of the conventional qualification schemes relying on a 1.1 eV activation energy is fully confirmed at the 45 nm NOR node.
- Published
- 2012
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