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A 300-GHz CMOS transmitter that covers the vast unallocated frequency band above 275 GHz with six channels has recently been reported. It employed a tripler-based subharmonic mixer called the cubic mixer. However, the maximum perchannel data rate was limited to 17.5 Gb/s with 32 QAM because of the interference between the desired signal and the unwanted image signals at approximately 300 GHz, originating from an image of the second intermediate frequency signal, IF2, at around 100 GHz. In this study, we show that the image signals at around 300 GHz can be reduced significantly by using a set of LO frequencies different from that used previously, without impacting the allocation of the six channels. This is accomplished because the image of IF 2 is driven out-of-band of the IF amplifier for IF 2 . As a result, the maximum per-channel data rate reached 21 Gb/s with 64 QAM. The aggregate data rate over six channels is 123 Gb/s.

It is a challenge to design amplifiers operating near the transistor unity-power-gain frequency f max . This paper presents a graphical chart (MAG-K chart) and associated analytic equations for analysis and design of near-/ max gain-boosted feedback amplifiers. The graphical approach provides an efficient means of finding feedback networks that give the highest possible maximum available gain (MAG) for a given stability (K) at a target frequency. This is somewhat analogous to the Smith chart providing an intuitive means of synthesising matching networks. Each of the designs thus found can subsequently be checked for bandwidth and realisability. It is shown with simulated design examples that a better feedback network could be found that offers higher gain over a broader bandwidth than successful state-of-the-art designs. Feedback configurations taken up in the examples include not only the simple shunt-shunt and series-series feedback, but also more complex, tapped transformer feedback, which was recently successfully used in an InP millimetre-wave amplifier.

In this paper, we propose a method of reducing the number of measurements when a bias optimization of an amplifier is required. We also provide a method of reconstructing an entire model of the amplifier from the reduced number of measurement results. We fabricated an eight-stage D-band low-noise amplifier (LNA) using a 65-nm CMOS technology. Applying these methods to this LNA to maximize a figure of merit, we obtained a 14.4-dB gain with ultra-low power consumption of 22.6 mW.

A QAM-capable 300GHz CMOS transmitter operating above/max was recently reported. A key component is a cubic mixer, which is a tripler-based up-conversion mixer. This paper studies the SNR characteristics of cubic mixer theoretically for realizing high-speed communication. The condition of avoiding the interference between the RF signal and spur component is clarified.

To realize a terahertz (THz) transmitter that supports complex digital modulation with a CMOS process having a sub-THz fmax, an unconventional triple-conversion transmitter architecture is introduced. Its first mixer is a quadrature modulator. The second mixer generates a second IF signal with two “sidebands” (up-converted signal and its image). The third mixer is the frequency quintupler-based, LO-less “quintic mixer” with an amplitude-distortion compensation filter. It up-converts the second IF signal to RF with high linearity using the two sidebands. No LO signal needs to be supplied, which simplifies the design of THz transmitter. A proof-of-concept experiment of the quantic mixer is demonstrated using a CMOS test chip with an on-chip IF receiver. A 16-QAM signal centered around 159 GHz is successfully generated from a modulated second IF signal at 31 GHz.

A QAM-capable 300-GHz transmitter operating above the transistor ƒmax, covering a 30-GHz bandwidth with multiple channels was recently reported. A key enabling component was a tripler-based up-conversion mixer called the “cubic mixer.” This paper theoretically and experimentally studies the S/N characteristics of such a mixer and elucidates the condition for realizing high single-channel data-rate. 30 Gb/s with 32QAM and 21 Gb/s with 64QAM are achieved under optimal conditions, which are faster than the previously reported per-channel data-rate of 17.5 Gb/s.

The vast unallocated frequency band lying above 275GHz offers enormous potential for ultrahigh-speed wireless communication. An overall bandwidth that could be allocated for multi-channel communication can easily be several times the 60GHz unlicensed bandwidth of 9GHz. We present a 300GHz transmitter (TX) in 40nm CMOS, capable of 32-quadrature amplitude modulation (QAM) 17.5Gb/s/ch signal transmission. It can cover the frequency range from 275 to 305GHz with 6 channels as shown at the top of Fig. 20.1.1. Figure 20.1.1 also lists possible THz TX architectures, based on recently reported above-200GHz TXs. The choice of architecture depends very much on the transistor unity-power-gain frequency fmax. If the fmax is sufficiently higher than the carrier frequency, the ordinary power amplifier (PA)-last architecture (Fig. 20.1.1, top row of the table) is possible and preferable [1–3], although the presence of a PA is, of course, not a requirement [4,5]. If, on the other hand, the fmax is comparable to or lower than the carrier frequency as in our case, a PA-less architecture must be adopted. A typical such architecture is the frequency multiplier-last architecture (Fig. 20.1.1, middle row of the table). For example, a 260GHz quadrupler-last on-off keying (OOK) TX [6] and a 434GHz tripler-last amplitude-shift keying (ASK) TX [7] were reported. A drawback of this architecture is the inefficient bandwidth utilization due to signal bandwidth spreading. Another drawback is that the use of multibit digital modulation is very difficult, if not impossible. An exception to this is the combination of quadrature phase-shift keying (QPSK) and frequency tripling. When a QPSK-modulated intermediate frequency (IF) signal undergoes frequency tripling, the resulting signal constellation remains that of QPSK with some symbol permutation. Such a tripler-last 240GHz QPSK TX was reported [8]. However, a 16-QAM constellation, for example, would suffer severe distortion by frequency tripling. If the 300GHz band is to be seriously considered for a platform for ultrahigh-speed wireless communication, QAM-capability will be a requisite.

This paper proposes an RF signal generator using a time domain harmonic suppression technique based on Fourier series analysis. The circuit consists of four differential ring voltage control oscillators (VCO's) with phase differences and the pulse signal summing circuit. By summing pulse signals from VCO's with appropriate phase differences determined by Fourier series in time domain, the third and fifth harmonics can be cancelled without filters. To confirm the validity, a prototypal RF signal generator was fabricated in 90-nm CMOS technology. As a result, we succeeded in generating an RF signal from digital pulse signals. The frequency range is from 1.1 to 3.7GHz with 1-V power supply. The suppression of both the third and fifth harmonics are below -48dBc at 1.1GHz and -42dBc at 3.7GHz.

As great advancements have been made in CMOS process technology over the past 20 years, RF CMOS circuits operating in the microwave band have rapidly developed from component circuit levels to multiband/multimode transceiver levels. In the next ten years, it is highly likely that the following devices will be realized: (i) versatile transceivers such as those used in software-defined radios (SDR), cognitive radios (CR), and reconfigurable radios (RR); (ii) systems that operate in the millimeter-wave or terahertz-wave region and achieve high speed and large-capacity data transmission; and (iii) microminiaturized low-power RF communication systems that will be extensively used in our everyday lives. However, classical technology for designing analog RF circuits cannot be used to design circuits for the abovementioned devices since it can be applied only in the case of continuous voltage and continuous time signals; therefore, it is necessary to integrate the design of high-speed digital circuits, which is based on the use of discrete voltages and the discrete time domain, with analog design, in order to both achieve wideband operation and compensate for signal distortions as well as variations in process, power supply voltage, and temperature. Moreover, as it is thought that small integration of the antenna and the interface circuit is indispensable to achieve miniaturized micro RF communication systems, the construction of the integrated design environment with the Micro Electro Mechanical Systems (MEMS) device etc. of the different kind devices becomes more important. In this paper, the history and the current status of the development of RF CMOS circuits are reviewed, and the future status of RF CMOS circuits is predicted.

In the conventional scaling scheme, interconnect delay cannot be reduced and the global interconnect delay become worse if the length of the wire is not scaled. The conventional approaches of global interconnect design are (1)introduction of inverse scaling concept where the upper metal layers have larger cross sections than lower metal layers, (2)insertion of repeaters, and (3) architecture level approach of multi/many core. In order to improve global interconnect delay even in aggressively miniaturized circuit, we have developed the transmission lien interconnect. This paper describes the novel analytical interconnect length distribution and discussion on future interconnect design direction. Then, recent our developments of the transmission line interconnect are described and performance comparison with another global wiring scheme such as optical interconnection is discussed.

A low-power inductorless 1:4 DEMUX and a 4:1 MUX for a 90 nm CMOS are presented. The DEMUX can be operated at a speed of 25 Gb/s with the power supply voltage of 1.05 V, and the power consumption is 8.9 ㎽. The area of the DEMUX core is 29 × 40 ㎛². The operation speed of the 4:1 MUX is 13 Gb/s at a power supply voltage of 1.2 V, and the power consumption is 4 ㎽. The area of the MUX core is 30 × 18 ㎛². The MUX/DEMUX mainly consists of differential pseudo-NMOS. In these MUX/DEMUX circuits, logic swing is nearly rail-torail, and a low Vdd. The component circuit is more scalable than a CML circuit, which is commonly used in a high-performance MUX/DEMUX. These MUX/DEMUX circuits are compatible with conventional CMOS logic circuit, and it can be directly connected to CMOS logic gates without logic level conversion. Furthermore, the circuits are useful for core-to-core interconnection in the system LSI or chip-to-chip communication within a multi-chip module, because of its low power, small footprint, and reasonable operation speed.

This paper presents a wide band low noise amplifier (LNA) that utilizes shunt feedback topology (SF). SF based lna suffers from strict trade-off between the input matching reflection coefficient (S'il) and noise figure NF. To break this trade-off a feed forward (FF) stage is added to achieve two in-phase nodes in the path of the signal where "a negative" Miller capacitance can be obtained by employing another capacitive FF resulting in a partial cancellation of the parasitic capacitance associated with the dominant pole hence expanding the BW of both gain and S'il while slightly affect the NF. The LNA was realized using 90 nm CMOS technology and achieves gain of 14 dB, Su < −10 dB and NF less than 2.2 dB in the frequency range from 0.5–2.2 GHz and less than 2.8 dB in the entire BW of 0.1–5GHz while draws 10 mA from 1.2 V DC source and occupies 0.003 mm2

This paper describes a technique to improve the linearity of low noise amplifier (LNA) that is implemented by the shunt-shunt feedback (SSFB) topology. By employing a parallel positive/negative feedback a suppression of the 2nd order harmonic distortion (OHD) in the feedback loop can be achieved which will result in minimization of the IM3 that is produced by mixing of this 2nd OHD with the input signal leading to an improvement of the LNA IIP3. Two LNA were fabricated using 180nm CMOS technology one adopting the conventional SSFB that was described in [1] and another one using our proposed linearization technique where an average improvement of +8dBm of IIP3 is achieved while maintaining quite similar minimum noise figure of 2.8dB, 3-dB bandwidth of 3.7GHz. Each of the fabricated LNAs consumes a current of 7.8mA from 1.8V power supply and occupies 0.007mm2.

There are many challenges inherent in the design of nano-CMOS. This paper describes our recent work relating to the physical design of CMOS circuits. First, in line with variation-aware design, a novel ingenious method of measuring variations in subthreshold characteristics is described. Next, recent RF CMOS issues and approaches to nano-CMOS are discussed. Finally, an on-chip transmission line interconnect developed for global wiring is discussed.

Theory and experiments are presented of modal decomposition of scattering matrices of multiconductor transmission lines (TLs). In effect, n coupled TLs are decomposed into n independent ones. Its use is demonstrated by applying it to thru-only de-embedding of 4 coupled TLs (synthesized data) and 2 coupled TLs (measurement data from a 0.18 ?m-CMOS chip). The proposed de-embedding method could greatly facilitate accurate characterization of on-chip multiport networks.

A compact model is proposed for accurately incorporating effects of STI (shallow trench isolation) stress into post-layout simulation by making layout-dependent corrections to SPICE model parameters. The model takes in-plane (longitudinal and transverse) and normal components of the layout-dependent stress into account, and model formulas are devised from physical considerations. Not only can the model handle the shape of the active-area of any MOSFET conforming to design rules, but also considers distances to neighboring active-areas. Extraction of geometrical parameters from the layout can be performed by standard LVS (layout versus schematic) tools, and the corrections can subsequently be back-annotated into the netlist. The paper spells out the complete formulation by presenting expressions for the mobility and the threshold voltage explicitly by way of example. The model is amply validated by comparisons with experimental data from 90 nm- and 65 nm-CMOS technologies having the channel orientations of, respectively, (110) and (100), both on a (100) surface. The worst-case standard errors turn out to be as small as 1.7% for the saturation current and 8 mV for the threshold voltage, as opposed to ∼20% and ∼50 mV without the model. Since device characteristics variations due to STI stress constitute a significant part of what have conventionally been treated as random variations, use of the proposed model could enable one to greatly narrow the guardbands required to guarantee a desired yield, thereby facilitating design closure.

A 124-GHz injection-locked quadrature voltage-controlled oscillator (ILQVCO) fabricated using a 40-nm CMOS process is presented. It locks onto a fundamental reference signal at 124 GHz generated on-chip from an external reference at 31 GHz, thereby avoiding generation of spurious noise commonly se en in the phase noise spectra of subharmonically injection-locked VCOs. The QVCO's phase noise levels in the free-running and injection-locked conditions are −87 dBc/Hz and −117 dBc/Hz, respectively, at 1-MHz offset. The high fundamental oscillation frequency and the low phase noise are realized by adopting a ring-type topology and transformers for inter-stage impedance matching. The ILQVCO is combined with an on-chip double-balanced quadrature modulator for vector signal generation. A 32QAM signal thus generated achieved a data rate of 25 Gb/s with an error-vector magnitude (EVM) of 5.1%.

An injection-locked frequency divider (ILFD) is utilized to divide the frequency of a voltage-controlled oscillator (VCO). We propose an ILFD that can be directly connected to a VCO by minimizing the input capacitance of the input nodes. The capacitance is reduced by limiting the number of MOSFETs connected to the injection nodes. We fabricated a 54 GHz divide-by-4 ILFD using 65 nm CMOS technology whose core area is 60 × 90 μm2. By limiting the number of driven MOSFETs and reducing the parasitic capacitance, a locking range of 430 MHz is achieved at a −20 dBm input. The power consumption is 21 mW with a 1.2 V supply and the phase noise is −120 dBc/Hz at a 1 MHz offset.

This paper presents a wideband differential amplifier operating at 138 GHz in 40-nm CMOS. It is composed of five differential common source stages with cross-coupled capacitors. A small-signal gain of 18 dB at 138 GHz and a 3-dB bandwidth of 27 GHz are achieved. It consumes 75 mW from a 0.94-V voltage supply. The die area with balun and pads is 945 × 842 μm2 and the core size not including input/output matching networks is 201 × 284 μm2. The small core area is realized by using a refined "fishbone" layout technique.

Formal comparative analysis is presented of three known de-embedding and characteristic impedance estimation techniques for on-chip transmission lines, used after probe-tip calibration. Somewhat counterintuitively, experience accumulated in the field seems to suggest that the apparently most simplistic of the three gives much better results than the other two, more "accurate-looking" techniques. The reason, however, never seems to have been explained clearly. This paper attempts to explain why and suggests some new alternative techniques.

Wideband decoupling for millimeter-wave circuits can be achieved using a transmission line having an extremely low characteristic impedance. The characteristic impedance of such a line can be estimated at high frequencies by measuring the input impedance of open and shorted stubs. However, since the propagation constant cannot be estimated reliably, a circuit model applicable to low frequencies has not yet been established. In this study, we extract the transmission-line parameters at low frequencies and build a circuit model using the RLGC parameters. This model is verified by comparing the results obtained from a circuit simulation and measurement data up to 40 GHz.

In this paper, we propose a calibration method for the parameters of a CMOS process and the structures of transmission lines used in the calibration. The process parameters of each dielectric layer can be determined separately using this method. To verify the proposed method, test structures of four types of transmission lines were fabricated using a 40 nm CMOS process. It was shown that the results of EM simulation using the process parameters calibrated by the proposed method were in good agreement with the measurement results up to 330 GHz.

This paper proposes an improved cold-bias de-embedding technique that properly separates the bias-independent parasitics from the bias-dependent core MOSFET characteristics. This is accomplished by considering possible discrepancy between dc and high-frequency I–V characteristics. It makes the core MOSFET model very simple. A 32-µm-wide common-source MOSFET fabricated in a 65 nm LP CMOS process is successfully modeled up to 330 GHz.

This paper presents a compact wideband amplifier at 160 GHz in 40-nm CMOS. Typical wideband amplifier design requires higher-order matching networks and more gain stages, both of which demand larger die area. The presented 8-stage amplifier uses a compact “fishbone” layout technique, and its core size is as small as 190 × 123 µm2. A small-signal gain of 15 dB at 160 GHz and a 3-dB bandwidth of 41 GHz are achieved. It consumes 117 mW from a 0.9 V voltage supply.

This paper presents compact and low-loss bandpass filters (BPFs) with ground-signal-ground interfaces that can easily be integrated with RFICs. The filters are realized by post-wall waveguide fabricated into a silica-substrate for the first time. A 59.11-GHz five-pole BPF with a 3.10% fractional bandwidth and a 2.62-dB insertion loss including input- and output- transitions is presented. Its intrinsic area is 8.4 mm by 2.0 mm. The proposed technology can offer practical integrated passive solutions for millimeter-wave applications.

A CMOS decoupling power line intended for use in millimeter-wave circuits is fabricated and characterized up to 325 GHz. It is designed to have a low dc resistance and an extremely low high-frequency characteristic impedance. The input impedance of a 0.3-mm-long line is shown to stay roughly below 1 Ω in 20 GHz–170GHz and below 2 Ω in 220 GHz–325 GHz, irrespective of whether the far end of the line is open- or short-ended, which clearly demonstrates its extremely wideband decoupling capability.

A wideband decoupling power line for millimeter-wave circuits can be realized with a transmission line having an extremely low characteristic impedance, Z 0 → 0Ω. It is, however, very difficult to characterize such a line with the ordinary two-port S-parameter measurement. This paper presents an alternative measurement technique that uses transmission line stubs. The measurement results confirm that a power line impedance below 1Ω is successfully achieved over a very wide frequency range (> 80 GHz). A measurement-based method of finding the necessary length of such a low-impedance line for realizing good decoupling is also proposed.

This work proposed the systematic calibration method of process parameters for electromagnetic analysis of CMOS back-end devices in millimeter-wave and THz frequencies. It uses the propagation constants of transmission lines in all the measurement frequency and the RLGC model parameters in low frequency as the objective variables of the parameter fitting. It was showed that the EM simulation results using calibrated process parameters were in good agreement with the measurement results up to 330 GHz.

Coulomb blockade devices can circumvent some of the problems that arise from the continuing miniaturization of conventional circuits. However, device miniaturization and higher circuit integration aggravate cross-coupling phenomena in Coulomb blockade circuits. As an example, a silicon-based bidirectional electron pump was electrically characterized with emphasis on cross-coupling arising from the clock signal driving the pump. The cross-coupling alters profoundly the expected device characteristics, and the experimental data are confirmed by Monte Carlo simulations.

This paper concerns maximizing the conversion gain of a CMOS push-push doubler, in which the drains of a pair of differentially driven MOSFETs are tied together. We propose to insert transmission lines, which act as resonators at the fundamental frequency, between the drains of the MOSFETs. In the simulation of the proposed circuit, it achieved an output power improvement of 2.2 dB at the 0 dBm input power.

A CMOS transmission line-to-waveguide transitions with a patch antenna for a WR3 waveguide (220–325 GHz) was designed using an electromagnetic-field simulator. The position of inserting the antenna to the waveguide and the size of the antenna were optimized to realize a low insertion loss and a wide bandwidth. As a result, an insertion loss of 0.9 dB and a 3-dB bandwidth of 120GHz were achieved.

It is difficult to evaluate four-port on-chip CMOS devices in the millimeter-wave (MMW) band using four-port vector network analyzer. To obtain the differential-mode characteristics, we proposed the technique of evaluating four-port networks as two-port networks using on-chip baluns, and applied the technique to the evaluation of differential transmission lines in the MMW band. As a result, it was shown that the propagation constant of the differential mode obtained by this technique was in the good agreement with one obtained by the EM simulation at the frequency band from 47 GHz to 110 GHz. By using this technique, it is expected that on-chip CMOS differential devices in the MMW band can be evaluated more easily.

This paper presents a systematic procedure for calibrating process parameters for electromagnetic field analysis. A few CMOS back-end material parameters are first chosen as fitting parameters by sensitivity analysis, and then their values are unambiguously determined from contour maps showing electrical characteristics versus effective material parameters. Calibration with measured data for 1–170 GHz is shown to give reasonably predictive simulation even at higher frequencies. Extraction of effective complex permittivities are also attempted up to 325 GHz in the presence of dummy metal fills for two filling patterns. The results indicate that the effective-parameter approach to dummy metal fills can reproduce measured propagation constants of transmission lines. The predictive power of such a simple approach is yet to be assessed.

This paper gives a brief review of our recent work done in the area of nanometre-scale Coulomb blockade (CB) memory and logic devices, that enable us to realize future electron-number scalability by overcoming inherent problems to conventional semiconductor devices. We introduce multiple-tunnel junctions (MTJs), naturally formed in heavily doped semiconductor nanowires, as a key building block for our CB devices. For memory applications, the hybrid MTJ/MOS cell architecture is described, and its high-speed RAM operation is investigated. For logic applications the binary decision diagram logic is discussed as a suitable architecture for low-gain MTJ transistors.

Pump circuits consisting of single-electron transistors are analyzed in which electrons are pumped by multiphase clock pulses. An optimal low-temperature operation condition is presented where pumped current is maximized, yet the power consumption is not. Approximate formulas for the number of electrons transferred per clock cycle and the power consumption are derived for that condition, which clearly show the advantage of the pump circuits for low-power applications. The power consumption becomes even less at higher temperatures. However, the relatively large island capacitance between transistors limits the operation temperature.

The effect of a tunnelling electron on the tunnel barrier shape is studied at the limit where a static image charge model is applicable. It is shown that the single-electron tunnelling current through an ultrasmall voltage-biased junction is not proportional to the junction area because of charging at the electrodes. Simple expressions are presented for the effective static barrier shape of a voltage-biased junction and of a junction in a circuit, the former of which accounts for the anomalous current scaling. A possible experimental arrangement for verifying the scaling relationship is suggested, with numerical results.

We have developed a 79 GHz CMOS power amplifier (PA) with temperature compensation implemented using 40 nm CMOS technology that suppresses the variation of small-signal gain and the degradation of linearity within 0.8 dB in the temperature range from 0 to 100°C. The PA consists of an on-chip temperature sensor and four-stage common-source NMOS amplifiers. The temperature-compensated PA operating at 100°C achieved a small-signal gain of 15.7 dB, a 12 GHz bandwidth and a saturated output power (Psat) of 6.8 dBm with 96.2 mW power consumption at a supply voltage of 1.1 V.

A 79 GHz power amplifier (PA) using 4-stages common-source structure is presented in this paper. To evaluate temperature dependence of circuit characteristics, the PA is measured at various temperatures. At room temperature (RT) and 100°C, the saturated output power is 7.6 and 7.1dBm, the maximum PAE is 6.2% and 4.9%, respectively. The reliability and lifetime of PA is also obtained. To the author's knowledge, this is the first paper to show the lifetime results of PA at two different biases in 40nm CMOS process.

It is known that the THRU standard (a transmission line) used for thru-reflect-line (TRL) calibration/de-embedding for S-parameter measurement has to be long enough that only a single electromagnetic mode propagates at its center for it to work reliably. But ideally, TRL standards should occupy as little precious silicon real estate as possible. This paper attempts to experimentally find out how long a THRU is long enough above 110GHz up to 170 GHz through measurements of transmission lines of various lengths. The results indicate that the length of a THRU should be at least 400 micrometers, excluding pads and pad-to-line transitions.

An inductorless phase-locked loop with subharmonic pulse injection locking was realized (PLL area: 0.11 mm2) by adopting 90 nm Si CMOS technology. The proposed circuit is configured with two cascaded PLLs; one of them is a reference PLL that generates reference signals to the other one from low-frequency external reference signals. The other is a main PLL that generates high-frequency output signals. A high-frequency half-integral subharmonic locking technique was used to decrease the phase noise characteristics. For a 50 MHz input reference signal, without injection locking, the 1 MHz offset phase noise was −88 dBc/Hz at a PLL output frequency of 7.2 GHz (= 144 × 50 MHz); with injection locking, the noise was −101 dBc/Hz (spur level: −31 dBc; power consumption from a 1.0 V power supply: 25 mW).

Performance of thru-only cascade de-embedding methods and their variants that use a Π- or a T-equivalent to represent and bisect a symmetric THRU is assessed. The results from the Π- and T-based methods are reasonable at low frequencies. However they are shown to deviate noticeably from the correct results as the frequency gets high or, equivalently, when the length of the THRU approaches an effective wavelength λ. A better alternative at high frequencies is TSD (thru-short-delay), which, when THRU is symmetric, requires only THRU and LINE. TSD gives correct results except in the periodically appearing ‘dead zones’, provided that the characteristic impedance, Z χ , of the transmission line (TL) in the LINE is known. A Π-based method could be used to extract Z χ at low frequencies, from which Z χ can be extrapolated to higher frequencies.

A characteristic impedance determination technique that can be used in the CMOS process with a large substrate loss is proposed. Furthermore, it is shown using image parameters that the propagation constant is obtained directly from Thru and Line without determining error networks. The validity of the characteristic impedance obtained by the proposed method is shown using the measurement and EM simulation results. The calibration patterns used for the validation check were fabricated using the 40 nm CMOS process.

A wide-frequency-range phase-locked loop (PLL) with subharmonic injection locking is proposed. The PLL is equipped with a wide tunable ring-type voltage-controlled oscillator (ring VCO), frequency dividers, and a doubler in order to the widen injection-locked tuning range (ILTR). In addition, high-frequency injection signals are used to improve phase noise, which is supposed to be generated by a reference PLL. The proposed circuit is fabricated by using a 65 nm Si complementary metal oxide semiconductor (CMOS) process. The measured frequency tuning range is from 1.2 to 17.6 GHz with a frequency doubler and dividers. The phase noise at 14.4 GHz (=32×450 MHz) with injection locking was -109 dBc/Hz, which shows a 21-dB reduction compared with that in the case without injection locking.

Two Coulomb blockade devices connected in series and separated by a main island to which a rf signal was applied, are characterized electrically. The main island is large enough so that Coulomb phenomena in it can be neglected. Although no source–drain voltage is applied, the rf signal causes a current. The polarity of this current depends on the dc gate voltages, which control the two Coulomb blockade devices. The experimental data correspond closely to the simulations. Furthermore, it is evident from theoretical considerations that the circuit can pump electron packets against an applied potential.

The compact SOI-MOSFET model HiSIM-SOI based on the complete surface-potential description is presented. The model considers all possible charges induced in the device for the formulation of the Poisson equation, which is solved iteratively. Thus HiSIM-SOI is valid for any structural variations from thick to extremely thin SOI or BOX layers. The dynamic depletion between the fully and partially depleted conditions is well reproduced. It is also demonstrated that the floating-body effect can be accurately captured by considering the accumulated charge in the SOI layer for the solution of the Poisson equation. HiSIM-SOI is verified to correctly reproduce 2D-device simulation results automatically for different SOI-structure types without any additional option setting.