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Summary: Flicker noise and white noise from the charge pump (CP) within a phase locked loop (PLL) are key contributors to the close‐in phase noise floor of a fractional‐N frequency synthesizer. The pulse train from the phase frequency detector imposes different types of random pulse modulation on the up and down current sources, which causes different modulation effects to the flicker and white noises at low frequency. This paper rigorously analyzes the underlying noise random modulation mechanisms for the system operating in integer‐N and fractional‐N modes. Transient noise simulation using Verilog‐A behavioral modeling followed by power spectrum analysis is applied to support the mathematical analysis of the random noise modulation. [ABSTRACT FROM AUTHOR]

The high phase noise (PN) of CMOS millimeter-wave oscillators has encouraged the adoption of wide loop bandwidth for an integer- $N$ phase-locked loop (PLL). This article proposes a quadrature sampling phase-frequency detector (QS-PFD) to disengage the tradeoff between spur rejection and loop bandwidth. With the introduction of an auxiliary path for phase detection, the spur generated by the main path is canceled without incurring extra power or degrading the loop stability. The high gain of the QS-PFD attenuates its jitter contribution to the loop. The QS-PFD enables fast frequency detection and lock detection. Implemented in 40-nm CMOS technology, the proposed PLL shows a −75-dBc reference spur, −101.5-dBc/Hz PN at a 1-MHz offset, and a minimum integrated jitter of 121.9 fsrms (10 kHz–100 MHz) at 38.2 GHz with a division ratio of 128. The lock detection time is at the microsecond level. The proposed PLL consumes 23.6 mW from a 1.1-V power supply, leading to a figure of merit (FoM) of −245 dB. [ABSTRACT FROM AUTHOR]

We demonstrate the coherent transfer of an ultrastable optical frequency reference over a 490 km noisy field fiber link. The fiber-induced phase noise power spectrum density per-unit-length at 1 Hz offset frequency can reach up to 510 rad2â‹...Hzâˆ'1â‹...kmâˆ'1, which is much higher than the fiber noise observed in previous reports. This extreme level of phase noise is mainly due to the fiber link laying underground along the highway. Appropriate phase-locked loop parameters are chosen to complete the active compensation of fiber noise by measuring the intensity fluctuation of additional phase noise and designing a homemade digital frequency division phase discriminator with a large phase detection range of 212 Ď€ rad. Finally, a noise suppression intensity of approximately 40 dB at 1 Hz is obtained, with fractional frequency instability of 1.1 Ă— 10âˆ'14 at 1 s averaging time, and 3.7 Ă— 10âˆ'19 at 10000 s. The transfer system will be used for remote atomic clock comparisons and optical frequency distribution over a long-distance communication network established in China. [ABSTRACT FROM AUTHOR]

This paper proposes a full-speed-domain position-sensor-less control strategy for precise control under forward and reverse rotation conditions to address the weak convex polarity of surface-mounted permanent magnet synchronous motor (SPMSM). The strategy comprises several key stages: pre-positioning of the rotor, constant current variable frequency (I/F) start-up, construct the Luenberger State Observer, and utilization of an improved phase-locked loop (PLL) for position estimation. In the pre-positioning stage, a constant amplitude current is applied to drag the rotor to a predetermined position. Subsequently, the I/F start-up stage accelerates the motor to a predetermined speed before transitioning to the Luenberger observer for closed-loop speed control, which is based on an extended back electromotive force (back-EMF) a two-phase rotating coordinate system. The improved PLL for position and speed estimation features three components: a phase discriminator (PD), a voltage-controlled oscillator (VCO), and loop filter (LF). Experimental results demonstrate the efficacy of the proposed strategy, showing quick start-up response, speed estimation error below 2 RPM, rotor position estimation error under 0.6 degrees post-loop closure, stable tracking during rapid speed changes, and consistent accuracy and stability even under reverse rotation conditions, thereby meeting the control strategy's objectives. • Propose a full speed domain sensorless control strategy. • Rapid and smooth switching of operating states. • Stable and precise control in both forward and reverse rotation. • Control strategies are experimentally verified using a hardware platform. [ABSTRACT FROM AUTHOR]

We study the out-of-time-order correlators (OTOC) of Skyrmion as baryon in the D0-D4/D8 model which is expected to be holographically dual to QCD with instantons as D0-branes or with a non-zero theta angle. Baryon states are identified to the excitations of the Skyrmion which are described by a holographic quantum mechanical system in this model. By employing the definition of OTOC in quantum mechanics, we derive the formulas and demonstrate explicitly the numerical calculations of the OTOC. Our calculation illustrates the quantum OTOC with imaginary Lyapunov coefficient indicates the possibly metastable baryonic status in the presence of the instanton while the classical OTOC can not, thus it reveals the instantonic or theta-dependent features of QCD are dominated basically by its quantum properties. Furthermore, the OTOC also implies the baryonic phase becomes really chaotic with real Lyapunov exponent if the instanton charge increases sufficiently which agrees with the unstable baryon spectrum presented in this model. In this sense, we believe the OTOC may be treated as a tool to detect the baryonic phase structure of QCD. [ABSTRACT FROM AUTHOR]

The ATLAS New Small Wheel (NSW) Muon spectrometer upgrade, completed in 2022, was the largest Phase I detector upgrade among LHC experiments. The NSW enhances triggering in the endcap region (1. 3 < | η | < 2. 4) by confirming muons from the Interaction Point (IP) and rejecting fake contributions. It also improves muon tracking with 2.5 million high-resolution channels across 16 layers. The NSW Trigger, based on small-strip Thin Gap Chambers (sTGC) and Micromegas (MM) technologies, provides Level-1 triggers at every Bunch Crossing (BC) with a fixed low latency (44 BC). Integrated into ATLAS in 2023, the NSW Trigger significantly reduces fake rates and overall readout deadtime. The custom electronics of the NSW Trigger system efficiently collect, process, and trigger on IP muons, focusing on the fully operational sTGC pad-only path based on the Pad Trigger (PT) and Trigger Processor (TP) FPGA based boards. Performance studies using 13. 6 TeV pp collisions are presented, demonstrating NSW's readiness for the High Luminocity LHC (HL-LHC) era and outlining Phase II upgrade perspectives. [ABSTRACT FROM AUTHOR]

In this work, a novel phase frequency detector (PFD) architecture using pass transistor logic is proposed. The circuit does not have a reset path, resulting in the elimination of blind zone and dead zone. The ϕ -V characteristics of the PFD were found to have better linearity across the range of − π to π due to the absence of blind and dead zones. The Taguchi and ANOVA statistical techniques were used to optimize the PFD. The optimized PFD exhibited a phase noise of −142.24 dBc/Hz, consumed 5.64 μ W of power and had a maximum operating frequency of 5.25 GHz, and a delay of 10.65 ps. Using this PFD, a GHz-range synthesizer was designed, and its performance characteristics were obtained from circuit simulations using CADENCE Virtuoso. The synthesizer had a power consumption of 4.25 mW at a supply of 1.8 V, achieved a lock time of 2. 95 μ s , and could generate frequencies ranging from 0.1 GHz to 4.75 GHz while occupying a chip area of 0.013 mm 2. Moreover, the work introduced a new figure of merit, FoM. The synthesizer has potential applications in various devices such as radio receivers, televisions, mobile phones, satellite receivers, and GPS systems. • The simple circuit of Phase Frequency Detector avoids the use of reset path to achieve zero dead zone and high operating frequency. • Pass transistor logic employed to the second stage of PFD which enhance the operating frequency and simplify the circuit. • Taguchi DoE and ANOVA optimization methodology have been used to find out the sizes of MOS transistors and supply voltage to achieve optimized results. • Optimized PFD has lower phase noise, low power dissipation, lesser delay and high maximum operating frequency thus beneficial for low power and high speed frequency synthesizer applications. • Significant high speed, low power dissipation, low THD and lesser chip area of Frequency synthesizer making it suitable for use in high-speed devices such as radio receivers and GPS systems. [ABSTRACT FROM AUTHOR]

A new optical beam splitting method is proposed, based on which the optical frame camera capable of capturing multiple frames in a single exposure is designed and experimentally verified. The operation of the frame camera is based on an ultra-fast response semiconductor detector. It is equipped with an optical beam splitter and an optical imaging module. The ultrafast semiconductor detector receives an optical pulse that produces a transient refractive index change, and ultrafast physical processes are recorded by diffracting the probe laser through the transient phase grating. The interaction of an X-ray pulse with a semiconductor detector to produce a phase grating is simulated, based on the Monte Carlo method. The optical beam splitting mode separates a laser into two optical pulses with a certain time difference in the direction of polarization perpendicular to each other. The imaging module filters the diffracted probe laser in the spectral plane and then images multiple frames. The frame camera was used to record the temporal and spatial distribution characteristics of femtosecond laser pulses with a temporal resolution of 4.1 ps. This frame camera has great potential and value for applying to experimental studies of inertial confinement fusion. [ABSTRACT FROM AUTHOR]

This paper presents a fully integrated analog phase‐locked loop (PLL) fractional‐N frequency synthesizer for 5G wireless communication and Internet‐of‐Everything (IoE) applications. To demonstrate the effectiveness of this frequency synthesizer, we apply it to three wireless communication standards. Contrary to using Verilog or VHDL to implement the programmable frequency divider, we propose a new approach in the transistor level with a new divide‐by‐2/3 circuit, dynamic asynchronous resettable D and JK flip‐flops, and the OR & AND gates to customize the divider for low‐power, low‐jitter, and fast‐lock time applications. In addition, we have designed a new frequency phase detector (PFD) to overcome the dead region issue. An ultra‐low phase noise and low‐power voltage control oscillator (VCO) is exploited from our previous work with the flicker noise corner frequency around 10 kHz to achieve the lowest possible phase noise. The implementation is done in 180‐nm standard CMOS technology. It covers two frequency ranges including 2.4 to 2.48 GHz and 5 to 5.825 GHz for these wireless communication standards. According to simulations in the worst case, the lock time, rms‐jitter, in‐band fractional spur, power consumption, and jitter‐power figure‐of‐merit of the frequency synthesizer is 18 μs, 56 fs, −63 dBc, 4 mW, and −259, respectively. [ABSTRACT FROM AUTHOR]

PURPOSE: To compare imaging performance of a cadmium telluride (CdTe) based photon counting detector (PCD) with a CMOS based energy integrating detector (EID) for potential phase sensitive imaging of breast cancer. METHODS: A high energy inline phase sensitive imaging prototype consisting of a microfocus X-ray source with geometric magnification of 2 was employed. The pixel pitch of the PCD was 55μm, while 50μm for EID. The spatial resolution was quantitatively and qualitatively assessed through modulation transfer function (MTF) and bar pattern images. The edge enhancement visibility was assessed by measuring edge enhancement index (EEI) using the acrylic edge acquired images. A contrast detail (CD) phantom was utilized to compare detectability of simulated tumors, while an American College of Radiology (ACR) accredited phantom for mammography was used to compare detection of simulated calcification clusters. A custom-built phantom was employed to compare detection of fibrous structures. The PCD images were acquired at equal, and 30% less mean glandular dose (MGD) levels as of EID images. Observer studies along with contrast to noise ratio (CNR) and signal to noise ratio (SNR) analyses were performed for comparison of two detection systems. RESULTS: MTF curves and bar pattern images revealed an improvement of about 40% in the cutoff resolution with the PCD. The excellent spatial resolution offered by PCD system complemented superior detection of the diffraction fringes at boundaries of the acrylic edge and resulted in an EEI value of 3.64 as compared to 1.44 produced with EID image. At equal MGD levels (standard dose), observer studies along with CNR and SNR analyses revealed a substantial improvement of PCD acquired images in detection of simulated tumors, calcification clusters, and fibrous structures. At 30% less MGD, PCD images preserved image quality to yield equivalent (slightly better) detection as compared to the standard dose EID images. CONCLUSION: CdTe-based PCDs are technically feasible to image breast abnormalities (low/high contrast structures) at low radiation dose levels using the high energy inline phase sensitive imaging technique. [ABSTRACT FROM AUTHOR]

The Visible Telescope (VT), which is the primary payload for the Chinese-French Space Multi-band Variable Object Monitor (SVOM) mission, is designed to observe the optical afterglow of gamma-ray bursts (GRBs). While calibration is one of the key factors to validate that VT achieves its scientific objectives in terms of detection limit, photometric accuracy and photometric system deviation. In the dissertation, based on the scientific objectives and optomechanical parameters of SVOM VT, the calibration techniques for space-based astronomical telescopes are studied. We have carried out comprehensive characterization and high-precision calibration of VT qualification model in three phases: detector, instrumentation and in-orbit laboratory verification, and all tests have reached the desired results and meet the requirements of calibration indicators. [ABSTRACT FROM AUTHOR]

This article proposes a phase-locked loop (PLL) based on the direct digital synthesis (DDS)/digital-to-analog converter (DAC) and the double-edge zero-crossing sampling phase detector (DS-PD) for frequency-modulated continuous-wave (FMCW) radar. Its DS-PD and frequency divider are combined to achieve refined time resolution while effectively expanding the phase lock range, thus eliminating the frequency-locked loop (FLL). The DDS/DAC is used to generate FMCW signals while achieving fast frequency hopping. A differential eight switching current unit is proposed to implement an ultrahigh-speed time-interleaved DAC. The 8.55–17.11-GHz PLL prototype, fabricated in 65-nm CMOS, consumes 10.11 mW with 0.29-mm2 active area, while the DDS/DAC consumes 12.0 mW with a 0.16-mm2 active area. The measured in-band phase noise (PN) at a 17.11-GHz output is −120.2 dBc/Hz at a 1-MHz offset with a root-mean-square (rms) jitter of 51.7 fs. The reference spur is <−51 dBc. Finally, a figure-of-merit (FoM) value of −255.7 dB is obtained. The prototype PLL effectively generates fast (500 MHz/ $3.6~\mu \text{s}$) and precise (105-kHzrms frequency error) triangular chirps for FMCW radar applications. [ABSTRACT FROM AUTHOR]

This paper presents a phase‐locked loop (PLL) with a novel phase frequency detector (PFD) and charge pump (CP) which can extend the linear phase difference detection range and eliminate cycle slips. Thus, the frequency settling time can be effectively reduced compared with the conventional PFD and CP during the frequency acquisition process. The proposed PLL with linear range extension PFD and CP (LEPFD/CP) is designed in 180 nm BiCMOS technology and occupies 3.61 mm2 area. As the LEPFD/CP is disabled when the PLL is locked, the PLL is robust enough and the extra power consumption can be ignored. The measurement results show that a 50 MHz reference frequency acquisition process with 10 μs has been accelerated 3.7 times compared with the conventional PFD/CP PLL with the same 200 kHz loop bandwidth. [ABSTRACT FROM AUTHOR]

This article presents a fractional-N sampling type-I phase-locked loop (PLL). To overcome the impairments of a conventional type-I PLL, namely the frequency-tuning-dependent time offset and the narrow range of the sampling phase detector (SPD), which would prevent fractional-N synthesis, a novel digital phase error correction (DPEC) technique, operating in the background, is introduced, which provides robust low-jitter performance. Besides, a novel frequency locking method is presented, which provides fast lock and seamless hand-off to main PLL operation. The PLL has been fabricated in a 28-nm CMOS technology process, and it synthesizes frequencies from 11.9 to 14.1 GHz, achieving an rms jitter of 58.2 and 51.7 fs (integrated into the 1 kHz–100 MHz bandwidth) for a fractional-N and integer-N channel, respectively. The reference spur is as low as −73.5 dBc, while the worst case near-integer fractional spurs are lower than −63.2 dBc. With a power consumption of 18 mW, the jitter-power figure of merit is −252.1 dB (fractional-N) and −253.3 dB (integer-N). The locking time is below 9 $\mu \text{s}$ for a 1-GHz frequency step. The synthesizer occupies 0.16 mm2, including decoupling capacitors. [ABSTRACT FROM AUTHOR]

This article presents design techniques for a continuous-rate reference-free clock and data recovery (CDR) circuit employing a stochastic frequency–phase detector (SFPD). By taking a histogram-based design methodology, optimal weights for both frequency and phase detection are obtained by utilizing the same information as the Alexander phase detector. The design methodology is inductive and stochastic, distinguished from the conventional, deductive, and procedural methods. To verify a robust operation, the effects of varied data patterns, noise, and channel loss are examined, together with the avoidance of harmonic locking. In addition, a consideration of a sample window is analyzed by fast Fourier transform (FFT) simulation. Fabricated in 40-nm low-power (LP) CMOS technology, the proposed CDR circuit achieves a capture range from 6.4 to 32 Gb/s and a lock time of less than $11 \mu \text{s}$. The measured frequency acquisition behavior shows that harmonic locking is avoided with a seamless transition to the fundamental mode. The CDR circuit tested over a 10-dB loss channel achieves a bit error rate (BER) less than 10−12 and energy efficiency of 0.96 pJ/b. [ABSTRACT FROM AUTHOR]

This article reports a single-loop full-rate bang-bang clock and data recovery (BBCDR) circuit supporting a four-level pulse amplitude modulation (PAM-4) pattern. We eliminate both the reference and the separate frequency detector (FD) by deliberately adding two fixed strobe points in the bang-bang phase detector (BBPD) curve via a clock-selection scheme. As such, we can achieve a wide frequency-capture range in a single-sided FD polarity. The BBPD also incorporates a hybrid control circuit to automate the frequency acquisition over a wide frequency range. Prototyped in a 28-nm CMOS, the proposed BBCDR occupies a tiny area of 0.0285 mm2 and exhibits a 23-to-29-Gb/s capture range. The acquisition speed [8.2 Gb/s/ $\mu \text{s}$ ] and energy efficiency (0.68 pJ/bit) compare favorably with the state of the art. [ABSTRACT FROM AUTHOR]

This article presents a low-jitter and low-spur charge-sampling phase-locked loop (CSPLL). A charge-domain sub-sampling phase detector is introduced to achieve a high phase-detection gain and to reduce the PLL in-band phase noise. Even without employing any power-hungry isolation buffers, the proposed phase detector dramatically suppresses the reference spurs by both minimizing the modulated capacitance seen by the voltage-controlled oscillator (VCO) tank and by reducing the duty cycle of the sampling clock. A 50- $\mu \text{W}$ RF-dividerless frequency-tracking loop is also introduced to lock the CSPLL robustly when the VCO faces a sudden frequency disturbance. Fabricated in a 40-nm CMOS process, the prototype CSPLL occupies a core area of 0.13 mm2 and synthesizes 9.6-to-12-GHz tones using a 100-MHz reference. At 11.2 GHz, it achieves a reference spur of −77.3 dBc and an RMS jitter of 48.6 fs while consuming 5 mW. [ABSTRACT FROM AUTHOR]

Summary: The objective of this article is to increase the efficiency of face recognition in the aspect of a dynamic frame. Studies were carried out that focus on maintaining the high detection rate as well as increasing the accuracy. The study was conducted by considering the current recording of the dynamic frame of randomly selected people walking on a treadmill. Here, the variety of facial features was studied and extracted using different viewing angles on the subject. The existence of a huge amount of datasets and economical processing power is subject to value enhancement in the presence of a convolutional neural network (CNN) on different object identification and realization criteria. These methodologies with excellent knowledge of deep learning techniques that subjects to enhance the potential of the machine to learn the face values. CNN is capable to identify faces, positive positioning facial benchmarks, estimating postures and understanding faces in interconnected images and dynamic video frames. In this article, we present a novel phase detector technique that is rapid and has the potential of recognizing faces with huge changes. This is performed by a technique of using adopted CNN and recurrent neural network's subpart long‐short term memory technique in a particular way so that the objective of bringing improvement in the reorganization procedure can be fulfilled. And this was completed by getting 97.5%–98.1% of accuracy is sustained in this. [ABSTRACT FROM AUTHOR]

This brief describes an integer-N-type-II sub-sampling phase-locked loop (SS-PLL) incorporating a push–pull sub-sampling phase detector to significantly suppress the spur-induced binary frequency shift keying modulation (BFSK) effect and a low-power fast-locking frequency-locked loop (FLL) to shorten the settling time. Prototyped in 65-nm CMOS, the SS-PLL at 3.3 GHz shows a reference spur of −82.2 dBc, an integrated jitter of 64.9 fsrms (1 kHz to 40 MHz), and an in-band phase noise (PN) of −128.4 dBc/Hz at 1-MHz offset. The corresponding jitter power figure of merit (FOM) is −255 dB. The entire SS-PLL consumes 7.5 mW, with only $90~\mu \text{W}$ associated with the FLL. [ABSTRACT FROM AUTHOR]

The zero‐velocity update (ZUPT) method is an effective way to reduce accumulated velocity errors of pedestrian navigation systems (PNSs). For a typical scheme, a stance phase detection module based on a fixed threshold is used to trigger the ZUPT algorithm. However, the detector is not robust enough for dynamic gait speeds. The false detection will degrade the navigation performance. In this letter, to improve the stance phase detector, the adaptive zero‐velocity detection problem is cast under dynamic gait speeds as a sequential threshold of a traditional detector inferring problem and a zero‐velocity detection framework proposed by combining a deep neural network with a traditional binary gait phase detector. Sufficient experimental results show that the proposed method outperforms other discussed learning‐based methods taking into account the trade‐off among model performance, structure, and size. Compared with the traditional method with a fixed threshold, the real‐world high‐dynamic positioning experiments show that this proposed method reduces the root mean squared error (RMSE) of absolute distance error by 48.7%, RMSE of start‐end error by 12.5%, and average RMSE of position error by 19.2%. [ABSTRACT FROM AUTHOR]

This letter proposes a new approach for online detection of low-quality synchrophasor data under both normal and event conditions. The proposed approach utilizes the features of synchrophasor data in time and frequency domains to distinguish multiple regional PMU signals and detect low-quality synchrophasor data. It is more effective to detect low-quality data with apparently indistinguishable profiles. Case studies from recorded synchrophasor measurements verify the effectiveness of the proposed approach for detecting low-quality synchrophasor data in frequency, voltage magnitude and voltage angle. [ABSTRACT FROM AUTHOR]

Coherent processing in cooperative multi-agent networks can achieve significant performance gain via accurate alignment of observed signals. However, the inaccessibility of phase information in mobile scenes prevents the acquisition of a high degree of coherence for target detection. This paper presents a quasi-coherent mobile detection framework for cooperative multi-agent networks, which exploits the phase information inherent in the carrier wave of direct-path signals. Specifically, we derive the quasi-coherent detector with the aid of phase calibration by incorporating the maximum likelihood estimation of phase-related parameters obtained from direct-path signals. Next, we characterize the detection performance degradation induced by the mismatch of initial phase, transmitter position, orientation and clock. We further demonstrate the near-optimal detection capability of the proposed detector compared with generic coherent detectors and validate the effectiveness of phase information exploitation via numerical simulations. [ABSTRACT FROM AUTHOR]

Copyright of Journal of Harbin Institute of Technology. Social Sciences Edition / Haerbin Gongye Daxue Xuebao. Shehui Kexue Ban is the property of Harbin Institute of Technology and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

This work presents a 6-GHz low-jitter and high figure-of-merit (FoM) fractional- $N$ phase-locked loop (PLL). It uses a digital-to-time converter (DTC)-based sampling PLL architecture. To achieve ultra-low jitter in fractional- $N$ mode, a phase detector range reduction technique is used to halve the required DTC delay range (DR), resulting in lower thermal noise and better DTC linearity. Moreover, a reconfigurable dual-core voltage-controlled oscillator (VCO) provides extra freedom in power and jitter tradeoff. It achieves 83.4-fs rms jitter in fractional- $N$ mode, integrated from 10 kHz to 100 MHz, with a 76.8-MHz crystal oscillator (XO) reference. In the low-power mode, the rms jitter degrades to 96.3 fs and the PLL FoM improves from −250.1 to −251.2 dB, as the PLL power consumption reduces from 14.2 to 8.2 mW. The measured fractional spurs are less than −70 dBc for near-integer channels. The PLL rms jitter remains within 100 fs across the 5–7-GHz output frequency band, thanks to the digital background calibrations. It is implemented in a 14-nm FINFET process and occupies 0.31 mm2. [ABSTRACT FROM AUTHOR]

Active load impedance variations in a phased array transmitter cause significant power amplifier (PA) performance degradation, in terms of output power, linearity, and power-added efficiency, which are key parameters to enable high-speed data throughputs using spectrally efficient modulation schemes. The system performance can be restored by using PAs having active or passive reconfigurability with the help of antenna impedance sensors. This article presents a low-power reflection-coefficient sensor for 5G millimeter-wave phased-array applications. The complex load impedance of the PA is determined based on the complex voltage over a sensing element, which can be integrated and co-designed with the PA output matching network, with minimal loss (< 0.2 dB) and a negligible area penalty. A full-range phase detector with improved detection resolution is proposed, enabling an amplitude-insensitive phase detection. Fabricated in a 22 nm FD-SOI process, the sensor prototype occupies a silicon area of 0.024 mm2 and consumes 13.2 mW power. The sensor demonstrates a wide detection range with $\vert \Gamma \vert $ up to 0.7 (VSWR 5.67) in a load-pull test at 28 GHz. From $\Gamma $ circle of 0.2 up to 0.7, the maximum detection errors in the magnitude and phase of the $\Gamma $ are 0.14° and 40°, respectively. [ABSTRACT FROM AUTHOR]

In this article, a mixed–signal, 32-kHz reference-based 2.4-GHz fractional- ${N}$ over-sampling phase-locked loop (OSPLL) is proposed. Different from the conventional $1\times $ sampling PLL, which only uses zero-crossing timing information of the reference signal, the proposed OSPLL fully utilizes both the voltage and timing domain information of the reference signal and realizes oversampling ratio (OSR) times phase detection (PD) in one reference cycle. The proposed OSPLL employs the digital-to-analog converter (DAC) to construct the reference-like feedback signal in the voltage domain and utilizes the digital-to-time converter (DTC) to improve PD resolution in the time domain. The adaptive lookup table (LuT)-based calibration is proposed to generate the correct information for DAC and DTC control. A clocked passive comparator works as a bang-bang phase detector (BBPD) for the PLL control and LuTs’ construction. The co-design of low-noise analog circuits and digital calibrations enables good jitter and spur performance. The proposed OSPLL is fabricated in 65-nm CMOS technology, with the core area of 0.58 mm2, and the power consumption is 4.97 mW with a 1-V power supply. It achieves 5.79-ps root-mean-square (rms) jitter in fractional- ${N}$ modes with the loop-bandwidth (BWloop) of 200 kHz, corresponding to the figures of merit (FoMs) of −217.8 dB. The measured fractional spur is less than −36 dBc, and the reference spur is −78 dBc, respectively. [ABSTRACT FROM AUTHOR]

A voltage-controlled oscillator (VCO)-based comparator that automatically adapts its noise performance reflecting the input voltage difference ($\Delta V_{\text {in}}$) is presented. Such adaptive operation significantly reduces the power of high-precision comparators in successive-approximation-register (SAR) ADCs. $\Delta V_{\text {in}}$ is integrated as a time difference via the VCO, where the integration continues as long as the time difference is below a certain threshold, defined by the phase detector deadzone. Thus, when $\Delta V_{\text {in}}$ is large, the comparator operates as a low-power delay line-based comparator, and with small $\Delta V_{\text {in}}$ , the VCO oscillates to integrate the input signal and suppresses the comparator noise. The required oscillations to complete the comparison are inversely proportional to $\Delta V_{\text {in}}$ , realizing fully adaptive noise and power scaling. This article provides a detailed analysis and specific design guidelines of the VCO comparator. Moreover, the PVT drift tolerance and detailed circuit implementations are deeply discussed as well. For proof-of-concept, a 13-bit SAR ADC with the proposed VCO-based comparator was fabricated in 65-nm CMOS. By off-chip LMS calibration, the ADC achieves peak SNDR 66 dB at 1 MS/s with a peak FoM of 29 fJ/conv.-step. [ABSTRACT FROM AUTHOR]

Most conventional vital-sign radars cannot easily detect human vital sign signals under nonperiodic body movement. This article presents a novel frequency-locked loop (FLL) radar that can track the phase changes that are caused by nonperiodic body movement. A gain/phase detector and a cross correlation function (CCF) in the FLL radar greatly reduce the second harmonic, the intermodulation terms between vital sign signals and nonperiodic body movement noise, enhancing both the signal-to-noise ratio and the accuracy of detection of the vital signs. Measurements indicated that the implemented 2.4-GHz FLL radar with a gain/phase detector and CCF can effectively detect the human respiration rate (RR) and heart rate (HR) under nonperiodic body movement. Using a chest belt as the measurement reference, the standard deviation (SD) of RR and HR measurements were 1.27 and 5.69 beats/min, respectively, when the seated subject under test (SUT) swung nonperiodically his upper body. When the SUT walked away from the radar naturally at 2.6 km/h, the implemented FLL radar measured RR and HR with SDs of 2.67 and 8.28 beats/min, respectively. [ABSTRACT FROM AUTHOR]

The Phase-Locked Loops, conceived in the 1930's by Henri de Bellescize, and used in a large scale on TV sets and integrated services digital telecommunication networks are nowadays increasing their relevance, being present in the time-basis generation and detection either in integrated circuits or in smart-grids power distribution systems. Among the Phase-Locked Loop architecture components is the Phase Detector. The phase detection function is a measure of phase/frequency errors in the Phase-Locked Loop, with analog, hybrid and digital implementations. In most of the classical literature the phase detection function is implemented by a signal multiplier device that can be approximated by a sine function from the phase error. Additional simplifications made on the phase detection function approximates the Phase-Locked Loop to a Düffing system. The phase detection function usually generates oscillations, such as the double-frequency jitter, which is a sinusoidal signal with the double of the synchronization frequency. Nowadays, software implementation allows a considerable flexibility to the phase detection function. Therefore, the phase detection requires accurate modeling to guarantee precision to the obtained clock signals. This work presents a performance comparison between the multiplier, the sine and the Düffing detectors. [ABSTRACT FROM AUTHOR]

This article introduces an adaptive self-tuned controller IC for resonant wireless power transfer (RWPT) transmitters. The controller IC comprises an on-the-fly very-high-frequency tracking hardware with high resolution and an independent high-resolution digital pulsewidth modulator (PWM)-based (HR-DPWM) current programmed control. These facilitate precise frequency generation as well as adaptive tuning of the reactive components in the matching network, which translate into tight current/power regulation capabilities while retaining optimized power transfer conditions on the transmitting side. The controller IC enables to effectively disengage the power-delivery capabilities from the variations of the resonators, electrical circuits, and wireless medium. The controller core is based on a fully synthesizable digital architecture that has been realized through HDL tools, and several key building blocks have been developed and described in detail: a delay-line-based phase detector, high-resolution digital frequency synthesizer, and HR-DPWM. To fully exploit the benefits of digital electronics, reduce power consumption, and save area, the digital core of the controller has been designed completely through asynchronous architecture, eliminating the need of high-speed clock and its related hardware. The mixed-signal controller IC has been designed, implemented, and fabricated in 0.18-μm 5-V CMOS process, resulting in effective silicon area of 0.6 mm2. To demonstrate the mixed-signal controller IC in closed-loop operation of a wireless power system, an experimental 20-W resonant capacitive-based WTP system has been designed and validated. The effectiveness of the controller is well demonstrated and evaluated at the MHz range up to 200 mm misalignment, meeting the strict requirements of resonant-based WPT systems. [ABSTRACT FROM AUTHOR]

This article presents a low-power fractional- ${N}$ all-digital phase-locked loop (ADPLL) employing a reference-waveform oversampling (ROS) phase detector (PD) that increases its effective rate four times, thus leading to lower jitter and settling time. The proposed ROS-PD adopts a bottom-plate sampling with a voltage zero-forcing technique, which yields high power efficiency and supports fractional phase compensation in the voltage domain through a programmable DAC. The PD output is then amplified by a low-noise gated amplifier and digitized by a low-power successive approximation register analog-to-digital converter (SAR-ADC). Leveraging the benefits of digital architecture, gain mismatches from the waveform estimator are calibrated by means of an LMS algorithm, consequently lowering fractional spurs. The proposed ADPLL is implemented in TSMC 28-nm LP CMOS. The prototype generates a 2.0–2.3-GHz carrier with an rms jitter of 414 fs while consuming only 1.15 mW. This corresponds to a state-of-the-art ADPLL FoMjitter of −247 dB in a fractional- ${N}$ mode. Due to the wide (largely linear) monotonic range and $4\times $ oversampling rate from a 48-MHz reference, without any additional circuitry, the proposed ADPLL can settle within $3~\mu \text{s}$ in face of a 70-MHz frequency step. [ABSTRACT FROM AUTHOR]

This paper presents an energy efficient successive-approximation register (SAR) analog-to-digital converter (ADC) for low-power applications. To improve the overall energy-efficiency, a skipping-window technique is used to bypass corresponding conversion steps when the input falls in a window indicated by a time-domain comparator, which can provide not only the polarity of the input, but also the amount information of the input. The timedomain comparator, which is based on the edge pursing principle, consists of delay cells, two NAND gates, two D-flip-flop register-based phase detectors and a counter. The digital characteristic of the comparator makes the design more flexible, and the comparator can achieve noise and power optimization automatically by simply adjusting the delay cell number. An energy efficient digital-to-analog converter (DAC) control scheme suitable for the skipping window technique is also developed to reduce the switching energy during SAR conversion. Together with the skipping-window technique, the linearity and the power consumption of the SAR ADC are improved. The impact of different window sizes on comparison cycles, DAC switching energy and the overall energy efficiency is analyzed. Simulation results show that the proposed skipping-window technique can improve the overall energy-efficiency of the SAR ADC, as well as the linearity, and the optimized window size for the overall energy efficiency will vary with the DAC switching energy. [ABSTRACT FROM AUTHOR]

In this article, a fully integrated capacitorless low-dropout regulator (LDO) is presented for Internet-of-Things (IoT) edge sensor application. To achieve sub-1-V operation and fast transient response with low quiescent current, the conventional operational transconductance amplifier (OTA)-based error amplifier (EA) is replaced with oscillator-based voltage-to-time converter and time-domain signal processing, including time-domain edge-based frequency comparator (FC) and event-driven voltage mode charge pump (CP). Compared with the conventional phase frequency detector (PFD), the proposed clock-edge-based FC achieved more than six times power reduction. Event-driven CP is adopted to drive analog power transistor and the transient response is enhanced by feedforward capacitor $C_{\mathrm {FD}}$ and coarse–fine CP control. To further reduce the power consumption, multi-voltage domain and clock frequency optimization are implemented. A prototype chip is fabricated in a standard 65-nm CMOS process. The design only consumes 310-nA quiescent current while achieving 0.5–1.2-V input range, $1.0\times 10^{6}$ load dynamic range, and 3-fs figure of merit (FoM). [ABSTRACT FROM AUTHOR]

Many sensory systems utilize parallel ON and OFF pathways that signal stimulus increments and decrements, respectively. These pathways consist of ensembles or grids of ON and OFF detectors spanning sensory space. Yet, encoding by opponent pathways raises a question: How should grids of ON and OFF detectors be arranged to optimally encode natural stimuli? We investigated this question using a model of the retina guided by efficient coding theory. Specifically, we optimized spatial receptive fields and contrast response functions to encode natural images given noise and constrained firing rates. We find that the optimal arrangement of ON and OFF receptive fields exhibits a transition between aligned and antialigned grids. The preferred phase depends on detector noise and the statistical structure of the natural stimuli. These results reveal that noise and stimulus statistics produce qualitative shifts in neural coding strategies and provide theoretical predictions for the configuration of opponent pathways in the nervous system. [ABSTRACT FROM AUTHOR]

In this article, we propose a frequency discriminator (FD) design method to produce uniform frequency sub‐bands. FDs are designed using an interferometer projected with the proposed formulated phase. For experimental verification that a uniform sub‐band is formed using the proposed phase formula, 3‐bit FDs are designed and fabricated to operate in the 2 to 3 GHz and 2 to 4 GHz bands, respectively. The FD consists of a power divider/combiner, reference line, and delay line. Scattering parameters of the FDs are analyzed using RF simulation and measurement results. RF characteristic results show that a 3‐bit FD designed using the proposed phase formula can identify an unknown signal inside the defined frequency band. [ABSTRACT FROM AUTHOR]

This article describes a design of an field-programmable gate array (FPGA) implementation of a clock and data recovery (CDR) system. The core will be integrated in the FPGA configuration for the front-end electronics (FEE) board of the Jiangmen underground neutrino observatory (JUNO) experiment. The front-end will be placed on the main detector, underground and underwater, making the electronics not accessible after installation. The timing and trigger system relies on a synchronous link connection over CAT5e cable (up to 100 m long) between the front-end and the back-end electronics (BEE), where a twisted-pair is dedicated to clock-forwarding. The robustness of the recovery clock system is essential for the stability of the FPGA firmware. The proposed project is intended to improve the clock recovery operation by increasing the immunity of the link to sudden electromagnetic interference (EMI). On top of this, the core allows to free a twisted-pair in the link, since the clock can be recovered from the data and there is no more need for a clock-dedicated transmission. This will optimize the link granting the possibility to implement other features. The design is based on two components: a numerically-controlled oscillator (NCO), in order to create a controlled frequency clock signal, and a digital phase detector (PD) to match the clock frequency with the data rate. NCOs are often coupled with a digital-to-analog converter (DAC) to create direct digital synthesizers (DDSs), which are able to produce analog waveforms of any desired frequency. In the presented case instead, the NCO generates a digital clock signal of an arbitrary frequency, while the PD manages this frequency by intercepting any shifting on the relative phase between the clock and the data. A phase aligner (PA) module guarantees that data are sampled in the middle of the eye pattern, which represents the optimal sampling point. The article presents an overview of the NCO-based CDR design and implementation, together with some tests and results in order to verify the CDR reliability. Moreover, in the last section, some other possible applications of the core are illustrated. [ABSTRACT FROM AUTHOR]

Phase rotator-based digital clock and data recovery (CDR) using multi-level bang-bang phase detector (ML-BBPD) and time to digital converter (TDC) is analyzed at system and circuit level. A model is proposed for calculating the quantization noise and bit error rate (BER), in order to evaluate the important parameters in CDR design. The jitter analysis is done based on the probability density function achieved from the quantization noise error of the BBPD and TDC. The analysis of ML-BBPD is shown that by increasing the number of sampling clocks, the quantization noise and consequently the jitter and BER are significantly reduced. Also, it is shown that by improving the resolution of the TDC and increasing number of delay cells for the purpose of keeping fixed the dynamic range, the output jitter of TDC is decreased. In the proposed model and also simulation, it is approved that by increasing the ratio of RMS input Gaussian jitter to the quantization step, the output jitter reaches to its saturated value. To prove the jitter model, the goodness of fit test based on Kolmogorov–Smirnov test is used and in addition, the simulation is provided for circuit level CDR. The circuit level simulation is done in TSMC 65 nm CMOS technology. The CDR is worked under 1 V supply voltage at 480Mbit/s bit rate useful for USB2 applications. The CDR dissipates 913 µW power and generates 0.258 ps RMS jitter, while it occupies 166 µm × 104 µm chip area. [ABSTRACT FROM AUTHOR]

A phase frequency detector (PFD) with a very low dead zone is proposed which is based on a configuration adaptable to both CMOS or carbon nano-tube transistors (CNTFETs). In the first step the proposed configuration is designed using CMOS transistors, and then CNTFETs are substituted to improve the speed and reduce the propagation delay. The proposed PFD in addition to very low dead zone, has low power consumption and high frequency range of operation, which are achieved as a result of the elimination of the reset path. The simulation results based on 32 nm technology for CNTFET and 180 nm technology for CMOS, illustrate that CNTFET-based proposed circuit dissipates 2 µW and has frequency of operation up to 30 GHz, and the dead zone equal to 1 ps. Compared to the conventional PFD based on CMOS technology, its dead zone and power consumption are lower. In addition, the effects of blocks' parameters including the phase detector, which affect the operation of the phase locked loop, or delay locked loop, are systematically analyzed. [ABSTRACT FROM AUTHOR]

Although an injection-locked oscillator (ILO) can offer excellent jitter performance on average, its intense phase modification at a given injection rate inevitably degrades spur performance, unless injection timing is carefully controlled. This work investigates a behavioral model of the ILO with digital control of a bang-bang phase detector (BBPD) on a discrete-time domain, a quantitative analysis on the dynamics of the digital injection-locked clock multiplier (ILCM) is provided. Adjusting frequency error between the free-running oscillator and the injection signal is crucial to obtain better spur performance. However, the timing offset caused by the device mismatches hinders it from being correctly compensated. Therefore, we investigate the effect of timing offset (or mismatch) between the replica cells and BBPD and then propose the time-division dual calibration (TDDC) to reduce the discrepancies. In addition, three-stage replica cells are chosen to achieve a robust operation in the phase generating aspect. By removing the residual phase offset using multiple delay cells, the optimum locking point is guaranteed. [ABSTRACT FROM AUTHOR]

This article presents an amplitude and 360° phase shift array measurement system. The basic cell of the measurement system uses a novel amplitude and phase detector based on switched dual multipliers. The phase shift measurement is characterized using an analog phase detector (mixer), detecting a maximum range of ±90°, and a double multiplication of the input signals, in phase and phase shifted. This method broadens the frequency and amplitude range beyond other solutions that require fulfilling the quadrature condition. This method broadens the frequency and amplitude beyond other solutions requiring fulfilling the quadrature condition or phase and amplitude balance. Thus, it enables to compensate significant phase imbalance in the 90° hybrid or use amplitudes out of the range that ensures the switching operation of mixer diodes. The circuit calibration that allows compensation for errors (amplitude, phase shift, mismatching, etc.) is detailed, and its relation to the required measurement accuracy is discussed. The design can be easily extrapolated to other frequency ranges because it uses commercial RF devices available in a wide frequency range and avoids the need of crossing lines or complex 90° hybrid. A prototype with $3 \times 3$ cells has been built to evaluate various test conditions on $1 \times 3$ cell configurations that show the advantages of the procedure. It should be highlighted that the cell prototype uses devices that will be operating outside the frequency and amplitude ranges recommended by their manufacturers. A calibration from 2.6 to 6 GHz and −15 to −3 dBm was performed to evaluate the measurement errors. An analysis of the isolation between cells and different calibration configurations is performed to analyze the measurement errors. Measurements show compensation of +30°/−25° phase imbalance and 13-dB power lower than mixer manufacturer recommendation. [ABSTRACT FROM AUTHOR]

This article presents a circuit for the precise vertical landing of drones based on a three phase-shifts detection of a single frequency transmitted from the landing point. The circuit can be considered as a new navigation sensor that assists in guidance corrections for landing at a specific point. The circuit has three inputs to which the signal transmitted from an oscillator located at the landing point arrives with different delays. The input signals are combined in pairs in each of the three analog phase detectors, after having passed through 3 dB at 90° hybrid couplers that guarantee a theoretical nonambiguous phase shift range of ±90°. Each output has a voltage that is proportional to the phase shift between each of the input signals, which in turn depends on the position relative to the landing point. A simple landing algorithm based on phase shift values is proposed, which could be integrated into the same flight control platform, thus avoiding the need to add additional processing components. To demonstrate the feasibility of the proposed design, a triangular phase shift detector prototype has been implemented using commercial devices. Calibration and measurements at 2.46 GHz show a dynamic range of 30 dB and a nonambiguous detection range of ±80° in the worst cases. Those specs let us track the drone during the landing maneuver in an inverted cone formed by a surface with a ±4.19 m radius at 10 m high and the landing point. [ABSTRACT FROM AUTHOR]

An accurate and cost-effective islanding detection is in a great need for distributed generation (DG) integration. An onsite contactless islanding detection scheme is proposed in this article, based on a small number of tiny and portable electric field (EF) sensors. In contrast to the existing mainstream detection techniques, which are heavily depended on the instrument transformer measurement in substations, the proposed contactless scheme is able to be deployed on the ground below the overhead feeders, enabled by a compact EF sensor and the associated accurate frequency measurement algorithm. The effectiveness, robustness, efficiency, and security advantages of the proposed method are investigated and verified by the simulations using various feeder configurations. It is further supported by the laboratory experiments based on a scale-down overhead feeder testbed. [ABSTRACT FROM AUTHOR]

Measurement of optical transfer delay (OTD) is crucial to applications such as fiber-distributed multiantenna systems, fiber-optic sensors, and high-capacity optical fiber communications. However, present OTD measurement techniques are inadequate for the demands of high accuracy, high speed, and large measurement range, simultaneously. Here, we propose a novel method based on nonlinear frequency sweeping and phase derived ranging to achieve all the above-mentioned performance. A continuous-wave light modulated by a microwave signal propagates in a device under test. Then, the OTD is mapped into the phase variation of the microwave signal by photodetection. A microwave phase discriminator is used to extract the phase variation from the microwave signal, while the nonlinear frequency sweeping and a novel phase unwrapping algorithm are proposed to resolve $2\pi $ phase ambiguity caused by phase detection. Frequencies of the microwave swept signals are set at four selected points in a range of 10 MHz, which ensures high speed and large measurement range. Our experiment results verify an accuracy of ±0.05 ps in measuring an ultrahigh-accuracy optical delay line. In addition, long fiber is also tested, which proves that a measurement range of at least 37 km (theoretically 100 km) can be achieved. Moreover, the measurement speed reaches milliseconds per measurement. [ABSTRACT FROM AUTHOR]

We consider two related models for the propagation of a curvature sensitive interface in a time independent random medium. In both cases we suppose that the medium contains obstacles that act on the propagation of the interface with an inhibitory or an acceleratory force. We show that the interface remains bounded for all times even when a small constant external driving force is applied. This phenomenon has already been known when only inhibitory obstacles are present. In this work we extend this result to the case of - for example - a random medium of random zero mean forcing. The first model we study is discrete with a random forcing on each lattice site. In this case we construct a supersolution employing a local path optimization procedure. In the second, continuous, model we consider a random heterogenous medium consisting of localized small obstacles of random sign. To construct a stationary supersolution here, we need to pass through sufficiently many blocking obstacles while avoiding any obstacles of the other sign. This is done by employing a custom percolation argument. [ABSTRACT FROM AUTHOR]

Purpose: To evaluate vessel assessment in virtual monoenergetic images (VMI40keV) and virtual-non-contrast images (VNC) derived from venous phase spectral detector computed tomography (SDCT) acquisitions in comparison to arterial phase and true non-contrast (TNC) images. Methods: Triphasic abdominal SDCT was performed in 25 patients including TNC, arterial and venous phase. VMI40keV and VNC were reconstructed from the venous phase and compared to conventional arterial-phase images (CIart), TNC and conventional venous-phase images (CIven). Vessel contrast and virtual contrast removal were analyzed with region-of-interest-based measurements and in a qualitative assessment. Results: Quantitative analysis revealed no significant attenuation differences between TNC and VNC in arterial vessels (p-range 0.07–0.47) except for the renal artery (p = 0.011). For venous vessels, significant differences between TNC and VNC were found for all veins (p < 0.001) except the inferior vena cava (p = 0.26), yet these differences remained within a 10 HU range in most patients. No significant attenuation differences were found between CIart/VMI40keV in arterial vessels (p-range 0.06–0.86). Contrast-to-noise ratio provided by VMI40keV and CIart was equivalent for all arterial vessels assessed (p-range 0.14–0.91). Qualitatively, VMI40keV showed similar enhancement of abdominal and pelvic arteries as CIart and VNC were rated comparable to TNC. Conclusion: Our study suggests that VNC and VMI40keV derived from single venous-phase SDCT offer comparable assessment of major abdominal vessels as provided by routine triphasic examinations, if no dynamic contrast information is required. [ABSTRACT FROM AUTHOR]

The output of a Digital Delta-Sigma Modulator (DDSM) is always a periodic signal and the input is constant. A hybrid DDSM is a premiere to its conventional counterpart for having a potential speed, by the choice of its smaller bus. This paper offers an implementation for multi-stage noise shaping (MASH) DDSMs that includes four modulators named hybrid DDSM-1, DDSM-2, DDSM-3, and DDSM-4. Also, it introduces a new solution, where the desired ratio in fractional frequency synthesizers is formed by combining four different modulos. The first stage modulator is a programmable modulus EFM1 and has a modulus M1 that is not a power of 2. The second, third, and fourth stage modulators are modified MASH 1-1, multi-modulus MASH 1-1-1, and the efficiently dithered MASH 1-1-1-1 modulator that have conventional modulus M2, M3, and M4, respectively. The M1 modulus is optimally selected to synthesize the new structure of the desired frequencies. Design results confirm the suppositional predictions. In addition, the results of the circuit implementation proposed method offer a 17% reduction in hardware complexity. [ABSTRACT FROM AUTHOR]

This article proposes compact expressions for the jitter in clock and data recovery (CDR) circuits based on bang-bang phase detector including the phase noise of the transmitter and receiver oscillators as well as the quantization noise associated with the finite number of phases of the phase interpolator (PI) that align the receiver clock to the incoming data. Different approaches to perform the Early/Late detection on deserialized data and edge samples are compared: the use of majority voting degrades the CDR bandwidth, increasing the impact of the clock jitter on the CDR jitter; on the other hand, counting the single Early/Late occurrences does not degrade the bandwidth but increases the noise related to the finite phases of the PI. The proposed analytical formulas are validated against event-driven behavioral simulations of the CDR system including free-running oscillators as well as phase-locked loop (PLL) for clock generation. [ABSTRACT FROM AUTHOR]