Search

Wireless sensors and actor networks (WSANs) have been widely used in various fields, from basic data collection to precise real-time control and monitoring, including battlefield monitoring, rescue, and exploration. The actor nodes in a WSAN play a key role in processing and transmitting data, and because of the harsh environmental conditions encountered, network node failures are prone to occur. The failure of an actor causes a loss of connectivity with its neighbor nodes, resulting in network splits and failure to deliver messages between nodes. Therefore, determining how to quickly and autonomously recover network connectivity while minimizing the moving distance of backup nodes and the number of relocated nodes is crucial. In this paper, we propose a dynamic weight-based connectivity recovery (DWCR) method to minimize the total moving distance of actor nodes, the number of relocated nodes, the total messages sent, and the coverage loss rate. The proposed DWCR method involves selecting a backup node for each critical node by dynamically adjusting the weight. If a critical node fails, the backup node starts to move to restore the connectivity of the failed node. The simulation results indicate that the proposed DWCR method outperforms the recovery through inward motion (RIM) method and other methods in terms of minimizing the total moving distance, the number of relocated nodes, and the total messages sent. However, because the RIM algorithm requires the relocation of more nodes during the network process, the DWCR algorithm is slightly inferior to the RIM algorithm in terms of coverage loss rate. Nevertheless, the DWCR algorithm still outperforms the distributed actor recovery algorithm and the distributed autonomous connectivity restoration method based on finite state machine algorithm. [ABSTRACT FROM AUTHOR]

Discrete states linked together by events can describe a series of classical video game scenarios. Therefore, the formal concept of automata seems appropriate for describing such games. However, as simple finite automata need to keep track of past events, they are less appropriate for complex designs. By contrast, push-down automata featuring a stack present better capabilities in this context. This paper discusses an enhanced version of the classic PAC-MAN game with push-down automata. The modular design of this game allows the extraction of discrete states, and its minimalist concept enables various approaches and new versions without sacrificing its original essence. Using push-down automata expanded the game with new features, allowing an enhanced game experience. The automaton controls all aspects of the game, ensuring a consistent gameplay. The presented project demonstrates the capabilities of push-down automata in the gaming industry and their potential in future game development projects. [ABSTRACT FROM AUTHOR]

Recently, Solecki [Forum Math. Sigma 7 (2019), p. 40] introduced the notion of Ramsey monoid to produce a common generalization to theorems such as Hindman's theorem, Carlson's theorem, and Gowers' FIN_k theorem. He proved that an entire class of finite monoids is Ramsey. Here we improve this result, enlarging this class and finding a simple algebraic characterization of finite Ramsey monoids. We extend in a similar way a result of Solecki regarding a second class of monoids connected to the Furstenberg-Katznelson Ramsey theorem. The results obtained suggest a possible connection with Schützenberger's theorem and finite automata theory. [ABSTRACT FROM AUTHOR]

This paper presents the modelling technique of deterministic finite automata (DFA) of the procedure for controlling variables by solvers of different ages and educational backgrounds when solving a proportionality problem in a situation of constant rectilinear motion. The study is framed within the context of research aimed at characterizing cognitive change when solving proportionality tasks posed through interactive software. To demonstrate the potential of the DFA technique, the analysis of 2 cases is documented, regarding the frequency of transition towards different forms of using control variables. [ABSTRACT FROM AUTHOR]

We investigate connections between near-rings and cellular automata. Near-rings are the nonlinear generalisation of rings. Collections of linear cellular automata are rings, the generalisation to near-rings allows us to look at nonlinear cellular automata in an algebraic setting, providing new tools. We show that cellular automata with group structured state sets form a centralizer near-ring under composition and cell-wise addition. The property of being a unit is undecidable in certain near-rings of cellular automata, introducing a new type of undecidability into near-ring theory. Non continuous, infinite radius generalised cellular automata are investigated. The continuous near-ring of cellular automata with finite arity local functions is shown to be 2-primitive. The radical for cellular automata on a finite space group is shown to be large, in contrast to the case of torsion free space groups. The quotient near-ring is determined in this case. [ABSTRACT FROM AUTHOR]

Currently, distributed real-time control systems need the creation of devices that perform online computing operations close to the sensor. The proposed online-computers of elementary mathematical functions can be used as components for the functional conversion of signals in the form of pulse streams received from measuring sensors with frequency output. Objective. The objective of the study is the development of mathematical, architectural and automata models for the design of bit-stream online-computers of elementary mathematical functions in order to create a unified approach to their design, due to which the accuracy of calculating functions can be increased, functional capabilities expanded, hardware costs reduced, and design efficiency increased. Method. Mathematical models of devices were developed using the method of forming increments of ascending step functions based on inverse functions with minimization of calculation error. Automata models of online-computers based on Moore’s Finite State Machine have been developed, the graph diagrams of which made it possible to ensure the clarity of function implementation algorithms, to increase visibility and invariance of implementation in formal languages of programming and hardware description. Results. The paper presents the results of research, development and practical approbation of design models of bit-stream onlinecomputers of power functions and root extraction function. A generalized architecture of an online-computer was proposed. Conclusions. The considered functional online-computers are effective from the point of view of calculation accuracy, simplicity of technical implementation, and universality of the architecture. [ABSTRACT FROM AUTHOR]

In many digital systems, various sequential blocks are used. This paper is devoted to the case where the model of a Mealy finite state machine (FSM) represents the behaviour of a sequential block. The chip area occupied by an FSM circuit is one of the most important characteristics used in logic synthesis. In this paper, a method is proposed which aims at reducing LUT counts for FPGA-based Mealy FSMs with transformation of state codes into FSM outputs. This is done using the combined state codes. Such an approach allows excluding a block of transformation of binary state codes into extended state codes. The proposed method leads to LUT-based Mealy FSM circuits having exactly three levels of logic blocks. Under certain conditions, each function for any logic level is represented by a circuit including a single LUT. The proposed approach is illustrated with an example of synthesis. The results of experiments conducted using standard benchmarks show that the proposed method produces LUT-based FSM circuits with significantly smaller LUT counts than is the case for circuits produced by other investigated methods (Auto and One-hot of Vivado, JEDI, and transformation of binary codes into extended state codes). The LUT count is decreased by an average of 17.96 to 91.8%. Moreover, if some conditions are met, the decrease in the LUT count is accompanied with a slight improvement in the operating frequency compared with circuits based on extended state codes. The advantages of the proposed method multiply with increasing the numbers of FSM inputs and states. [ABSTRACT FROM AUTHOR]

An FPGA based alarm system, available of using unlimited number of inputs was programmed and put in use, in this work. A low cost FPGA RZ Easy A 2.2 was used, with its four dip or button switches acting as inputs. As soon as one or more switches are ON (bit 1), the respective LED lights on, while at the same time, seven segment display shows the number of ON state inputs, corresponding, for example, to the opened doors of a house. Simultaneously the buzzer clock algorithm is activated leading buzzer to sound. If all switches go manually to OFF state (bit 0), then all LEDs are off, buzzer stops sounding and seven segment display shows zero, thus indicating for example, that no house entries are open. The above function resembles a finite state machine, since the output state, depends on the inputs of the system. The VHDL code of our system gives the opportunity of having no limitation on the number of inputs and also the ability of changing the ringing rate of the buzzer. [ABSTRACT FROM AUTHOR]

The process control-oriented threat, which can exploit OT (Operational Technology) vulnerabilities to forcibly insert abnormal control commands or status information, has become one of the most devastating cyber attacks in industrial automation control. To effectively detect this threat, this paper proposes one functional patternrelated anomaly detection approach, which skillfully collaborates the BinSeg (Binary Segmentation) algorithm with FSM (Finite State Machine) to identify anomalies between measuring data and control data. By detecting the change points of measuring data, the BinSeg algorithm is introduced to generate some initial sequence segments, which can be further classified and merged into different functional patterns due to their backward difference means and lengths. After analyzing the pattern association according to the Bayesian network, one functional state transition model based on FSM, which accurately describes the whole control and monitoring process, is constructed as one feasible detection engine. Finally, we use the typical SWaT (SecureWater Treatment) dataset to evaluate theproposedapproach, and the experimental results showthat: for one thing, comparedwithother changepoint detection approaches, the BinSeg algorithm can be more suitable for the optimal sequence segmentation of measuring data due to its highest detection accuracy and least consuming time; for another, the proposed approach exhibits relatively excellent detection ability, because the average detection precision, recall rate and F1-score to identify 10 different attacks can reach 0.872, 0.982 and 0.896, respectively. [ABSTRACT FROM AUTHOR]

Concepts of generalized commutative intuitionistic fuzzy finite state machines and generalized switching intuitionistic fuzzy finite state machines are proposed in this paper, and properties of these two kinds of intuitionistic fuzzy finite state machines are investigated. By using the conditions associated with generalized commutativity, a kind of congruences of intuitionistic fuzzy finite state machines is defined. Homomorphic properties of generalized commutative intuitionistic fuzzy finite state machine are also discussed. Moreover, products of generalized commutative intuitionistic fuzzy finite state machines and products of generalized switching intuitionistic fuzzy finite state machines are studied, and some related properties are proved. [ABSTRACT FROM AUTHOR]

We present an application of strategy synthesis to enforce spatial properties. This is achieved by implementing a toolchain that enables the tools CATLib and VoxLogicA to interact in a fully automated way. The Contract Automata Library (CATLib) is aimed at both composition and strategy synthesis of games modelled in a dialect of finite state automata. The Voxel-based Logical Analyser (VoxLogicA) is a spatial model checker for the verification of properties expressed using the Spatial Logic of Closure Spaces on pixels of digital images. We provide examples of strategy synthesis on automata encoding motion of agents in spaces represented by images, as well as a proof-of-concept realistic example based on a case study from the railway domain. The strategies are synthesised with CATLib, while the properties to enforce are defined by means of spatial model checking of the images with VoxLogicA. The combination of spatial model checking with strategy synthesis provides a toolchain for checking and enforcing mobility properties in multi-agent systems in which location plays an important role, like in many collective adaptive systems. We discuss the toolchain's performance also considering several recent improvements. [ABSTRACT FROM AUTHOR]

In this letter, a high‐speed and low‐latency Ron Rivest‐4 (RC4) encryption algorithm is designed based on SMIC 14 nm process. Since the key issue of limiting the throughput of RC4 encryption algorithm is the swapping operation of S‐box, this proposed design is capable of achieving four swapping operations of S‐box within a clock cycle by utilizing fully combinational logic designs and advanced computations. All 256 swapping operations of key scheduling algorithm (KSA) can be done in 64 clock cycles. Moreover, the novel design greatly improves the encryption efficiency of RC4 since each clock cycle offers 4 bytes of key stream. The whole area can be further optimized by reusing the existing modules, and a lightweight countermeasure is embedded into the RC4 design to break the correlation between the processed data and power dissipation against differential power analysis (DPA) attacks. Finally, the whole design is assessed by the SMIC 14 nm process design kits (PDK). The corresponding clock frequency, throughput, area, and latency, respectively, are achieved as 1 GHz, 32 Gbps, 51,596 μm2, and 74 clock cycles. [ABSTRACT FROM AUTHOR]

Summary: This brief proposes a new lightweight authenticated encryption algorithm SIMON‐GCM for Internet of Things (IoT) security, which realizes the combination of SIMON block cipher and Galois/Counter Mode (GCM). The designed SIMON circuit supports 128/192/256‐bit key size, which improves the flexibility and enlarges the range of applications. Moreover, the scheme of 32‐cycle Galois field (GF) multiplier in GF(2128) is adopted to effectively reduce the hardware cost of the Galois Hash (GHASH) function in GCM. At the same time, a finite state machine (FSM) is used to run the SIMON and GHASH modules in parallel, thus shortening the authenticated encryption time. The whole circuit is designed and implemented in field programmable gate array (FPGA) platforms. It is measured to yield a throughput of 32.4 Gbps when consuming 331 slices in Artix‐7. Compared with the existing authenticated encryption algorithms, the proposed algorithm achieves lower resource consumption and better flexibility. [ABSTRACT FROM AUTHOR]

We investigate the state complexity of languages resulting from the cascade product of two minimal deterministic finite automata with  n and  m states, respectively. More precisely we study the magic number problem of the cascade product operation and show what range of complexities can be produced in case the left automaton is unary, that is, has only a singleton letter alphabet. Here we distinguish the cases when the involved automata are reset automata, permutation automata, permutation-reset automata, or do not have any restriction on their structure. It turns out that the picture on the obtained state complexities of the cascade product is diverse, and for all cases, except where the left automaton is a unary permutation(-reset) or a deterministic finite automaton without structural restrictions, and the right one is a reset automaton or a deterministic finite automaton without structural restrictions, we are able to identify state sizes that cannot be reached — these numbers are called "magic." [ABSTRACT FROM AUTHOR]

We investigate the state complexity of the permutation operation, or the commutative closure, on Alphabetical Pattern Constraints (APCs). This class corresponds to level  3 / 2 of the Straubing-Thérien hierarchy and includes the finite, the piecewise testable, or -trivial, and the ℛ -trivial and ℒ -trivial languages. We give a sharp state complexity bound expressed in terms of the longest strings in the unary projection languages of an associated finite language. Additionally, for a subclass, we give sharp bounds expressed in terms of the size of a recognizing input automaton and the size of the alphabet. We also state a related state complexity bound for the commutative closure on finite languages. Lastly, we investigate the language inclusion, equivalence and universality problems on APCs up to permutational, or Parikh, equivalence. These problems are known to be P S P A C E -complete on APCs in general, even for fixed alphabets. We show them to be decidable in polynomial time for fixed alphabets if we only want to solve them up to Parikh equivalence. We also correct a mistake from the conference version in a bound on the size of recognizing automata for the commutative closure. [ABSTRACT FROM AUTHOR]

In the Fourth Industrial Revolution, crime is hardly reported to the Police, or other law enforcement agencies. Most victims prefer to go to Social Media and vent, as this medium is easier for them to access and requires no paperwork or interrogations. This trend leaves policy makers and the law enforcers with skewed dataset, due to unreported crimes. Hence, it is paramount that one finds a way to “mine” the crime data reported on social media. In this paper, we have attempted to estimate crime rates, using Twitter as a data source. To do this, we have used a formal technique — Jumping Finite Automata (JFA), for the abstraction of a corpus of crimerelated words and used shuffle algorithms to establish semantic relationships between these words. The JFA was implemented in a tool called “Crime-Ripper”. Crime-Ripper uses tweets retrieved from crime hashtags on Twitter to estimate crime rates and produce reports that are map annotations, showing areas of a city and their respective estimated crime-rates. CrimeRipper is expected to find applications in law enforcement, policy making and public safety sensitization. [ABSTRACT FROM AUTHOR]

Distributed systems have been a hot topic of study in recent years. In general, a distributed system is defined as a computer system implemented within a computer network in which both software and hardware components located on computers within the network communicate and coordinate their actions via messages. Optimizing the performance of distributed web systems has become a top priority in the current context of technological evolution and the continuous growth in the number of users and online traffic. These systems are fundamental to delivering services and content to users worldwide, but the ever-increasing demands for availability and scalability have brought new challenges. Finite state machines are a powerful and flexible technique for modelling distributed systems using the Python language. Finite state machines are popular for modelling distributed systems due to the fact that they represent an easy and flexible way to represent these systems, and together with the Python language, they manage to model complex systems. The two are used to illustrate complex system behaviour, communication between system nodes, node synchronization, error handling, and performance optimization. In this study, various strategies and techniques for optimizing their performance have been analysed. [ABSTRACT FROM AUTHOR]

To study the braking process of the train under different adhesion conditions, this paper takes the braking system of a single rail vehicle as the research object. The author establishes a corresponding co‐simulation platform based on MATLAB/Simulink and AMESim, including the sub‐models of braking control, vehicle brake longitudinal dynamics and air brake unit. Considering the cleaning effect caused by large sliding, the author builds a suitable adhesion model for different adhesion conditions based on the improved Polach model, which is the input of the vehicle braking longitudinal dynamics sub‐model. Based on the finite state machine, the anti‐skid control algorithm of the train is constructed as the core of the brake control sub‐model, which can judge the motion state of the wheelset, and control the stage release and hold of the brake cylinder pressure. According to the International Standard EN15595 and the actual operating parameters of a certain type of train, the braking process of the train under dry and wet rail conditions is simulated on the platform. The validity of the model is verified, which provides a reliable method for future research on the braking process. [ABSTRACT FROM AUTHOR]

Due to the accelerated growth of the world's population, food security and sustainable agricultural practices have become essential. The incorporation of Artificial Intelligence (AI)-enabled robotic systems in cultivation, especially in greenhouse environments, represents a promising solution, where the utilization of the confined infrastructure improves the efficacy and accuracy of numerous agricultural duties. In this paper, we present a comprehensive autonomous navigation architecture for holonomic mobile robots in greenhouses. Our approach utilizes the heating system rails to navigate through the crop rows using a single stereo camera for perception and a LiDAR sensor for accurate distance measurements. A finite state machine orchestrates the sequence of required actions, enabling fully automated task execution, while semantic segmentation provides essential cognition to the robot. Our approach has been evaluated in a real-world greenhouse using a custom-made robotic platform, showing its overall efficacy for automated inspection tasks in greenhouses. [ABSTRACT FROM AUTHOR]

Covering problems find applications in many areas of computer science and engineering, such that numerous combinatorial problems can be formulated as covering problems. Combinatorial optimization problems are generally NPhard problems that require an extensive search to find the optimal solution. Exploiting the benefits of quantum computing, we present a quantum oracle design for covering problems, taking advantage of Grover’s search algorithm to achieve quadratic speedup. This paper also discusses applications of the quantum counter in unate covering problems and binate covering problems with some important practical applications, such as finding prime implicants of a Boolean function, implication graphs, and minimization of incompletely specified Finite State Machines. [ABSTRACT FROM AUTHOR]

Text-to-speech (TTS) is a technology that converts text into sound using a phonetization system and is especially useful to be applied to blind aids who need information in the form of sound because of their limitations. To help the visually impaired know their health conditions where the visually impaired feel limited to going out during the pandemic. For this reason, it is necessary to make an aid that can read text-based data such as body temperature, heart rate per minute, and oxygen levels into a voice that can be heard by the blind, the method used in this study is finite state automata (FSA) which is used to split Indonesian words into words according to its syllable patterns and facilitate the pronunciation process which is included in the blind aids so that it is expected to help the visually impaired to be able to find out their health condition. In this study, the test was carried out using the confusion matrix method and the results obtained were 100% accurate, 99.71% accuracy of temperature sensor, 98% accuracy of heart rate, and 95% accuracy of oxygen saturation. [ABSTRACT FROM AUTHOR]

Reservoir computers (RCs) and recurrent neural networks (RNNs) can mimic any finite-state automaton in theory, and some workers demonstrated that this can hold in practice. We test the capability of generalized linear models, RCs, and Long Short-Term Memory (LSTM) RNN architectures to predict the stochastic processes generated by a large suite of probabilistic deterministic finite-state automata (PDFA) in the small-data limit according to two metrics: predictive accuracy and distance to a predictive rate-distortion curve. The latter provides a sense of whether or not the RNN is a lossy predictive feature extractor in the information-theoretic sense. PDFAs provide an excellent performance benchmark in that they can be systematically enumerated, the randomness and correlation structure of their generated processes are exactly known, and their optimal memory-limited predictors are easily computed. With less data than is needed to make a good prediction, LSTMs surprisingly lose at predictive accuracy, but win at lossy predictive feature extraction. These results highlight the utility of causal states in understanding the capabilities of RNNs to predict.

Inferring a functional specification from an existing digital design is a challenge that is suitable with reverse-engineering methods. One of the most widely used functional specification formats is a finite state machine (FSM). This article studies the possibility of blind passive specification mining for a digital device, where the device is treated as a "black box". The presented approach treats an input and output signal waveform as the transition graph of an incomplete deterministic FSM and learns the FSM through FSM minimization. It employs a Boolean satisfiability problem (SAT) solver to find a minimal FSM that complies with observed object behavior. The known approach to identifying state machines in discrete event systems is adapted to operate with variables in the form of coloring and transition tables. The developed implementation produces a synthesizable specification in hardware description language (HDL) and a state diagram in unified modeling language (UML). The proposed approach for inferring an FSM from a waveform trace can serve as a supplementary tool during reverse engineering to provide developers with meaningful insight regarding the analyzed device. The presented case study defines metrics of successful FSM inference and applies them to a synthetic FSM and a real-world example FSM to demonstrate the applicability of the approach. [ABSTRACT FROM AUTHOR]

The process of electrospinning is over a century old, yet novel material and method achievements, and later the addition of nanomaterials in polymeric solutions, have spurred a significant increase in research innovations with several unique applications. Significant improvements have been achieved in the development of electrospun nanofibrous matrices, which include tailoring compositions of polymers with active agents, surface functionalization with nanoparticles, and encapsulation of functional materials within the nanofibers. Recently, sequentially combining fabrication of nanofibers with 3D printing was reported by our group and the synergistic process offers fiber membrane functionalities having the mechanical strength offered by 3D printed scaffolds. Recent developments in electrospun nanofibers are enumerated here with special emphasis on biomedical technologies, chemical and biological sensing, and energy harvesting aspects in the context of e-textile and tactile sensing. Energy harvesting offers significant advantages in many applications, such as biomedical technologies and critical infrastructure protection by using the concept of finite state machines and edge computing. Many other uses of devices using electrospun nanofibers, either as standalone or conjoined with 3D printed materials, are envisaged. The focus of this review is to highlight selected novel applications in biomedical technologies, chem.-bio sensing, and broadly in energy harvesting for use in internet of things (IoT) devices. The article concludes with a brief projection of the future direction of electrospun nanofibers, limitations, and how synergetic combination of the two processes will open pathways for future discoveries. [ABSTRACT FROM AUTHOR]

Hardware architecture optimized for implementing the elliptic-curve Diffie–Hellman ephemeral (ECDHE) on 256-bit Montgomery elliptic curves presents unique challenges, particularly for resource-constrained IoT and mobile devices. This work aims to provide an efficient hardware implementation of ECDHE on Curve25519, including a dedicated finite state machine (FSM) designed to handle point multiplication and ECDHE operations, utilizing constant-time algorithms and a unified memory block for resource management. Additionally, we introduce an optimized modular computation unit that covers modular addition, subtraction, multiplication, and inversion. Our proposed hardware architecture enhances the efficiency of ECDHE operations while maintaining low resource utilization, considerably reduced latency, and low power consumption. Synthesized on the Xilinx Artix-7 platform, our design boasts 64,000 Slices and a clock speed of 102 MHz, and it computes an ECDHE scalar multiplication operation in 1.1 ms, consuming 117 mW. The proposed hardware design can be applied to various platforms, including mobile devices and IoT systems. [ABSTRACT FROM AUTHOR]

The grain texture of the as-printed material evolves during the laser-based powder bed fusion (PBF-LB) process. The resulting mechanical properties are dependent on the obtained grain texture and the properties vary depending on the chosen process parameters such as scan velocity and laser power. A coupled 2D Cellular Automata and Finite Element model (2D CA-FE) is developed to predict the evolution of the grain texture during solidification of the nickel-based superalloy 625 produced by PBF-LB. The FE model predicts the temperature history of the build, and the CA model makes predictions of nucleation and grain growth based on the temperature history. The 2D CA-FE model captures the solidification behavior observed in PBF-LB such as competitive grain growth plus equiaxed and columnar grain growth. Three different nucleation densities for heterogeneous nucleation were studied, 1 × 1011, 3 × 1011, and 5 × 1011. It was found that the nucleation density 3 × 1011 gave the best result compared to existing EBSD data in the literature. With the selected nucleation density, the aspect ratio and grain size distribution of the simulated grain texture also agrees well with the observed textures from EBSD in the literature. [ABSTRACT FROM AUTHOR]

A finite automaton can be either deterministic (DFA) or nondeterministic (NFA). An automaton‐based task is in general more efficient when performed with a DFA rather than an NFA. For any NFA there is an equivalent DFA that can be generated by the classical Subset Construction algorithm. When, however, a large NFA may be transformed into an equivalent DFA by a series of actions operating directly on the NFA, Subset Construction may be unnecessarily expensive in computation, as a (possibly large) deterministic portion of the NFA is regenerated as is, a waste of processing. This is why a conservative algorithm for NFA determinization is proposed, called Quick Subset Construction, which progressively transforms an NFA into an equivalent DFA instead of generating the DFA from scratch, thereby avoiding unnecessary processing. Quick Subset Construction is proven, both formally and empirically, to be equivalent to Subset Construction, inasmuch it generates exactly the same DFA. Experimental results indicate that, the smaller the number of repair actions performed on the NFA, as compared to the size of the equivalent DFA, the faster Quick Subset Construction over Subset Construction. [ABSTRACT FROM AUTHOR]

Due to the growing interest in climbing, increasing importance has been given to research in the field of non-invasive, camera-based motion analysis. While existing work uses invasive technologies such as wearables or modified walls and holds, or focuses on competitive sports, we for the first time present a system that uses video analysis to automatically recognize six movement errors that are typical for novices with limited climbing experience. Climbing a complete route consists of three repetitive climbing phases. Therefore, a characteristic joint arrangement may be detected as an error in a specific climbing phase, while this exact arrangement may not considered to be an error in another climbing phase. That is why we introduced a finite state machine to determine the current phase and to check for errors that commonly occur in the current phase. The transition between the phases depends on which joints are being used. To capture joint movements, we use a fourth-generation iPad Pro with LiDAR to record climbing sequences in which we convert the climber's 2-D skeleton provided by the Vision framework from Apple into 3-D joints using the LiDAR depth information. Thereupon, we introduced a method that derives whether a joint moves or not, determining the current phase. Finally, the 3-D joints are analyzed with respect to defined characteristic joint arrangements to identify possible motion errors. To present the feedback to the climber, we imitate a virtual mentor by realizing an application on the iPad that creates an analysis immediately after the climber has finished the route by pointing out the detected errors and by giving suggestions for improvement. Quantitative tests with three experienced climbers that were able to climb reference routes without any errors and intentionally with errors resulted in precision–recall curves evaluating the error detection performance. The results demonstrate that while the number of false positives is still in an acceptable range, the number of detected errors is sufficient to provide climbing novices with adequate suggestions for improvement. Moreover, our study reveals limitations that mainly originate from incorrect joint localizations caused by the LiDAR sensor range. With human pose estimation becoming increasingly reliable and with the advance of sensor capabilities, these limitations will have a decreasing impact on our system performance. [ABSTRACT FROM AUTHOR]

Micro-Electro-Mechanical System (MEMS) capacitive accelerometers have received extensive attention in recent years due to their excellent performance indicators; especially in the fields of noise, power consumption, and bias instability, great development and progress have been made. In the field of noise, effective noise reduction is achieved by introducing oversampling modulation technology combined with digital noise reduction technology. In power consumption, the power consumption of the accelerometer is effectively reduced by using the successive approximation structure in the interface circuit and using the finite state machine for precise control. In bias instability, the effects of temperature offset and zero-point drift are suppressed by using a hybrid topology connection structure in the interface circuit, and an effective reduction of bias instability is achieved. In this paper, the research and progress of MEMS capacitive accelerometer in the field of noise, power consumption and bias instability are reviewed, and the articles published in recent years are listed and summarized and prospected. [ABSTRACT FROM AUTHOR]

High-performance computers are used for computation-intensive tasks. It is essential for these systems to simultaneously execute several computation-intensive tasks for efficient and timely system utilization. Since typical tasks have a longer runtime, it is essential to determine the runtime of each task prior to execution and schedule them accordingly. We propose a method for predicting the runtime of MPI-based software. Initially, we analyze the source code of the software by translating the code to finite automata and measuring the state complexity. Next, the runtime of software is trained using a deep neural network (DNN) along with its state complexity. Herein, we propose three models based on DNN, statistics and their hybrid. DNN model is superior in comparison. Additionally, the adaptability of our method is demonstrated by showing that our method can adapt on new environment with 90% accuracy on various software. [ABSTRACT FROM AUTHOR]

The design of System-on-Chip systems using synchronous circuits involves complex clock distribution strategies, which envisage challenges for designers to integrate large-scale systems. Globally Asynchronous Locally Synchronous architectures containing asynchronous port controllers encapsulated in the self-timed wrapper have been adopted in this work. These port controllers communicate through Asynchronous Finite State Machines defined by Signal Transition Graphs are implemented adopting the C element. This GALS architecture implemented for the point-to-point interface can also be modified for the multipoint interface. The proposed methodology uses a two-phase handshake protocol to communicate between two Locally Synchronous modules as it has fewer signal transitions, which, in turn, reduces latency. In this paper, the Queue Direct Memory Access subsystem is implemented using the Vivado simulator on UltraScale+™ device at a maximum frequency of 257.4MHz, and various parameters are reported. A comparison shows that the proposed wrapper has improved latency time of 53%, with a reduction in power dissipated by 27% and an increase in gate count by 13%. [ABSTRACT FROM AUTHOR]

The problem of scheduling household appliances with the availability of renewable energy is the biggest challenge in the smart home energy management system. The components such as renewable energy resources, household appliances, utility grid, storage batteries are pooled into a nonlinear, time-varying, indefinite, and dynamic structure that is impossible to control and refine. For this, real-time pricing is applied in most nations to withstand the burden on the grid. This requires attention to utilize renewable energy effectively. In this paper, a load scheduling method to schedule the loads based on the availability of solar energy and customer preferences is presented. First, the availability of solar energy is forecasted ahead one day using Regression Analysis. Second, the finite state machine approach-based load scheduling algorithm is implemented and tested using MATLAB Simulink and Lab VIEW. LabVIEW-based GUI is developed to visualize the MATLAB schedule for loads. The problem is divided into several states with the availability of solar power, and if solar power is unavailable, grid power is utilized. The loads preferred by the consumers are scheduled in alignment with the production of solar power with the finite state machine scheduling algorithm. Also, the loads considered are able to consume instantaneous energy with the instantaneous production of energy, thereby reducing CO2 emission by not consuming power from the grid. Finally, the loads are scheduled accordingly, and it is concluded that coordination can be established between energy providers, and the system proposed can flatten out the load profile. [ABSTRACT FROM AUTHOR]

Regular path query is a technique of using regular expressions to query graph data, usually uses finite state automata to achieve query matching. The matching result of the existing regular path query method is a sequence of vertex pairs, and the structure of the graph is not fully preserved. In order to solve this problem, this paper proposed a method of structured regular path query for graph data. By structuring constraints between different sequences, the query results could be transformed from paths to subgraphs. For this purpose, the method firstly defined a structured regular path query language, and then designed a structured query parsing and a matching algorithm based on this structure. Experimental results on simulated and real datasets verify the influence of network size on query speed. This paper compared the proposed method with the control group. Experimental results show that the proposed method can realize structured query under the premise of satisfying regular expression constraints. [ABSTRACT FROM AUTHOR]

A nondeterministic automaton is history-deterministic if its nondeterminism can be resolved by only considering the prefix of the word read so far. Due to their good compositional properties, history-deterministic automata are useful in solving games and synthesis problems. Deciding whether a given nondeterministic automaton is historydeterministic (the HDness problem) is generally a difficult task, which can involve an exponential procedure, or even be undecidable, as is the case for example with pushdown automata. Token games provide a PTime solution to the HDness problem of Büchi and co Büchi automata, and it is conjectured that 2-token games characterise HDness for all 1-regular automata. We extend token games to the quantitative setting and analyse their potential to help deciding HDness of quantitative automata. In particular, we show that 1-token games characterise HDness for all quantitative (and Boolean) automata on finite words, as well as discounted-sum (DSum), Inf and Reachability automata on infinite words, and that 2-token games characterise HDness of LimInf and LimSup automata, as well as Sup automata on infinite words. Using these characterisations, we provide solutions to the HDness problem of Safety, Reachability, Inf and Sup automata on finite and infinite words in PTime, of DSum automata on finite and infinite words in NPnco-NP, of LimSup automata in quasipolynomial time, and of LimInf automata in exponential time, where the latter two are only polynomial for automata with a logarithmic number of weights. [ABSTRACT FROM AUTHOR]

Context. The problem of building a program model of a finite state machine with datapath of transitions using VHDL language is considered. The model synthesis process is identified with the synthesis of this type of finite state machine, since the built model can be used both for the analysis of the device's behavior and for the synthesis of its logic circuit in the FPGA basis. The object of the research is the automated synthesis of the logic circuit of the finite state machine with the datapath of transitions, based on the results of which numerical characteristics of the hardware expenses for the implementation of the state machine circuit can be obtained. This makes it possible to evaluate the effectiveness of using this structure of the finite state machine when implementing a given control algorithm. Objective. Development and research of a VHDL model of a finite state machine with datapath of transitions for the analysis of the behavior of the state machine and the quantitative assessment of hardware expenses in its logic circuit. Method. The research is based on the structural diagram of a finite state machine with datapath of transitions. The synthesis of individual blocks of the structure of the state machine is carried out according to a certain procedure by the given graph-scheme of the con-trol algorithm. It is proposed to present the result of the synthesis in the form of a VHDL description based on the fixed values of the states codes of the state machine. The process of synthesizing the datapath of transitions, the block of formation of codes of transitions operations and the block of formation of microoperations is demonstrated. VHDL description of that blocks is carried out in a synthesizable style, which allows synthesis of the logic circuit of the finite state machine based on FPGA with the help of modern CAD and obtaining numerical characteristics of the circuit, in particular, the value of hardware expenses. To analyze the correctness of the synthesized circuit, the process of developing the behavioral component of the VHDL model, the function of which is the generation of input signals of the finite state machine, is considered. The classical combination of the synthesizable and behavioral parts of the model allows presenting the results of the synthesis of a finite state machine with datapath of transitions as a separate project that can be used as a structural component of the designed digital system. Results. Using the example of an abstract graph-scheme of the control algorithm, a VHDL model of a finite state machine with datapath of transitions was developed. With the help of CAD AMD Vivado, a synthesis of the developed model was carried out and behavioral modeling of the operation of the finite state machine circuit was carried out. The results of the circuit synthesis made it possible to obtain the value of hardware expenses when implementing the circuit in the FPGA basis. According to the results of behavioral modeling, time diagrams were obtained, which testify to the correctness of the implementation of the functions of transitions and outputs of the synthesized state machine. Conclusions. In traditional VHDL models of finite state machines, the states do not contain specific codes and are identified using literals. This allows CAD to encode states at its own discretion. However, this approach is not suitable for describing a finite state machine with datapath of transitions. The transformation of states codes using a set of arithmetic and logic operations requires the use of fixed values of states codes, which determines the specifics of the VHDL model proposed in this paper. This and similar models can be used, in particular, in the study of the effectiveness of a finite state machine according to the criterion of hardware expenses in the device circuit [ABSTRACT FROM AUTHOR]

Context. The issue of a synthesizable finite state machine with temporal events processing using hardware description language pattern. The object of this study is external event processing in real-time systems. Objective. The goal of this work is to introduce methods to express external temporal events on finite state machine state diagrams and corresponding HDL patterns of such events processing in control systems. Method. The classification of external events in real-time systems is analyzed. A device class that changes its internal state depending on the temporal external events is introduced. A method to express these events on the temporal state diagram is introduced. Possible model behavior scenarios based on the external event duration are analyzed. A Verilog HDL external event processing pattern is introduced. The efficiency of the proposed model is proved by developing, verifying, and synthesis of a powersaving module in Xilinx ISE. The results and testing showed the model's correctness. Results. External temporal events processing methods in real-time device models are proposed. The corresponding HDL pattern for the proposed model implementation is presented. Conclusions. The real-time systems with external temporal events automated synthesis problem has been solved. To solve this problem, a finite state machine model-based device using the Verilog language was developed and tested. The scientific novelty lies in the introduction a method to express temporal events on the state diagram of the finite state machine as well as in a HDL when implementing the proposed model on CPLD and FPGA. [ABSTRACT FROM AUTHOR]

Writing a Javanese script is considered complicated writing for people who would learn it. The process of transliterating Latin into Javanese script cannot be done directly because each alphabet is only sometimes represented by one Javanese script. Javanese script is not depicted by one or more Latin letters, so if transliteration of Latin letters to Javanese letters is required, a parsing process is required. The rows of Javanese letters form a ligature with specific rules, so parsing is also needed to correctly arrange the rows of Javanese letters. This study aims to design a program to facilitate the transliteration of Latin script to Javanese script. Finite State Automata (FSA) is used to describe writing rules. This study is limited to lowercase letters only. Capital letters and number symbols are not discussed in this study. The results of the study are in the form of a program design that can transliterate Latin writing into Javanese. Experiments were carried out on as many as 4 structures of vowel-consonant variations. All syllabic structures that include CV, CPV, CVC, and CPVC have been tried. The transliteration results show conformity with a 100% accuracy rate by the rules of writing Javanese script. This research shows that the application of FSA can handle the transliteration of Latin letters into Javanese. [ABSTRACT FROM AUTHOR]

The model called Finite State Machine with Input Multiplexing (FSMIM) was proposed as a mechanism for implementing Finite State Machines (FSMs) using ROM memory. This paper presents a novel approach for achieving more efficient FSMIM implementations in Field Programmable Gate Array (FPGA) devices. The aim of the proposed approach is to obtain further reductions in the use of Embedded Memory Blocks (EMBs). Unlike previous works, the proposed approach reduces the depth of the ROM by grouping states before simplifying the input selectors of the FSMIM. For this purpose, a new strategy for grouping states is proposed, and its optimality is proven. In addition, a new variant of the Minimum Maximal k-Partial Matching (MMKPM) problem and its corresponding Integer Linear Programming (ILP) formulation are proposed for simplifying input selectors. The proposed approach requires a significantly smaller number of EMBs than the approaches proposed previously. [ABSTRACT FROM AUTHOR]

This work proposes a method for hardware reduction in circuits of Mealy finite state machines (FSMs). The circuits are implemented as networks of interconnected look-up table (LUT) elements. The FSMs with twofold state assignment and encoding of output collections are discussed. The method is based on using two LUT-based cores to implement systems of partial Boolean functions. One of the cores uses only maximum binary codes, while the second core is based on the use of extended state codes. The hardware reduction is based on diminishing the number of transformed maximum binary codes. This leads to FPGA-based FSM circuits with three levels of logic blocks. Each logic block has a single level of LUTs. As a result, partial functions are represented by single-LUT circuits. The article shows a step-by-step procedure for the transition from the initial form of the FSM representation to its logical circuit (a network of programmable look-up table elements, flip-flops, and interconnects). The results of experiments conducted with standard benchmarks show that the proposed approach produces LUT-based FSM circuits with significantly better area characteristics than for circuits produced by such methods as Auto and One-Hot of Vivado, JEDI, and twofold state assignment. Compared to these methods, the number of LUTs is reduced from 9.44% to 69.98%. Additionally, the proposed method leads to the following phenomenon: the maximum operating frequency is slightly improved as compared with FSM circuits based on twofold state assignment (up to 0.6%). The negative effect of these improvements is an increase in power consumption. However, it is extremely insignificant (up to 1.56%). As the values of the FSM's main characteristics grow, there is an increase in the gain from the application of the proposed method. The conditions for applying the proposed method are determined. A generalized architecture consisting of three blocks of partial functions and a method for synthesizing an FSM with this architecture are proposed. A method for selecting one of the seven architectures generated by the generalized architecture is proposed. [ABSTRACT FROM AUTHOR]

The object of research is fuzzy search algorithms based on Damerau-Levenshtein automata and Levenshtein automata. The paper examines and compares solutions based on finite state machines for efficient and fast finding of words and lines with a given editing distance in large text data using the concept of fuzzy search. Fuzzy search algorithms allow finding significantly more relevant results than standard explicit search algorithms. However, such algorithms usually have a higher asymptotic complexity and, accordingly, work much longer. Fuzzy text search using Damerau-Levenshtein distance allows taking into account common errors that the user may have made in the search term, namely: character substitution, extra character, missing character, and reordering of characters. To use a finite automaton, it is necessary to first construct it for a specific input word and edit distance, and then perform a search on that automaton, discarding words that the automaton will not accept. Therefore, when choosing an algorithm, both phases should be taken into account. This is because building a machine can take a long time. To speed up one of the machines, SIMD instructions were used, which gave a speedup of 1–10 % depending on the number of search words, the length of the search word and the editing distance. The obtained results can be useful for use in various industries where it is necessary to quickly and efficiently perform fuzzy search in large volumes of data, for example, in search engines or in autocorrection of errors. [ABSTRACT FROM AUTHOR]

The problem of extending model checking from finite state machines to procedural programs has fostered much research toward the definition of temporal logics for reasoning on context-free structures. The most notable of such results are temporal logics on Nested Words, such as CaRet and NWTL. Recently, Precedence Oriented Temporal Logic (POTL) has been introduced to specify and prove properties of programs coded trough an Operator Precedence Language (OPL). POTL is complete w.r.t. the FO restriction of the MSO logic previously defined as a logic fully equivalent to OPL. POTL increases NWTL's expressive power in a perfectly parallel way as OPLs are more powerful that nested words. In this article, we produce a model checker, named POMC, for OPL programs to prove properties expressed in POTL. To the best of our knowledge, POMC is the first implemented and openly available model checker for proving tree-structured properties of recursive procedural programs. We also report on the experimental evaluation we performed on POMC on a nontrivial benchmark. [ABSTRACT FROM AUTHOR]

The early detection of cyber threats with cyber-attacks adapted to the nature of information systems is a crucial cybersecurity problem. This problem and the task of recognizing normal and abnormal states and behavior of various processes in information systems are closely related. An additional condition is often the absence of templates, signatures, or rules of normal behavior that would allow the use of existing statistical or other known data analysis methods. We analyze the existing and propose a new method for detecting abnormal behavior without using signatures based on the finite state machine (FSM) model and the Security Information and Events Management (SIEM) system. [ABSTRACT FROM AUTHOR]

Symbolic time series analysis (STSA) plays an important role in the investigation of continuously evolving dynamical systems, where the capability to interpret the joint effects of multiple sensor signals is essential for adequate representation of the embedded knowledge. This technical brief develops and validates, by simulation, an STSA-based algorithm to make timely decisions on dynamical systems for information fusion and pattern classification from ensembles of multisensor time series data. In this context, one of the most commonly used methods has been neural networks (NN) in their various configurations; however, these NN-based methods may require large-volume data and prolonged computational time for training. An alternative feasible method is the STSA-based probabilistic finite state automata (PFSA), which has been shown in recent literature to require significantly less training data and to be much faster than NN for training and, to some extent, for testing. This technical brief reports a modification of the current PFSA methods to accommodate (possibly heterogeneous and not necessarily tightly synchronized) multisensor data fusion and (supervised learning-based) pattern classification in real-time. Efficacy of the proposed method is demonstrated by fusion of time series of position and velocity sensor data, generated from a simulation model of the forced Duffing equation. [ABSTRACT FROM AUTHOR]

We prove that the limit dynamics of any finite automata network under the parallel update schedule correspond exactly to the fixed points of a so-called strictly one-way cellular automaton. This correspondence is proven to be exact, as any strictly one-way cellular automaton can be transformed into a corresponding automata network, the limit dynamics of the latter corresponding exactly to the fixed points of the former. This transformation is operated using output functions, which have been developed in the author's previous works. [ABSTRACT FROM AUTHOR]

Nowadays chaos-based cryptography systems are widely used to protect sensitive data. A variety of chaos-based cryptosystems with software implementation has been published in the literature. However, due to the rapid growth of connected devices, the development of hardware secure and low-resource cryptographic systems is necessary. In this paper, we enhance the design of one of our software cryptosystems and then we address its FPGA-based implementation. The improvement in the design consists essentially to introduce an Initial Vector (IV) entry to the Chaotic Pseudo Random Number Generator (CPRNG) thus allowing to generate a new dynamic keys for the confusion layer (using a modified 2-D cat map) and diffusion layer (using a logistic map) with each new execution of the system. The CPRNG is formed by XORred a discrete Skew Tent Map (STM) with a discrete Piecewise Linear Chaotic Map (PWLCM). The proposed cryptosystem, which operates in Cipher Block Chaining (CBC) mode, is controlled by a Finite State Machine (FSM) to ensure that both the encryption and decryption are performed by the same reconfigurable architecture. The system is implemented on a Xilinx XC7Z020 ZYNQ FPGA platform. The results obtained in terms of hardware implementation costs (logic resources, throughput, and efficiency) and in terms of security against cryptographic attacks demonstrate the effectiveness of the proposed chaos-based cryptosystem. [ABSTRACT FROM AUTHOR]

State identification is the well-known problem in the automata theory that is aimed to determining the current or initial state of a system under test and this fact is widely used in the model-based testing of software and hardware systems. When modern systems are modeled, it is necessary to take into account the timed aspects and for this reason classical Finite State Machines (FSM) are extended by clock variables. In this work, we study the homing problem for FSMs with timeouts (TFSM). For this purpose, we introduce the notion of a timed homing sequence (HS) that is different from that for classical FSMs and propose a method for checking the existence and deriving a timed HS if it exists. A proposed method is based on the FSM abstraction of a TFSM, i.e. on a classical FSM that partially describes the behavior of a corresponding TFSM and inherits many of its properties. Since timeouts allow the system to move from state to state without input impact, we define a timed HS as a sequence that sets a TFSM to a stable state where the system can stay infinitely long waiting for an input. [ABSTRACT FROM AUTHOR]