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In this paper, an analytical model has been developed to observe the recombination losses involved in a tunnel oxide passivated contact solar cell with a carrier-selective layer constituting polycrystalline silicon (poly-Si). The main focus of this paper is to observe the contribution of each component of recombination current density and its effect on open-circuit voltage, Voc. The effect of emitter saturation current density (Joe), surface recombination velocity, substrate thickness, and doping density of carrier-selective layer on Voc has been presented. The analysis indicates that Voc = 766 mV can be achieved for Joe = 2 fA/cm2, and a doping density of poly-Si > 1021cm−3 in a c-Si/SiO2/poly-Si contact for a 50- $\mu \text{m}$ -thick substrate in case of ideal surface passivation. For identical conditions, Voc attains a lower value of 750mV for a 180- $\mu \text{m}$ -thick substrate. The dependence of Voc on bandgap of tunnel layers has also been observed by considering other materials like Si3N4 and SiC. These results from the analyticalmodel have been compared with results froma simulation using automat FOR simulation of HETerostructures v2.5 and have been found to be in good agreement with each other. [ABSTRACT FROM AUTHOR]

Highlights • I D -V G characteristics and transient drain current behaviors are investigated in 3D NAND flash devices with various body thicknesses and grain sizes. • As the body thickness decreases with the same grain size, the transient current instability and on-state current are improved. • When the grain size is increased with the same body thickness, the transient current instability and on-state current are improved. Abstract In order to verify the effects of polycrystalline Si (poly-Si) body thickness scale-down on read operation in 3D NAND flash memory which has tube type thin body, TCAD simulations and the measurements of fabricated devices are performed. I D - V G characteristics and transient drain current behaviors are investigated in 3D NAND devices with various body thicknesses and grain sizes. It has been known that drain current undershoot/overshoot is observed in poly-Si channel devices by falling/rising step gate bias. These phenomena are strongly related with transient of potential barrier height due to slow capture/emission rate of poly-Si grain boundary traps. As the body thickness decreases with the same grain size, the transient current instability, on-state current, and subthreshold-swing are improved. When the grain size is increased with the same body thickness, the transient current instability, on-state current, and subthreshold-swing are improved. [ABSTRACT FROM AUTHOR]

As an upgraded version of passivated emitter and rear cell (PERC) solar cells, the performance of tunnel oxide passivating contacts (TOPCon) solar cells is very dependent on the silicon oxide layer and poly-Si layer. We found that different crystallization rates or doping of germanium, carbon and other elements in poly-Si can change the band gap of poly-Si, which has an impact on the efficiency (E ff) of TOPCon solar cells. Therefore, the appropriate band gap is particularly important. At the same time, the internal defect of poly-Si also have great influence on the performance of solar cells. The simulated band diagram, charge carrier concentration and recombination rate were used to deeply explore the defect in poly-Si and the influence of poly-Si with different band gap on the performance of TOPCon solar cells. • As the band gap increases, the performance of TOPCon solar cell improves. • After reaching the threshold value (1.34 eV), TOPCon solar cell performance no longer changes. • The performance of TOPCon solar cell decreases rapidly as the concentration of defect states in the acceptor-like defect states increases. • TOPCon solar cell performance decreases with increasing concentration of donor-like defect states, but the change is small. [ABSTRACT FROM AUTHOR]

Screen printing of Ag paste is a key process for implementing polycrystalline-silicon/silicon oxide (poly-Si/SiO x) passivating contacts in industrial solar cells. Thereby, the formation of Ag crystallites on the Si surface is crucial for a low-ohmic contact. Recently, it has been observed that Ag crystallites are predominantly formed within the poly-Si layer and stop at the thermal SiO x, thermal interface, causing a cuboidal shape. To avoid a direct contact of the Ag crystallites with the underlying SiO x, thermal /crystalline-Si (c-Si) interface, a multilayer approach with interlayer SiO x, inter between several poly-Si layers is presented. A stack of three 50 nm poly-Si layers achieves highest cell potential. Further, the metallization process parameters are scanned to check when this cuboidal Ag crystallite shape occurs. While different amorphous-silicon (a-Si) deposition techniques show no changes, there are strong indications that the glass frit etching is responsible for a different etching mechanism causing the breakdown of the SiO x stop. [ABSTRACT FROM AUTHOR]

In this paper, we report a single grain boundary (GB) junctionless thin film transistor (JLFET) on recrystallized polycrystalline silicon (poly-Si JLFET). Using 2-D simulations, the electrical performance of the poly-Si JLFET is evaluated for different single GB locations in the channel. Without the need for creating the source and the drain regions by implantation, we demonstrate the prospect of achieving thin-film poly-Si JLFETs whose performance is reasonable for silicon film thicknesses less than 10 nm.

A single grain boundary dopingless PNPN tunnel field effect transistor (TFET) on recrystallized polycrystalline silicon is studied by varying the position of the grain boundary in the channel. The performance of the proposed device is assessed using 2-D simulations. We establish the prospect of realizing low-cost thin-film recrystallized polycrystalline tunnel FETs with: 1) low OFF-state current and low sub-threshold swing (SS) and 2) an ON-state current similar to that of a comparable single grain boundary poly-silicon thin film transistor (TFT). Our results indicate that the proposed single grain boundary dopingless PNPN TFET could be an ideal substitute for the conventional TFTs making it appropriate for low power display applications as well as the driver circuits.

A high performance gate-all-around (GAA) junctionless (JL) polycrystalline silicon nanowire (poly-Si NW) transistor with channel width of 12 nm, channel thickness of 45 nm, and gate length of 20 nm has been successfully demonstrated, based on a simplified double sidewall spacer process. Without suffering serious short-channel effects, the GAA JL poly-Si NW device exhibits excellent electrical characteristics, including a subthreshold swing of 105 mV/dec, a drain-induced barrier lowering of 83 mV/V, and a high Ion/Ioff current ratio of 7 × 108 (VG = 4 V and VD = 1 V). Such GAA JL poly-Si NW devices exhibit potential for low-power electronics and future 3-D IC applications.

Defects in solar cells can be caused during processing or through a benign event like a falling leaf when operating in an outdoor system. Shading caused by such a leaf can result in the cell operating in the reverse direction and ultimately in hotspot formation, which in turn can cause the entire cell to breakdown and essentially become a power dissipator rather than a producer. More often than not, this reverse biasing of the cell will enhance the effect of any inherent defect. In this study, poly-Si cells were reverse biased to enhance the effect of their inherent defect. These defects were then analysed using non-destructive confocal Raman spectroscopy, since this technique allows us to observe small defects in cells/material using the intensity of the transverse optic bands. The intensity of defect-induced Raman band has a direct relationship with the observed morphological defects of the reverse biased cell. The quality of the active layer was also investigated; this includes the chemical composition and the stress level which can be found through the single spectrum bandwidth. The efficiency of solar material depends on the absorption capability of the solar material, while the optical and the electrical properties to a large extent determine the absorption capability of solar cell. However, its structure, defect and stress level can offset the total optical and electronic properties. The present study reveals defect in micro-level and the stress induced in the affected region of the solar cell. Confocal Raman is suitable for characterising stresses in relation to microstructure, defect level as well as the manufacturer-induced defect in the substrate. [ABSTRACT FROM AUTHOR]

A thorough investigation was performed on various chemicals and nanocomposite materials to apply antireflection coating on the PV panel intending to improve the solar cell efficiency by generating more voltage, current, and power at maximum power point (MPP). The improvement in solar cell efficiency would indicate the efficient way of utilizing solar energy and converting into electrical energy which in turn saves lot of cost and improves the power generation. To improve the efficiency by the coating approach, the nanocomposite materials mixing with some composition of efficient chemicals demonstrates extremely encouraging change in surface inactivity, antireflection, and wanted vitality band hole of the materials. After a detailed experimentation, it is been identified that the multiwall carbon nanotube, titanium dioxide, and silicon dioxide materials demonstrate elevated efficiency in increasing the VMPP, IMPP, and PMPP when compared with uncoated cells. The investigational inferences in detailed are analyzed along with scanning electron microscopy findings and finally characterized the poly-Si solar cell with coating. Overall, there is a relative improvement of 36.45% of efficiency when compared with the uncoated cells. [ABSTRACT FROM AUTHOR]

Carrier selective junctions using a poly-silicon/ silicon oxide stack on crystalline silicon feature low recombination currents J 0 whilst allowing for low contact resistivity ρ C . We describe the limiting current transport mechanism as a combination of homogeneous tunneling through the interfacial silicon oxide layer and transport through pinholes where the interfacial silicon oxide layer is locally disrupted. We present an experimental method and its theoretical basis to discriminate between homogenous tunneling and local pinhole transport mechanisms o n n  + / n or p  + / p junctions by measuring the temperature-dependent contact resistance. Theory predicts opposing trends for the temperature dependencies of tunneling and pinhole transport. This allows identifying the dominant transport path. For the contact resistance of two differently prepared poly-Si/ silicon oxide/ c-Si junctions we either find clear pinhole-type or clear tunneling-type temperature dependence. Pinhole transport contributes more than 94 % to the total current for the sample with a 2.1 nm-thick interfacial silicon oxide that we anneal at a temperature of 1050 °C to achieve highest selectivity. In contrast pinhole transport contributes less than 35 % to the total current for the sample with a 1.7 nm-thick silicon oxide that we annealed at only 700 °C in order to avoid pinholes. [ABSTRACT FROM AUTHOR]

Summary: Solar radiation can be converted into electrical energy and generate electric power that can be utilized in multiple ways. The technological improvements have provided enormous solutions to the mankind for utilizing the solar energy although photovoltaic's (PV) by consuming sunlight. Photovoltaic is popularly known by the process of converting light to electricity. The current estimated growth by producing global power around 368 GW in 2017 and projecting 3000 to 10 000 GW by 2030. Looking at all the available solar cells, it has been observed that the dye‐sensitized solar cell (DSSC) when compared to mono‐Si or poly‐Si has been effective in its performance and also reduces production cost to a great extent. The power conversion efficiency (PCE) of DSSC has reached to a better extent and been discussed in the paper. There are other mechanisms through which the efficiency can be improved like applying the antireflection coating. Reflection is a usual phenomenon that happens when light incident from one medium to another varies in refractive index. This reflection is one of the important reasons for the loss of power in the PV Cell. So to improve the PCE, the Mono‐Si or DSSC PV Cells can be applied with a thin film antireflection coating by the nanocomposite film consisting of single‐ or multi‐wall carbon nanotubes with TiO2 and other efficient nanoparticles. This paper discusses on different kinds of nanocomposite materials, and their functionalities has been clearly given. Remarkable improvements have been recorded in the last 1 year by applying the antireflection coating; the PCE has further been increased enormously when compared to the uncoated solar cell for both DSSC and Mono‐Si PV cells. [ABSTRACT FROM AUTHOR]

The charge carrier transport mechanism of passivating contacts which feature an ultra-thin oxide layer is investigated by studying temperature-dependent current-voltage characteristics. 4-Terminal dark J-V measurements at low temperatures reveal non-linear J-V characteristics of passivating contacts with a homogeneously grown silicon oxide, which result in an exponential increase in contact resistance towards lower temperature. The attempt to describe the R(T) characteristic solely by thermionic emission of charge carriers across an energy barrier leads to a significant underestimation of the resistance by several orders of magnitude. However, the data can be described properly with the metal-insulator-semiconductor (MIS) theory if tunneling of charge carriers through the silicon oxide layer is taken into account. Furthermore, temperature-dependent light J-V characteristics of solar cells featuring passivating contacts at the rear revealed a FF drop at T < 205 K, which is near the onset temperature of the exponential increase in contact resistivity. [ABSTRACT FROM AUTHOR]

The optimum sizing ratio of the photovoltaic (PV) array capacity, compared to the nominal inverter input capacity, was determined in grid-connected PV (GCPV) systems from two points of view: energetic and economic. The optimum ratio was determined by both empirical and analytical approaches, and based on two PV arrays connected to their inverters, plus three simulated inverters. The flatness of the optimum-energy region due to the inverter characteristics was decreased when economic factors were taken into account. The energetic and economic optimum sizing intervals were defined as the sizing regions causing less than 1% losses from their corresponding optimum points. Subsequently, a compound optimum sizing interval was proposed to maximise the energy injected to the grid and minimise economic costs simultaneously. The results showed that the GCPV system with lower specific DC power generation (kW DC /kWp) and inverter/module cost ratio presented a wider interval (1.12–1.25) than the interval (1.17–1.19) of the system with higher specific DC power generation and cost ratio, for all the analysed inverters. Finally, the optimum sizing ratio was completed by considering a PV module degradation rate of 1%/year, which resulted in a 10% increase in the optimum sizing ratio for a 20-year lifetime. [ABSTRACT FROM AUTHOR]

In this letter, stacked sidewall-damascene double-layer poly-silicon trigate field effect transistors (FETs) with and without rapid thermal annealing (RTA) are successfully demonstrated using a simple fabrication method. Devices with RTA exhibit superior electrical characteristics to those without RTA owing to better crystallinity. The better crystallinity of the device with RTA results from a larger grain size and fewer defects, leading to higher field-effect mobility \mu \text {FE} compared with devices without RTA. p-type stacked sidewall-damascene double-layer poly-Si trigate FETs with RTA show excellent electrical characteristics, including an extremely low drain-induced barrier lowering (DIBL) of 7 mV/V, a steep subthreshold swing of 136 mV/decade, and high \textI \mathrm{\scriptscriptstyle ON}/\text I \mathrm{\scriptscriptstyle OFF} current ratio of 1.1\times 10^7 . The fabricated n-type stacked sidewall-damascene double-layer poly-Si trigate FETs with RTA showed a low DIBL, subthreshold swing and an \textI \mathrm{\scriptscriptstyle ON}/\textI \mathrm{\scriptscriptstyle OFF} current ratio larger than seven orders of magnitude. Their simple fabrication method makes them a promising candidate for future monolithic 3D integrated-circuit applications. [ABSTRACT FROM AUTHOR]

Polysilicon (poly-Si) grain size control is a critical issue with scaling of MOS transistors in integrated-circuit design, more so in embedded nonvolatile memory (NVM) technology. This paper investigates an approach to suppress poly-Si grain growth under a necessary additional thermal budget for 40-nm embedded NVM technology. Our studies reveal that carbon implant can suppress poly-Si grain size growth and that the implant dose rather than its energy plays a key role in controlling the grain size. Physical analysis using advanced planar transmission electron microscopy technique shows a reduction in the poly-Si grain size with an increasing carbon implant dose. The application of the carbon implant technique to sub-40 nm embedded NVM technology can therefore help to reduce SRAM V {MIN} -related failures significantly. In this paper, we present a complete process reliability case study to incorporate carbon implant as an effective solution for suppressing poly-Si grain growth, thereby eliminating the side effects of an additional thermal budget in advanced embedded NVM. [ABSTRACT FROM PUBLISHER]

We report a low knee voltage and high breakdown voltage 4H-SiC TSBS employing poly-Si/Ni dual Schottky contacts. A knee voltage was significantly improved from 0.75 to 0.48 V by utilizing an alternative low work-function material of poly-Si as an anode electrode. Also, reverse breakdown voltage was successfully improved from 901 to 1154 V due to a shrunk low-work-function Schottky region by a proposed self-align etching process between poly-Si and SiC. SiC TSBS with poly-Si/Ni dual Schottky scheme is a suitable structure for high-efficiency rectification and high-voltage blocking operation. [ABSTRACT FROM AUTHOR]

Several works have been published recently regarding firing stability of passivating contacts featuring P-doped polysilicon on an interfacial oxide (poly-Si/SiO x). Therein, a degradation was reported if the (n) poly-Si/SiO x structure was capped by a dielectric passivation layer during firing due to creation of additional defects in the interfacial oxide. In part A of this study it is shown, that P-doped (n) poly-Si/SiO x structures capped by a SiN y or SiN y /AlO z stack only degrade during firing at moderate temperatures if they previously have been annealed below the optimum annealing temperature T opt. It was found that this degradation is stronger the colder the annealing temperature was below T opt. In part B of this study it is shown, that at excess firing temperatures also samples annealed at or above T opt degrade. Again, this degradation depends on the initial annealing temperature in a similar way that the degradation is stronger the colder the annealing temperature was below T opt. Furthermore, a saturation of the measured surface recombination density was observed for set firing temperatures above 900°C, which points to a saturation of the underlying defect creation mechanism in the interfacial oxide. • (n) poly-Si/SiO x contacts annealed colder than their optimum degrade upon firing. • Firing degradation due to inefficient shielding of firing-induced defects in SiO x. • Extent of firing degradation increases with peak firing temperature. • Amount of firing-induced defects saturates above a certain peak firing temperature. [ABSTRACT FROM AUTHOR]

In this brief, a negative bias stress (NBS) induced degradation in n-type multigate polycrystalline silicon (poly-Si) thin-film transistor (TFT) is investigated. It is observed that after NBS the transfer characteristic curves shift to the negative gate bias direction and multigate TFTs degrade more than the single-gate TFTs with the same effective channel length. The observed degradation phenomenon is explained with short channel effect that is resulted from the diffusion and distribution of hole carriers in the channel, which are generated in the source/drain depletion region and swept into the channel when the junctions are reversely biased during NBS. Pronounced NBS degradation caused by increased hole carriers in the channel is also verified in NBS experiment with light illumination. [ABSTRACT FROM PUBLISHER]

We have succeeded in developing a hybrid-type temperature sensor using poly-Si thin-film transistors (TFTs) that outputs rectangle waveforms. An advantage of the conventional hybrid-type sensor is that large temperature dependences of off-leakage currents can be utilized, and it simultaneously works in a digital operation tolerant of noises. Additionally, in this paper, by connecting two conventional ones, the sensor becomes able to output rectangle waveforms, which can be easily counted. We confirm the waveform and that the sensor can detect the correct temperature. We think that it is promising to integrate this temperature sensor in some applications using TFTs. [ABSTRACT FROM PUBLISHER]

In this paper, the electrical characteristics of the Pi-gate junctionless FETs (PG JL FETs) with the in situ n+ doped poly-Si (DP-Si) fin-channels have been experimentally investigated and comprehensively discussed. The subthreshold behavior and threshold voltage of the PG JL FETs are sensitive to the channel dimensions, especially the channel width. The crystallinity, carrier mobility, and effective carrier concentration in the DP-Si films are dependent on the initial DP-Si film thicknesses, which directly influence the on current and threshold voltage of the PG JL FETs. Based on an evaluation on the subthreshold behavior and the driving current, we found that the PG JL FETs with the low/high aspect ratio (A.R. = channel thickness/channel width) are separately suitable for the low-power/high-performance applications. Among these PG JL FETs, the device with a proper A.R. (3.35) exhibits a relatively steep subthreshold swing (S.S.) of 66 mV/decade and the highest ON/OFF currents ratio ( I \mathrm{\scriptscriptstyle ON}/I \mathrm{\scriptscriptstyle OFF}) of $1.2\times 10^{{8}}$ ( {V}_{D} = {1} V). These devices are very promising candidates for future multifunctional 3-D integrated circuit applications. [ABSTRACT FROM AUTHOR]

Operation characteristics of polycrystalline silicon (poly-Si) nanowire (NW) charge-trapping (CT) flash memory devices with a SiGe and a Ge buried channel are studied and compared in this work. The poly-Si NW devices with a Ge buried channel show faster programming and erasing speeds as compared to those with a SiGe one due to a lower energy barrier in tunneling layer with more Ge composition. The retention and endurance characteristics of devices with a Ge buried channel are similar to those with a SiGe one. Ge buried channel is promising to CT flash device for 3D nonvolatile memory applications. [ABSTRACT FROM AUTHOR]

In this paper, we investigate Low Pressure Chemical Vapor Deposition (LPCVD) SiN as a gate isolation material for AlGaN/gallium nitride (GaN) MIS-high electron mobility transistor power transistors. We compared the dielectric failure by forward-biased constant-current stress time-dependent dielectric breakdown measurements and statistical Weibull analysis. Several 4” AlGaN/GaN-on-Si wafers have been processed with different gate isolations and processes. Our investigation includes the dependence of the dielectric breakdown on the process flow (influence of dry etch), the thickness of the dielectric (12–20 nm), the area scaling, and the gate electrode, where we also consider the recently presented poly-silicon electrode. Additionally, we show the influence of the current density through the gate on the charge-to-breakdown characteristics as well as the influence of the temperature on the breakdown behavior. Using the poly-silicon electrode and 20 nm LPCVD SiN as gate isolation, we achieved a charge-to-breakdown of Q\text {BD, 10~\text {mA}/\text {cm}^{2}} ={3.7} ~ \text {kC}/\text {cm}^{{2}} at \text T = 130 ^\circ \text C for j = 10 ~ \text mA/\text cm^2 . A 20-years lifetime (100 ppm, \text T = 130 ^\circ \text C ) extrapolation for a scaled area of 0.2 ~ \text mm^2 ( \buildrel \wedge \over = WG = {100} ~ \text {mm} ) leads to a positive gate voltage of V\text {G} = {9.4} ~ \text V . [ABSTRACT FROM PUBLISHER]

Au (metal) induced layer exchange and crystallization of amorphous Si ( a -Si) on corning glass (CG) in a -Si/Au/CG thin film specimen upon vacuum annealing (~ 10 − 8 mbar) is reported. The crystallization characteristics of these specimens at temperatures ranging on either side of the Au-Si eutectic temperature T e (Au-Si) are investigated. Our results shows that solid state diffusion assisted layer exchange of the a -Si and Au layer, followed by crystallization of a -Si into crystalline Si ( c -Si) occur at 350 °C (below the T e ). The upper limit to this crystallization mechanism was observed to be above the T e (Au-Si) and this continues till ~ 400 °C in the present study. Above this limit, the layer exchange phenomenon ceases and eutectic mixing reaction of Au-Si takes over to form diffusion limited crystalline aggregates of Si with different microstructural attributes. [ABSTRACT FROM AUTHOR]

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Epitaxial InxGa1–xAs is grown by metal organic vapor phase epitaxy as replacement of polycrystalline silicon (Si) channel for high-density 3-D NAND memory applications. The most challenging steps to integrate InxGa1–xAs are thoroughly discussed; their impact on the electrical performances are investigated and the tunnel oxide (TuOx) quality is assessed. InxGa1–xAs channels with a diameter down to ~45 nm and different In concentrations are obtained after using two alternative surface preparation routes: HCl and Cl2. Thanks to the lower thermal budget involved, Cl2 seems the most suitable route to preserve the thickness of the TuOx. InxGa1–xAs channels with In concentration, x, higher than 0.45 have superior conduction properties compared with poly-Si channel, showing higher I\mathrm { {on}} and transconductance. [ABSTRACT FROM AUTHOR]

Carrier selective passivated contacts composed of thin oxide, n + polycrystalline Si and metal on top of a n-Si absorber can significantly lower the recombination current density ( Jorear ≤8 fA/cm2) under the contact while providing excellent specific contact resistance (5-10 mΩ-cm2); 25.1% efficient small area cells with photolithography front contacts on boron doped selective emitter and Fz wafers have been achieved by Fraunhofer ISE using their tunnel oxide passivated contact (TOPCon) approach. This paper shows a methodology to model such passivated contact cells using Sentaurus device model, which involves replacing the TOPCon region by carrier selective electron and hole recombination velocities to match the measured Jorear of the TOPCon region as well as all the light IV values of the cell. We first validated the methodology by modeling a 24.9% reference cell. The model was then extended to assess the efficiency potential of large area TOPCon cells on commercial grade n-type Cz material with screen-printed front contacts. To use realistic input parameters, a 21% n-type PERT cell was fabricated on Cz wafer (5 Ω-cm, 1.5-ms lifetime). Modeling showed that the cell efficiency will improve to only 21.6% if the back of this cell is replaced by the above TOPCon, and the performance is limited by the homogenous emitter. Efficiency was then modeled to improve to 22.6% with the implementation of selective emitter (150/20 Ω/sq). Finally, it is shown that screen printing of 40-µm-wide lines and improved bulk material (10 Ω-cm, 3-ms lifetime) can raise the single side TOPCon Cz cell efficiency to 23.2%. Copyright © 2016 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]

[Display omitted] • Dissolution of poly-Si in H 3 PO 4 consists of unstable suboxide formation and its dissolution. • Epoxy and vinyl group additives in H 3 PO 4 passivate poly-Si surface. • Epoxy and vinyl group additives suppress dissolution of poly-Si in H 3 PO 4. • Additives with Si–O bond as well as epoxy or vinyl group in H 3 PO 4 selectively remove Si 3 N 4 layers at multi-stacked Si 3 N 4 /SiO 2. This work investigates the mechanism of polycrystalline silicon (poly-Si) dissolution in H 3 PO 4. The etching rate of poly-Si was more rapid than that of silicon dioxide (SiO 2) in H 3 PO 4 solution, because poly-Si surface possesses unstable Si1+, Si2+, and Si3+ states – rather than Si4+, which is more stable. Additives such as epichlorohydrin, 1,2-epoxy-3-phenoxypropane, vinyl bromide, and phenyl vinyl ether with epoxy or vinyl groups were introduced into the H 3 PO 4 to passivate the poly-Si surface. This significantly increased the presence of the Si4+ state and provided hydrophobic functional groups on the poly-Si surface to reduce the wettability of the poly-Si surface. The introduction of these additives significantly reduced the etching rate of poly-Si. 3-glycidyloxypropyl trimethoxysilane, 3-glycidyloxypropyl dimethoxymethylsilane, allyltrimethoxysilane, and vinyltrimethoxysilane with Si–O bonds, as well as epoxy or vinyl groups in their molecular structures, were demonstrated to suppress the etching rate of both SiO 2 and poly-Si. The introduction of these additives to H 3 PO 4 promoted the selective removal of silicon nitride (Si 3 N 4) layers from multi-layered Si 3 N 4 /SiO 2 trench structures without the loss of either poly-Si or SiO 2. [ABSTRACT FROM AUTHOR]

In this paper, the Pi-gate (PG) poly-Si junctionless (JL) and inversion mode (IM) FETs with a high aspect ratio (A.R. = channel thickness/channel width ~ 3.4) have been successfully fabricated and demonstrated by a method without using the costly lithography technique. This method has some advantages: 1) the thickness of channels can be controlled simply by thickness of poly-Si layer; 2) the shape of channels can be controlled effectively by rectangular silicon nitride (Si3N4) as hard masks; 3) the series resistance can be reduced by raised source/drain configurations; and 4) Si-compatible low thermal budget process. The PG poly-Si JL FETs show excellent electrical performance in terms of low gate overdrive voltage ( VG – V\mathrm{ TH} = 2 V), extremely near-ideal subthreshold swing (S.S.) ~68 mV/decade, steep average subthreshold swing (A.S.S.) ~ 73 mV/decade, smaller drain-induced barrier lowering ~9 mV/V, a higher ON/OFF current ratio \sim 1.1 \times 10^8 ( \textV\mathbf {D} = 1 V), and a better field-effect mobility ( \mu \mathrm{ FE}) \sim 35 (cm2/Vs) as compared with PG poly-Si IM FETs. Thus, these devices are very promising for future 3-D integrated circuits applications. [ABSTRACT FROM AUTHOR]

A successful development of high-performance multilevel microdevices is attributed to the outstanding physical properties of a polycrystalline silicon (poly-Si) film which can be tailored by its process conditions. Here, we select deposition temperature and post-deposition annealing treatment as critical process parameters, followed by investigating their effects on both structure properties and chemical-mechanical planarization (CMP) manufacturability of a poly-Si film. Experimental samples are prepared through low-pressure chemical vapor deposition (LPCVD) poly-Si deposition at different temperatures of 545–625 °C and thermal annealing treatment at 1050 °C under nitrogen atmosphere. At first, the poly-Si sample is inspected to characterize changes in macroscopic structure properties caused by the critical process parameters, together with changes in its surface morphology and grain boundary density. Next, the sample is polished to quantify changes in poly-Si CMP manufacturability such as material removal rate (MRR) and surface roughness. A relation between changes in microscopic features and changes in macroscopic properties is also discussed in depth. A poly-Si film deposited at 625 °C and then thermally annealed at 1050 °C shows significant improvement in both structure and CMP manufacturing aspects. The findings of this paper can potentially have a significant impact on developing poly-Si-based multilevel microdevices. [ABSTRACT FROM AUTHOR]

Although photovoltaics have been established as the dominant technology considering the field of solar energy conversion systems, issues regarding their relatively low efficiency still remain practically unsolved. Very recently, the possibility of combining photovoltaic (PV) cells and thermoelectric generators (TEGs) in hybrid systems, as a means of improving the overall conversion efficiency, has attracted particular attention. In this paper, the performance of a tandem PV–TEG hybrid, employing poly-Si as well as dye-sensitized solar cells, has been examined experimentally. Thermoelectric devices of different thermoelement geometry have been tested in order to identify the corresponding performance effect. In addition, the outcomes of the experimental process have been exploited in order to evaluate the performance of the system under real operating conditions. The analysis conducted indicates that the utilization of TEGs with shorter thermoelements results in enhanced power output levels, when conditions of actual operation are considered. Moreover, although improved power output is obtained by the setup employing the polycrystalline cell, dye-sensitized technology could become particularly attractive when the incorporation of solar cells in PV–TEG hybrids operating under conditions of elevated temperature is examined. [ABSTRACT FROM AUTHOR]

We developed partial laser anneal silicon (PLAS) thin-film transistor (TFT) of novel low-temperature polycrystalline-silicon (LTPS) technology, which had the mobility of 28.1 cm2/Vs lager than that of mass produced oxide TFT and photo-stability comparable with that of LTPS TFT in bottom gate structure. This innovative technology enables the conversion from an α-Si TFT to a high-mobility TFT most easily and inexpensively. Moreover, there is no limit of substrate size, such as Gen10 and more. Photo-stability of PLAS will be suitable to organic light-emitting diode backplane, high-dynamic range TV, and outdoor IDP. [ABSTRACT FROM AUTHOR]

We report high performance p-type poly-Si thin-film transistors (TFTs) achieved by lateral grain growth of amorphous silicon (a-Si) by using a continuous-wave blue diode laser of wavelength 445 nm. The blue laser beam is efficiently absorbed into the a-Si film, such that full melting and lateral crystallization is achieved in all thicknesses investigated, 50–200 nm. TFTs fabricated with 75-, 100-, and 125-nm-thick poly-Si films laterally grown by the blue laser annealing exhibited field-effect mobility of 108 ± 7, 104 ± 9, and 134 ± 12 cm2/ \textrm V\cdot \textrm s , and subthreshold swing of 210±51, 191±16, and 193±53 mV/decade, respectively, and high ON/OFF current ratio of \sim 10^8 . [ABSTRACT FROM PUBLISHER]

In this paper, we report the development of a high- k /metal gate stacking process to reduce the effective gate resistance, and circuit level validation results in 28-nm gate first integrated high- k /metal gate CMOS devices. To achieve this, millisecond annealing was adopted and the silicon (Si) gate and TiN gate electrode thicknesses were controlled. The recrystallized poly-Si gate by millisecond annealing improved the performance of the ring oscillator (RO) by 15% and the minimum operating voltage ( V\min ) of the high-frequency test pattern (HFTP) by 34 mV. The poly-Si gate improved the uniformity of the boron concentration and suppressed localized low doping area at the bottom of the gate. When the Si gate thickness was reduced by 10 Å with respect to the reference (POR) value, the performance of the RO improved by 5% and V\min of HFTP improved by 20 mV due to the shorter boron diffusion distance. A 10- Å thicker TiN gate electrode improved V\min of HFTP by 30 mV, since the thicker TiN reduced the TiN/Si gate interface resistance. [ABSTRACT FROM AUTHOR]

Passivating contacts based on polycrystalline silicon on an interfacial oxide (poly-Si/SiO x) require a fine-tuned in-diffused dopant profile at the surface of the crystalline silicon wafer. In particular, a strong dopant in-diffusion causes excessive recombination. This study contributes to reveal the yet unclear mechanism of this degradation of passivation. Boron in-diffusion from co-sputtered (p) poly-Si layers through the interfacial oxide is investigated for several layer thicknesses and plateau temperatures during the solid phase crystallization. It is shown that for higher temperatures and unexpectedly also for thicker layers the observed recombination current density increases up to a total loss of passivation, accompanied by a physical interfacial oxide disruption, which is not observed for intrinsic reference layers. This behavior is supported by simple numerical calculations. The recombination current densities are transferred into the actual surface recombination velocity which in turn reveals an exponential increase towards higher boron concentrations at the interface between the oxide and the crystalline Si base. It is concluded that rather dopant penetration of the interfacial oxide is responsible for the degradation of passivation than the actual boron concentration at the interface itself as reported before in literature. • Co-sputtered (p) poly-Si/SiO x passivating contacts degrade towards thicker poly-Si and higher annealing temperatures. • The identified degradation mechanism is a physical disruption of the interfacial oxide. • The degradation is rather driven by boron penetration than by the actual boron concentration at the interface. • Modelling of the actual surface recombination velocity reveals an exponential relation to the interface boron concentration. [ABSTRACT FROM AUTHOR]

A HfO 2 /SiON/SiN (HON) bandgap-engineered trapping layer (BETL) on inversion-mode (IM) and junctionless (JL) polycrystalline-Si flash memory devices is investigated in this work. The HON layer is formed by performing a rapid thermal oxidation process between the depositions of SiN and HfO 2 . For IM device, the programming speed, retention and endurance characteristics are improved by the HON BETL while without degrading its erasing speed when compared to that with HfO 2 /SiN (HN) BETL. As to the JL device, improved erasing speed and retention characteristics are obtained with HON BETL; high programming speed and good endurance performances of the JL device are also observed. HON BETL is promising to improve retention characteristics of poly-Si flash memory devices since the conduction band level of SiON is higher and the trap density of SiON is lower as compared to those of SiN. [ABSTRACT FROM AUTHOR]

The microstructural properties of polycrystalline silicon films obtained by either solid-phase crystallisation (SPC) or laser-induced liquid-phase crystallisation (LPC) were investigated by transmission electron microscopy (TEM). In SPC films, the most common intra-grain defects are dislocations with the density as high as 1E10 cm −2 determined from cross-sectional weak-beam dark-field images. The highest dislocation density in LPC film is at least two orders of magnitude lower than the SPC film, 1E8 cm −2 and typically it is below 1E6 cm −2 . The most common defect type in LPC films is twin boundaries and other junctions of different coincidence site lattice (CSL) boundaries. Such differences in the material structural properties result in far superior electrical performance of solar cells made of LPC films, such as mobility up to 400 cm 2 V −1 s −1 , similar to c-Si wafers, and the higher open-circuit voltage up to 585 mV. [ABSTRACT FROM AUTHOR]