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We have developed a scalable gate-last process to fabricate self-aligned InGaAs FinFETs that relies on extensive use of dry etch. The process involves F-based dry etching of refractory metal ohmic contacts that are formed early in the process. The fins are etched in a novel inductive coupled plasma process using BCl[subscript 3]/SiCl[subscript 4]/Ar. High aspect ratio fins with smooth sidewalls are obtained. To further improve the quality of the sidewalls and shrink the fin width, digital etch is used. Through this process flow, we have demonstrated FinFETs with L[subscript g] = 20 nm and fin width as narrow as 7 nm with high yield. Good electrostatic characteristics are obtained in a wide range of device dimensions. In devices with 7 nm fin width, record channel aspect ratio, and transconductance per unit footprint are obtained., United States. Defense Threat Reduction Agency (Grant HDTRA1-14-1-0057), National Science Foundation (U.S.) (Grant E3S-STC-0939514)

We demonstrate ultralow ohmic contact resistance to antimonide-based, p-channel quantum-well field-effect transistor (QW-FET) structures using a new p[superscript ±]-InAs/InAsSb cap structure. The incorporation of a p[superscript ±]-InAsSb layer enables the use of a thicker cap with lower sheet resistance, resulting in an improved contact resistivity. Using a Pd-based ohmic scheme, the composite cap structure resulted in a 4x reduction in contact resistance compared with a standard p[superscript ±]-InAs cap. This translates into nearly 3x improvement in the gm of fabricated InGaSb p-channel QW-FETs. Furthermore, Ni contacts on the composite cap were fabricated and a contact resistance of 45 Ω · μm was obtained. An accurate contact resistivity extraction in this very low range is possible through nanotransmission line models with sub-100 nm contacts. In devices of this kind with Ni-based contacts, we derive an ultralow contact resistivity of 5.2 · 10[superscript -8] Ω · cm[superscript 2]., Samsung (Firm), Intel Corporation

High electron affinity transition-metal oxides (TMOs) have gained a central role in two-dimensional (2D) electronics by enabling unprecedented surface charge doping efficiency in numerous exotic 2D solid-state semiconductors. Among them, diamond-based 2D electronics are entering a new era by using TMOs as surface acceptors instead of previous molecular-like unstable acceptors. Similarly, surface-doped diamond with TMOs has recently yielded record sheet hole concentrations (2 × 1014 cm−2) and launched the quest for its implementation in microelectronic devices. Regrettably, field-effect transistor operation based on this surface doping has been so far disappointing due to fundamental material obstacles such as (i) carrier scattering induced by nonhomogeneous morphology of TMO surface acceptor layer, (ii) stoichiometry changes caused by typical transistor fabrication process, and (iii) carrier transport loss due to electronic band energy misalignment. This work proposes and demonstrates a general strategy that synergistically surmounts these three barriers by developing an atomic layer deposition of a hydrogenated MoO3 layer as a novel efficient surface charge acceptor for transistors. It shows high surface uniformity, enhanced immunity to harsh fabrication conditions, and benefits from tunable electronic gap states for improving carrier transfer at interfaces. These breakthroughs permit crucial integration of TMO surface doping into transistor fabrication flows and allow outperforming electronic devices to be reached.

A p-type Diamond:H/WO 3 metal-oxide-semiconductor field-effect transistor (MOSFET) based on surface transfer doping is demonstrated. Using a low-temperature ALD-grown HfO 2 as gate insulator, the Diamond:H/WO 3 MOSFETs show excellent output characteristics, gate-controllable 2-D hole gas, and low gate leakage current. Long-channel FETs exhibit improved subthreshold behavior but reduced transconductance with respect to short-channel devices. An observed WO 3 -thickness-dependent threshold voltage is consistent with enhanced surface transfer doping as the WO 3 layer is thinned down. Low-temperature measurements suggest a significantly lower mobility than expected in this material system. This illustrates the challenge of maintaining high TMO quality during device fabrication.

We demonstrate for the first time InGaAs/InAs heterojunction single nanowire (NW) vertical tunnel FETs fabricated by a top-down approach. Using a novel III-V dry etch process and gate-source isolation method, we have fabricated 50 nm diameter NW TFETs with a channel length of 60 nm and EOT=1.2 nm. Thanks to the insertion of an InAs notch, high source doping, high-aspect ratio nanowire geometry and scaled gate oxide, an average subthreshold swing (S) of 79 mV/dec at V[subscript ds]= 0.3 V is obtained over 2 decades of current. On the same device, I[subscript on]= 0.27 μA/μm is extracted at V[subscript dd]= 0.3 V with a fixed I[subscript off]= 100 pA/μm. This is the highest ON current demonstrated at this OFF current level in NW TFETs containing III-V materials., National Science Foundation (U.S.). Center for Energy Efficient Electronics Science (Award 0939514)

We have investigated the stability of the gate stack of GaN n-MOSFETs under positive gate stress. Devices with a gate dielectric that consists of pure SiO[subscript 2] or a composite SiO[subscript 2]/Al[subscript 2]O[subscript 3] bilayer were studied. Our research has targeted the evolution of threshold voltage (V[subscript T]), subthreshold swing (S) and transconductance (g[subscript m]) after positive gate voltage stress of different duration at different voltages and temperatures. We have also examined the recovery process after the stress is removed. We have observed positive V[subscript T] shift (ΔV[subscript T]) in both gate dielectrics under positive gate stress. In devices with a SiO[subscript 2] gate oxide, we have found that ΔV[subscript T] is caused by a combination of electron trapping in pre-existing oxide traps and interface trap generation. In devices with a composite SiO[subscript 2]/Al[subscript 2]O[subscript 3] gate oxide, on the other hand, ΔV[subscript T] is due to electron trapping in pre-existing oxide traps and generation of near interface oxide traps.