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This paper reports the development of a highly-sensitive and ultra-thin silicon stress sensor chip (UTSC) and its applications for wearable sensors. Stress sensor chips are fabricated using CMOS technology, and after dicing the individual chips are reconfigured into a virtual wafer on a carrier wafer using temporary adhesive bonding. The reconfigured wafer is then thinned using mechanical grinding, polishing, and wet etching. After thinning, the sensor chips with thickness of 35 μm are laminated to a thin Kapton PI film, followed by de-bonding to separate the carrier wafer. Measurement results show that the UTSC is able to comply with curved surfaces, and the sensitivity is around 70 times that of metal strain gauge. The specifications of the UTSC are characterized in terms of linearity, repeatability, hysteresis, and zero drift. The UTSCs are demonstrated to measure human pulses on wrist and orthodontic forces of invisible aligners for dental treatment. The preliminary results show that the reconfigured method is applicable to thinning individual chips, and the UTSCs are flexible and sensitive enough for measurement of stress and strain on curved surfaces on human bodies.

This paper reports a readout integrated circuit with embedded data compression function for image sensors. Data compression is realized by adding a comparator in a two-step incremental sigma-delta analog-to-digital converter (ADC) with a fully floating double sampling integrator. The output difference between two adjacent pixels is compared with a predefined threshold using the comparator to detect redundant pixels. Once the difference is smaller than the threshold, indicating a redundant pixel, the AD conversion is omitted and the redundant information is stored using a Boolean variable. Thus, the conversion speed can be improved and the storage space is saved. An ADC test vehicle with an \(8 \times 8\) array has been fabricated using 0.5-\(\mu \) m CMOS technology. Measurement results show that the frame rate of the image sensor is 10%-236% faster than conventional ADC, and data compression ratios between 1 and 5 are achieved for images with different redundancy. The advantages of this on-chip image compression are the embedded and simple circuits, considerable speed and storage space improvement, and low power consumption. The preliminary results have demonstrated the feasibility and the effectiveness of the proposed compression method.

Pattern transfer on structured surfaces is still a technical challenge in MEMS fabrication due to the accumulation of photoresist at the structure base and the discontinuity at the structure opening. This paper reports a planarization method which employs a two-step polymer spin-coating to cap the structures to facilitate pattern transfer on structured surfaces. The first spin-coating uses heat-depolymerizable poly (propylene carbonate) (PPC) to either partially fill or completely intersect the structures, and the following spin-coating uses polyimide (PI) to form a complete capping film on the structured surfaces. The thermal decomposable feature of PPC allows it to decompose as a sacrificial layer during PI curing, leaving only PI films on the structured surfaces after the two-step coating. High topography surfaces with deep holes with diameter of 25 μm, long trenches with length of 500 μm, and large cavities with width of 100 μm, have been well planarized using the proposed method. Subsequent photolithography verifies that photoresist can be well applied onto the planarized surfaces, and the pattern transfer results are satisfactory. Silicon dioxide deposited using plasma enhanced chemical vapor deposition (PECVD) and aluminum deposited using sputtering are also demonstrated on planarized surfaces. The preliminary results demonstrate the feasibility of planarization of high topography surfaces using the two-step coating method.

Cell-substrate interaction is important in tissue engineering. Vascular smooth muscle cells (VSMCs) cultured on the microgrooved surface of poly(3-hydroxybutyrate-co-3-hydroxyhexanoate) (PHBHHx) showed a distinctive polarized morphology and a high expression level of let-7a compared with the flat substrates. LIMK2, a crucial regulator of actin dynamics, was identified as a new target of let-7a. F-Actin content on flat substrates was significantly higher than that on microgrooved ones. Either overexpression of let-7a on flat substrates or inhibited expression on microgrooved substrates can rescue the difference. In accord with actin dynamics, the expressions of contractile smooth muscle markers, such as SM22 and SMA, decreased in VSMCs cultured on microgrooved substrates compared to those on flat ones, though PHBHHx can induce the synthetic-to-contractile phenotype shift. These results indicate that microgrooved PHBHHx could enhance actin dynamics of VSMCs through let-7a-involved regulation and trigger a synthetic shift.

Due to the flowability of benzocyclobutene (BCB) and the unavoidable shear components of the bonding force applied by bonding facilities, it is quite challenging to achieve void-free BCB adhesive bonding with simultaneous high post-bonding alignment accuracy. To solve this problem, this paper reports a compensation method for alignment errors to achieve simultaneous void-free and accurate wafer bonding using soft-baked BCB. By characterizing the wafer shift induced bonding force, it is found that the wafer shift is a systematic error associate with the bonders but independent of the wafers. Upon this investigation, a compensation method presetting a pre-bonding alignment shift opposite to the post-bonding shift is proposed to compensate the bonding induced wafer shift. Using this method, void-free bonding with soft-baked BCB has been achieved, and the alignment errors are improved significantly from around 35---40 μm to around 3 μm. Test results show that the average bonding strength of soft-baked BCB is about 26.4 % higher than that of partially-cured BCB. The preliminary results demonstrate the efficacy of the proposed compensation method, which has potential to improve the alignment accuracy of BCB bonding for three-dimensional integration, MEMS, and microsensors.

Open microfluidics is an emerging field of bio/medical applications that need direct energy/matter exchange between microfluids and environment. This paper presents the design, simulation, fabrication, and test of a microfluidic chip for a water-in-oil (WiO) two-phase flow in closed-open-closed microchannels. The chip, fabricated from PDMS using soft lithography, consists of a flow-focusing structure for WiO droplet generation and a long closed-open-closed channel for droplet flow. A negative pressure applied to the end of the channel is used as the driving force for WiO droplets to flow through the open channel. It is found that the negative pressure that is capable of driving a steady flow for a given flow rate, without overflow and air suction, falls into a pressure range instead of being an exact value. The mechanism for the pressure range is investigated theoretically and experimentally and is attributed to the surface tension. Yeast cells have been incorporated in the droplets, and the successful flow through the open channels verifies the function of the chips.

This paper reports the development of a hot embossing method for fabricating chalcogenide microlens arrays using soft polydimethylsiloxane (PDMS) stamps. The stamps are formed by molding PDMS on photoresist masters fabricated with sphere segments by thermal reflow. Upon proper temperatures, the chalcogenide glass softens and is embossed using PDMS stamps with low pressure. Void defects at the center and at the side of microlenses are found, and the mechanisms for the void formation are investigated and verified. The hot embossing parameters including pressure, temperature, embossing time, and the thicknesses of the PDMS stamps are optimized. A 400 × 400 microlens array with uniform profiles, smooth surface roughness, and good roundness have been successfully fabricated on both chalcogenide thin films and bulk wafers. The preliminary results demonstrate the feasibility of using hot embossing with soft PDMS stamps as a simple and low cost method to fabricate chalcogenide microlens arrays.

Using air-gaps to replace conventional silicon dioxide as the insulators of through-silicon-vias (TSVs) has the possibility to improve the electrical performance and some thermal reliability issues of TSVs. This paper reports the implementation of TSVs with air-gap insulators by developing a polymer sacrificial technology. The sacrificial technology and the key fabrication processes are investigated in detail, including spin-coating of poly propylene carbonate (PPC) on the sidewalls of blind vias, copper chemical-mechanical polishing, PPC grinding, and PPC pyrolysis to form air-gaps. To address the technical challenge in coating thin and conformal PPC sacrificial claddings in blind vias, a vacuum-assisted solvent refilling technique is developed. Air-gap TSVs are successfully fabricated and the electrical performances are characterized. The accumulation capacitance of the air-gap TSVs is 48 fF, and the leakage current is as low as 1.22 pA at bias voltage of 20 V. Finite element simulation shows that air-gaps are able to reduce thermal stresses. The preliminary results demonstrate the feasibility of the sacrificial technology and the good electrical performance of air-gap TSVs.

Low capacitance is critical to the electric performance of through-silicon-vias (TSVs). This paper reports the development of a low capacitance TSVs by replacing silicon dioxide insulation layers (liners) with benzocyclobutene (BCB) polymer. The BCB liner TSVs are fabricated by etching deep annular trenches on substrates, void-free filling the trenches with BCB polymer, selective etching the silicon post in the annular trenches, and filling the via with copper. Key fabrication processes including void-free BCB polymer filling in deep trenches, BCB chemical mechanical planarization, and selective etching of silicon post to BCB are developed. TSVs with BCB liners are successfully fabricated and the electrical performance is measured. The measurement results show that the capacitance of the BCB liner TSVs is around 42 fF, and the leakage currents to substrates and to neighboring TSVs are 2.2 pA and 1.1 pA at 10 V voltage, respectively. These preliminary results demonstrate the feasibility of the proposed fabrication technology and the efficacy of BCB liners in reducing TSV capacitance.

A laser-assisted chemical vapor deposition (LCVD) method has been developed for in situ synthesis of carbon nanotube (CNT) films on suspended microstructures. Focused laser beams are used to heat locally the suspended microstructures with low thermal mass and low thermal dissipation to high temperatures for localized CNT growth. Other substrate areas than the microstructures remain at low temperatures, preventing the devices on the substrate from being destroyed by high temperatures. The synthesizing parameters and the influences on CNT morphology and structures are systematically investigated and optimized, and solutions for uniform temperature distribution are proposed. Upon optimization, uniform, localized, and rapid growth of CNT synthesis has been achieved on suspended microstructures, and aligned CNTs with length and uniformity comparable to conventional hot-wall CVD have been successfully obtained. The experimental results show LCVD is a promising technology for in situ and localized synthesis of CNT films on suspended microstructures for CNT-CMOS (complementary metal oxide semiconductor) integration.

Low capacitance is critical to the electric performance of through-silicon vias (TSVs). This paper reports the development and electrical characterization of ultralow-capacitance TSVs which use air gaps to replace the conventional silicon dioxide as the insulation layers. The air-gap TSVs are successfully fabricated by developing a sacrificial technology which uses void-free filling and selective etching of an annular benzocyclobutene polymer cladding that surrounds copper plugs. The capacitance and the leakage current are tested to characterize the electrical performance. The lowest effective dielectric constant of the air enables the capacitance of the air-gap TSVs to be as low as 24 fF, and the capacitance density is more than one order of magnitude lower than that of conventional SiO2 liner TSVs. The leakage current to the substrate is 3 ×10-13 A at 40 V, and no leakage current degradation occurs after a 40-cycle thermal shock test. The preliminary results demonstrate the new air-gap structure and the efficacy of air gaps in reducing TSV capacitance.

Polymer insulation layers (liners) have several potential advantages in terms of capacitance and reliability over conventional silicon dioxide for through-silicon-via (TSV) applications. This paper reports the development and measurement results of a TSV using poly (propylene carbonate) (PPC) polymer as the insulation layers. To address the challenge in coating thin and uniform PPC liners on the sidewalls of high aspect-ratio vias, a spin-on technique using vacuum treatment and solvent refill is developed to prevent formation of air bubbles in the vias, and using this technique circular vias with aspect-ratio as high as 9:1 have been coated with uniform PPC layers. Based on these results, TSVs with thick PPC polymer liners have been fabricated and the capacitance and the current leakage are measured. Thanks to the relatively large thickness and the low dielectric constant of PPC liners, the TSV capacitance density is about 2.45nF/cm^2 and the leakage current is around 40nA/cm^2 at 5V voltage, indicating that replacing silicon dioxide with PPC as liners considerably reduces TSV capacitance. The preliminary results demonstrate the feasibility of fabrication of high aspect ratio and low capacitance TSVs with polymer liners.

Detection of trace explosives is still a challenging task because of the extremely low vapor concentrations. This paper reports a new microcalorimeter for detection of trace explosives with low detection limit and fast detection rate. The microcalorimeter consists of a suspended micromembrane with integrated heaters and thermistors and a carbon nanotube (CNT) interface layer in-situ synthesized on the membrane surface. Due to the large surface areas, the CNT interface layer improves adsorption to target chemical molecules. By operating the microcalorimeter in differential scanning calorimetry mode and differential thermal analysis mode, trace chemical detection is achieved through heating the adsorbed chemicals to deflagration and measuring the induced thermal response features and the total heat. The microcalorimeter is verified by explosive detection, and an equivalent limit of detection of 2.6 pg has been achieved by extrapolating the measurement results. Theoretically, detection is distinguishable upon 10-s fast exposure to saturated explosive vapors. These preliminary results demonstrate the ability of the microcalorimeter in detection of trace energetic chemicals.

This paper reports a cell trapping and patterning method using dielectric-pattern-assisted negative dielectrophoresis (dnDEP) that can achieve high-density cell arrays and complicated cell patterns. The dnDEP device consists of two planar metal electrodes and a patterned dielectric layer sandwiched in-between. The dielectric patterns generate non-uniform electric fields when an ac voltage is applied on the two electrodes, and the interaction of polarizable cells and the non-uniform electric fields imposes negative DEP forces on the cells, pushing them to the patterns in the dielectric layer. Using this dnDEP device, human lymphoma cells were successfully patterned in high-density microwell arrays and stellate structures. Thanks to the three-dimensional configuration and the small distance between the electrodes, cell trapping and patterning can be implemented with a voltage of 10 V. This dnDEP device has the advantages of simple configuration, low actuating voltage, and the compatibility with high conductivity physiological media for cell culturing.

This paper reports a chemical sensor that consists of a suspended microcantilever and a carbon nanotube (CNT) network that is in situ synthesized on the microcantilever. The in situ synthesis achieves minimized thermal resistance of the interface between the CNTs and the microcantilever, which together with the low thermal mass and the high thermal conductivity allows the sensor to operate in microcalorimeter mode. By heating the CNT networks with an integrated heater, the explosive vapors adsorbed on the CNT surfaces are ignited to deflagration, which releases extra heat to deflect the microcantilever and thus changes the resistance of an integrated piezoresistor. This thermal-mechanical coupling transduction mechanism bridges the heat changes on the CNT networks and the mechanical deflection of the microcantilever. The large surface to volume ratio of CNTs enables fast adsorption of the chemical sensor to explosive vapors and improved equivalent limit of detection (LOD). An equivalent LOD of 2.4 pg is achieved for TNT detection, and run-to-run repeatability and device-to-device reproducibility are better than 4% and 10%. The preliminary results demonstrate the feasibility of development of sensitive CNT chemical sensors using in situ synthesized CNT networks and thermal-mechanical coupling transduction mechanism.

A technical challenge in fabrication of ultra-thin sensor chip (UTSC) is to keep chip integrity in debonding the ultra-thin chips from grinding facilities. This paper presents a new debonding method by utilizing a thermally decomposable polypropylene carbonate (PPC), as the temporary bonding adhesive. Because PPC can readily decompose at relatively low temperature, this method can maintain the chip integrity even the chips have a thickness of tens of microns. UTSCs with thickness of 30μm have been achieved using this method, and stress sensors have been developed to verify the performance of UTSC. The experimental results show that the proposed method is able to fabricate UTSC with good flexibility and characterizations, demonstrating the newly proposed method an enabling technology for fabrication of sensors for flexible and wearable applications.

In this paper, a novel manufacturing scheme based on heat-depolymerizable material and thermosetting material is proposed to achieve high performance through silicon vias (TSVs) with porous polymer insulation liners. In order to strengthen the mechanical reliability and guarantee the low capacitance and low thermal expansion stress of TSVs, we come up with the novel TSVs with porous polymer insulation liners. And we present a manufacturing scheme for the porous polymer insulation liners. The polymer adopted in the manufacturing scheme is the mixture polymer of heat-depolymerizable material Polyimide (PPC) and thermosetting material Polyimide (PI). To address the challenge in fabrication of porous polymer liners in high aspect-ratio TSVs, we have adopted a vacuum-assisted spin-coating technology for filling the mixture polymer (PPC&PI) in high aspect-ratio annular trenches. Finally, through initial pre-cure and eventual pyrolysis, the porous structure can be achieved.

We present a monolithic integration of multiple sensors that have various structures and different packages. The multi sensors include an electrical field sensor (EFS) and accelerometers in a vacuum package and pressure, humidity, temperature sensors with direct contact with environment. To conduct the electrical signals from the vacuum package, three-dimensional (3-D) integration is implemented with a silicon interposer with through-silicon-vias (TSVs). The configuration of the multi sensor system, the co-design and co-fabrication, and packaging schemes are presented.

Inertial measurement units (IMUs) are widely used in motion measurement. However, the drift of IMUs results in significant accumulated errors for long-term position and orientation measurement. This paper reports a method to compensate the drift of inertial sensors with the assist of ultrasonic sensors and magnetometers. The magnetometer is combined with a three-axis accelerometer as a digital compass for orientation determination in static state by measuring the gravity and the earth's magnetic field vectors. A three-axis gyroscope is used to measure the orientation in dynamic state to complement the digital compass. Displacement determination is implemented using the accelerometer through double integration, and an ultrasonic sensor is employed to periodically calibrate the accumulated errors of the accelerometer. The redundant data from the multi-sensors are fused using extended Kalman filter (EKF), in which the position measured by the ultrasonic sensor and the orientation measured by the digital compass are defined as the observation values, and the position, velocity, and orientation are included in the state vector. Experimental results show that the accumulated errors of inertial sensors are reduced by ultrasonic sensors and magnetometers, and EKF improves the accuracy of orientation and position measurements.

A silicon piezoresistive stress sensor is developed to measure the three components of the orthodontic forces of a tooth in invisible aligners. The stress sensor chip consists of multiple piezoresistor rosettes, and is fixed on the tooth surface to measure the orthodontic force induced stresses. An inverse problem algorithm is established to reconstruct the orthodontic forces of the tooth from the measured stresses. A key thinning process is developed using chemical-mechanical polishing to thin the sensor chip from 650 to 100 , such that it can be accommodated to the limited space between the aligner and the tooth, without much influence on the orthodontic force. The ultra-thin thickness enables the sensor chip to be compliance with tooth deformation, and improves the stress measurement sensitivity as much as 40 times, making it capable of measuring small orthodontic force. The sensor design, fabrication, orthodontic stress measurement, and force reconstruction are given in details, and the experimental results demonstrate the feasibility of using miniaturized and ultra-thin sensors to determine the in vitro orthodontic forces.

This paper reports a novel chip-to-wafer (C2W) three-dimensional (3D) integration approach using a template for precise alignment. The key unit process steps, including template fabrication, chip edge definition, C2W alignment and bonding, are investigated. To demonstrate this C2W approach, benzocyclobutene (BCB) and Cu are selected as the starting materials for template and bonding, respectively. Wafers with Cu daisy chains are fabricated for both the chip and host wafer. Individual chips are produced by a 2-step process: defining the chip edges and dicing. All individual chips are aligned to the host wafer with a BCB template, followed by a wafer-level Cu-Cu bonding process. An alignment accuracy of approximately [email protected] is achieved and a good Cu-Cu bond interface is observed with Cu grain-growth across the bonding interface. This C2W 3D integration approach has the potential for low cost and high throughput fabrication of multi-layer high-performance 3D systems.

A microbridge based calorimetric sensor is developed for the detection of trace energetic substances by measuring their characteristic temperature change in thermal reactions. The micro-calorimeter is mainly a suspending microbridge made of silicon dioxide (SiO2) and integrated with heating and detecting resistors. It is fabricated based on silicon-on-insulator (SOI) wafers using a front-side releasing method, which is simple, efficient and high-yielding. The tiny microbridge is with an extremely low dimension and achieves low thermal capacity, allows small temperature changes induced by chemical reactions detectable. A limit of detection of sub-100 pg is demonstrated for trinitrotoluene (TNT) by measuring the endothermic and exothermic reactions when heating the preconcentrated TNT to the deflagrating temperature, indicating the ability of the sensors in energetic chemical detection.

This paper presents the experimental and theoretical investigation of the thermal stress development in the C2W 3D integration with template alignment and the impact of fabrication parameters on the thermal stress. The experimental approach is accompanied with an optical profilometer, while the theoretical study is based on COMSOL FEM analysis. It is found that the thermal stress is primarily induced in the polymer hard curing process, and is accumulated within the cooling process due to the mismatch of coefficients of thermal expansion (CTE) with substrate. The thermal stress highly depends on the polymer thickness and the treatment temperature, and could be partially released by polymer etching. The measurement and simulation results indicate that the template alignment technology is compatible with semiconductor fabrication by optimizing the fabrication parameters. The feasibility of C2W 3D integration with template alignment is furthered demonstrated.

Thermal management is one of the critical challenges in three-dimensional (3D) integration. As the polymer bonding adhesive is the major source of the internal thermal resistance in 3D integration, this paper reports an approach to increase the thermal conductivity of the bonding adhesive benzocyclobutene (BCB) by loading carbon nanotubes (CNTs). By exploiting the aromatic property of BCB, an ultrasonication and mechanical stirring assisted non-covalent dispersion method is developed to disseminate CNTs with concentrations ranging from 0.25% to 2% to form BCB-CNT composites. The effects of ultrasonication and mechanical stirring on CNT dispersion are experimentally investigated, and the electrical properties, the thermal diffusivity, and the bonding strength of BCB-CNT composites are characterized. The results show that ultrasonication in conjunction with mechanical stirring can significantly improves the CNT dispersion results, and an 80% improvement in the thermal conductivity is achieved for BCB by loading CNTs. The bonding strength of BCB-CNT composites, though varies with CNT concentrations, are improved compared with pure BCB for CNT concentrations less than 1.75%.

This paper reports a method for measuring the heat capacity of as-grown carbon nanotubes (CNTs) using a microcalorimeter. The microcalorimeter consists of a double-layer suspended silicon dioxide microstructure and two silicon resistors sandwiched in-between the silicon dioxide layers. CNTs for heat capacity measurement are locally synthesized on the surface of the microstructure using laser-assisted chemical vapor deposition. The CNTs and the microcalorimeter are heated to a high temperature with a silicon resistor, and the temperature of the microcalorimeter with CNTs is measured with using the other silicon resistor. The heat capacity of the CNTs is obtained by dividing the measured effective heating power by the rate of temperature increase. The suspended configuration and the low thermal conductivity of silicon dioxide achieve low thermal dissipation, which together with the minute thermal capacity enable significant temperature changes. Using this sensitive microcalorimeter, the heat capacity of as-grown CNTs, 6-14 nJ/K from 340 to 440 K, is measured in-situ without the need of CNT transfer and pretreatment, avoiding damage to the CNT samples. This microcalorimeter is also applicable to in-situ measurement of structure-related thermal properties of porous materials.

Thermal management is one of the critical challenges in 3-D integration. The intermediate bonding interfaces between two chips, such as silicon dioxide and polymer adhesives, are the major source of internal thermal resistance in 3-D integrated circuits, leading to thermal issues such as high temperature spots and larger temperature gradients. This paper reports an approach to reduce the thermal resistance of a common bonding adhesive benzocyclobutene (BCB) by loading carbon nanotubes (CNTs) to improve the thermal conductivity. By exploiting the aromatic property of BCB, an ultrasonication-assisted noncovalent dispersion method is developed to disseminate CNTs with different concentrations into BCB. Thanks to the high thermal conduction ability of CNTs, the thermal conductivity of BCB is improved as much as 20% by loading 1.5 wt% CNTs. The surface temperature of bonded chips during heating are measured to evaluate the dynamic heat transfer ability, and a 13% improvement is achieved for BCB-CNT composites. The bonding strength of pure BCB and BCB-CNT composites are tested and the results show that CNTs is beneficial to improving the bonding strength.

Because of the pinch-off effect, filling high aspect- ratio, void- and seam-free through-silicon-vias (TSVs) using damascene copper electroplating is one of the technical challenges in realizing 3-D integration and packaging. This paper presents simulation investigation and experimental verification of bottom-up copper electroplating (BCE) to verify its capability in fabricating high aspect-ratio void-free TSVs. Theoretical models for blind- and through-via copper electroplating are derived, and a generic solving method is developed by employing a moving boundary simulation to address the challenge of time-dependent process. The time-resolved evolution of electroplating profiles is simulated after the ion concentration distribution and the electric current density are obtained. The simulation results predict the behaviors of copper electroplating of blind- and through-vias, and reveal the mechanism of void formation. By employing a transfer wafer to provide seed layers, improved BCE is developed and high aspect-ratio void-free TSVs are successfully fabricated. The experimental results verify the theoretical model and the moving boundary simulation method, and prove the capability of BCE in filling high aspect-ratio TSVs.

In this paper, a Wafer Level Packaging (WLP) compatible pressure sensor system enabled with Through Silicon Via (TSV) and Au-Sn inter-chip micro-bump bonding is designed and fabricated in lab, in which TSV transmits electrical signal from piezoresistive circuit to processing circuit vertically. The pressure sensor system includes TSV integrated piezoresistive pressure sensor chip and Read-Out Integrated Chip (ROIC) in which TSV also incorporated. Two CMOS compatible fabrication process flows for pressure sensor system are demonstrated. And, flip chip bonding structure of TSV integrated pressure sensor with a ROIC are realized using one of these two process flows. Inter-chip interconnects enabled with TSV and micro-bump bonding is obtained.

We report here the use of nanomolding in capillaries (NAMIC) coupled with dithiocarbamate (DTC) chemistry to fabricate sub-50 nm quasi-1D arrays of 3.5 nm core gold nanoparticles (Au NPs) over large areas. Owing to chemical immobilization via the DTC bond, the patterned NP systems are stable in water and organic solvents, thus allowing the surface modification of the patterned Au NP arrays through thiol chemistry and further orthogonal binding of proteins. The electrical properties of these patterned Au NP wires have also been studied. Our results show that NAMIC combined with surface chemistry is a simple but powerful tool to create metal NP arrays that can potentially be applied to fabricate nanoelectronic or biosensing devices.

This paper reports the reactive ion etching (RIE) characteristics of benzocyclobutene (BCB) in sulfur hexafluoride/oxygen (SF"6/O"2) plasmas. The dependence of etching rate and etch anisotropy on the processing parameters, including RF power, chamber pressure, and SF"6 concentration, are investigated comprehensively ranging from 50 to 200W, 22.5 to 270mTorr, and 0% to 80%, respectively. The BCB etching rate increases with chamber pressure and RF power in spite of nonlinearity, but decreases with the increase in SF"6 concentration. Anisotropic etching can be achieved using low chamber pressure, large RF power, and high SF"6 concentration. To avoid grass-like residue that happens at low pressure and large power fluorine-poor conditions, processing parameters with respect to residue-free etching are recommended. The etching mechanisms of the dependence of the etching characteristics on the processing parameters are discussed. Optimal processing parameters are presented as a guideline for isotropic etching of BCB as sacrificial layers to release structures and for anisotropic etching of BCB to precisely control etching dimensions and profiles.

This paper presents a new method for detecting trimethylamine (TMA) in gas and liquid phases using a piezoresistive microcantilever sensor functionalized with a self-assembled monolayer (SAM). The microcantilever consists of two silicon dioxide layers and a single crystalline silicon piezoresistor in-between. This configuration allows microcantilevers to achieve high sensitivity because of the low stiffness of silicon dioxide and the high piezoresistive coefficients of single crystalline silicon. The surface of the microcantilever is chemically functionalized with a self-assembled monolayer of 11-mercaptoundecanoic acid (11-MUA) via Au–SH covalent bonding on a gold film deposited on the microcantilever. The 11-MUA SAM adsorbs TMA through hydrogen bonding between the SAM and TMA molecules, and the microcantilever is deflected by the changes in the surface stress as a result of the hydrogen bonding based chemisorption. Experimental results show that the deflection of the microcantilever depends on the concentration of TMA, and the minimum detection limits of 10 mg/L for liquid TMA and 1.65 μg/L for gas TMA are achieved. The selectivity of TMA with respect to ethanol, acetone, and butanone is also investigated.

Three-dimensional (3D) integration, which employs through-silicon-vias (TSVs) to electrically interconnect multiple-stacked chips, is a promising technology for significant reduction in interconnect delay and for hetero-integration of different technologies. To fabricate void-free TSVs, this paper presents a copper electroplating technique with the assistance of ultrasonic agitation to fill blind-vias, and discusses the influence of ultrasonic agitation on copper electroplating. Blind-vias with an aspect ratio of 3:1 are used for copper electroplating with both direct current (DC) and pulse-reverse current modes, combined with either ultrasonic agitation or mechanical agitation. Experimental results show that blind-vias with small aspect ratio can be completely filled using pulse-reverse current, regardless of the agitation methods. For DC, ultrasonic agitation is superior to mechanical agitation for copper electroplating in filling void-free vias. These results indicate that agitation, though is a secondary control factor to pulse-reverse current, can enhance mass transfer in blind-vias during copper electroplating and can improve the filling capability of copper electroplating.

Three-dimensional (3D) integration is emerging as an attractive technology to continue Moore's law through the integration of multi-stacked chips interconnected with through-silicon-vias (TSVs). To address the challenge in filling high aspect-ratio TSVs with copper, this paper reports an improved bottom-up copper electroplating (BCE) technique by introducing a glass transfer wafer, which is temporarily bonded with the device wafer to provide a copper seed layer. As the copper seed layer on the transfer wafer covers the through-holes, copper is electroplated from the bottom seed layer to the top opening of the through-holes without forming any voids or seams. This avoids the time consuming sealing process in conventional BCE, which normally takes 3-5h. Thanks to the mechanical support of the transfer wafer, the device wafer can be thinned to several tens of micrometers. Using this technique, TSVs with diameter of 5@mm and aspect-ratio of 13:1 have been achieved. Based on the improved BCE technique, a through-via type 3D integration strategy is developed.

This paper presents the fabrication and characterization of a curved-up piezoresistive microcantilever flow sensor. The microcantilever sensor, fabricated with silicon-on-insulator (SOI) wafers, consists of two layers of silicon dioxide and a silicon piezoresistor in-between. The difference in the residual stresses between silicon and silicon dioxide layers curves the microcantilever upwards and the free-end bends out of plane. The curved-up microcantilever transfers fluidic momentum that acts on it to drag force, which bends the curved-up microcantilever and changes the resistance of the piezoresistor. This configuration has the advantage of high sensitivity for low flow rate measurement and allows the microcantilever to be integrated in microchannels to measure steady flow. The flow sensor is calibrated with respect to low flow rates at range of 0–20 cm/s. The sensitivity, repeatability, and zero drift are characterized in detail.

This paper presents the development of a piezoresistive stress sensor fabricated on silicon-on-insulator (SOI) wafers for measurement of electronic packaging stress at high temperature. The sensor consists of a series of sensor elements and calibration elements. The sensor elements comprise a 0deg-90deg p-type piezoresistor pair and a plusmn45deg n-type piezoresistor pair for stress measurement, and the calibration elements comprise two polar three-piezoresistor rosettes with specific angels to calibrate the piezoresistive coefficients. The sensor and the calibration piezoresistors are etched from the SOI layer as separate ldquosilicon islandsrdquo on the dielectric buried oxide (BOX) layer. This configuration exploits the excellent electrical insulation of the BOX layer, and enables high-temperature operation of the stress sensor by eliminating the leakage current. Design, fabrication, and the calibration of the piezoresistors at high temperatures show the feasibility of the SOI high-temperature stress sensor. The piezoresistive coefficients are calibrated versus stress and temperature, and the nonlinearity of the resistance versus temperature and the calibration errors are discussed in detail.

A theoretical model for laminated piezoresistive microcantilevers with discontinuous layers is developed for surface stress sensitive biosensors. The microcantilever consists of two supporting layers of silicon dioxide and two silicon piezoresistor strips sandwiched in-between. To address the issue of discontinuity of the piezoresistive layer, the microcantilever is segmented and a closed-form equation is developed for each segment using classical laminated plate theory. A two-dimensional theoretical model for the discontinuous microcantilever is deduced by integrating all the segments and is validated using finite-element-method (FEM) simulation. The model allows the predication of the deflection and the sensitivity of piezoresistive microcantilever biosensors with discontinuous layers and surface stress. The effects of the dimension of the discontinuous piezoresistors on the performance of the microcantilevers are obtained using the segment model. Based on the model, guidelines for design and optimization of surface stress sensitive microcantilever biosensors are given.

This paper presents the design, fabrication, and characterization of a piezoresistive microcantilever sensor fabricated on silicon-on-insulator (SOI) wafers. The microcantilever consists of two silicon dioxide supporting layers and a single crystalline SOI layer in-between. The piezoresistors are implanted in the surface of the SOI layer to exploit its large piezoresistive coefficients. Laminated beam theory is employed to design the microcantilevers and the piezoresistors. A front-side releasing method is developed to suspend the microcantilevers by isotropically etching the substrate beneath the microcantilevers from the front-side of the wafers using SF6 plasma. The features of SOI wafers and the front-side releasing enable high uniformity and high yield for the fabrication of piezoresistive microcantilever sensors. The sensors are validated using specific binding reaction of antigen and antibody of immunoglobulin G on the sensor surface, and the experimental results show that they are promising for portable and integrated sensing applications.

Three-dimensional (3D) integration, which uses through-silicon-vias (TSVs) to interconnect multiple layers of active circuits, offers significant improvements over planar integrated circuits (ICs) on performance, functionality, and integration density. To address a key issue in 3D integration, the fabrication of high aspect ratio TSVs, this paper presents the bottom-up copper electroplating technique to fill high aspect ratio vias with copper. Deep through-silicon holes with aspect ratio as high as 10:1 are etched using deep reactive ion etching (DRIE) method, and are completely filled with copper using bottom-up copper electroplating technique without forming any voids or seams. Based on this technique, a multi-layer 3D integration method is proposed. This method uses temporary transfer wafer to provide mechanical support to the device wafer during wafer thinning process and to provide the seed layer for copper electroplating. Then bottom-up electroplating is performed to fill the high aspect ratio vias with copper. Experimental results verify the feasibility of the proposed method.

Measuring electric field has a very wide range of applications in the power system, but for the ion field under the HVDC transmission lines, the current measurements are insufficient. In this paper, effects of interventional measurement, theoretical analysis, measuring programs are researched. Sensors in a Poisson field sense an electric field Ein, which consists of three parts. E0 is the origin electric field, E1 indicates the field generated by charges attached on the sensor, E2 represents the influence of the redistribution of ion flow after the sensor is put into the field. Based on multi-physics simulation, this paper figures out the effects of sensor's intervention through analysing the movement of charged particles and found that when the charging process is completed, there is a spherical region around the sensor where the charge density is zero, which is called the “empty zone”. This paper figures out the relationship between inside field and outside field. The electric field directly measured by the sensor kernel module can be approximately regarded as the sum of the space field which we aim to measure and the self-generated electric field of the charge accumulated on the metal shell of sensor's shell. A structure of two-MEMS-device is promoted to deal with the effect of the ion flow, and it could applied in the ion field or nominal electric field without ion flow and ignore the angular offsets of placing, according to the simulations.

This paper presents the design, fabrication, and characterization of a piezoelectric micromachined ultrasonic transducer (pMUT) operating in d33 mode. A piezoelectric PZT thin film is polarized along the in-plane direction using top square interdigital electrodes (IDEs), and the in-plane polarization and IDEs enable the pMUT to operate in d33 mode, which allows the PZT to convert the ultrasonic pressure-induced in-plane stresses into in-plane direction charges. The square IDEs fully exploit the stresses of the diaphragm to improve sensitivity and increase device capacitance, and the pMUT is optimized by varying the IDE dimensions rather than the thickness of the PZT film. Theoretical and finite-element analyses are performed to optimize the diaphragm and the IDE dimensions in terms of resonance frequency and sensitivity, respectively. The ultrasonic directivity of the pMUTs with different packaging configurations is characterized, showing large ultrasound inlet areas beneficial to ultrasonic applications requiring high directivity.

In this paper, Pb(Zr0.53,Ti0.47)O3 films are deposited on titania by sol-gel method, and PZT films of ∼4 μm in thickness are successfully obtained by repeating multi-coating and annealing. Based on the think film deposition processing, a laminated Pt/Ti/PZT/TiO2/SiO2/Si structure is proposed, and the PZT films are in-plane polarized by top InterDigital Electrodes (IDE). The capacitance-voltage curves of the PZT thick films are measured in a range of −40 V to 40 V, and the symmetric butterfly shapes of the curves indicate good ferroelectric properties of the films. The capacitance is found dependent on the parameters of the electrode configuration, and a simple equation for predicting the IDE capacitance is deduced.

This paper reports an integrated silicon CMOS stress sensor chip. The sensor chip integrates a 16×16 CMOS stress sensor array with decoders, subtraction circuits, capacitive feedback trans-impedance amplifiers (CTIA), correlated double sampling circuits (CDS), rail-to-rail followers, and a low dropout regulator (LDO) in a monolithic chip. Each stress sensing cell in the array has a dimension of 55 μm × 55 μm to achieve high spatial resolution. Full integration of stress sensor array with signal processing circuits significantly suppresses circuit noises, enabling the sensor chip to achieve excellent performance. Measurement results on linearity, repeatability, zero drift and full-scale drift show that the overall error of the sensor chip is around 1.5% full-scale output.

In this paper, we design a new program to achieve carbon nanotubes through silicon vias (TSV) interconnects compatible with CMOS technology using an auxiliary TSV structures and laser local heating method. Auxiliary TSV structures are made by two wafers. One wafer is etched into ups and downs structures and then deposited SiN x and SiO 2 film. The other one is made into TSV structures by deep silicon etching, depositing thin film and wafer thinning and polish. Two wafers are bonded together by patterned BCB (Benzocyclobutene). For the entire device structures, we use FDTD solutions software to simulate infrared optical properties of SiN x . SiN x film layer can absorb 10.6 µm infrared laser strongly. Thermal simulation of geometrical model by COMSOL Multiphysics software shows well temperature compatibility. It turns out the program is compatible with current CMOS processes. Using a laser local heating method, we have studied the local growth of carbon nanotubes. Carbon nanotubes grown in TSVs are sparse, intertwined and have a poor morphology; the reason for this is that TSVs' geometric sizes limit gases flows. Carbon nanotubes interconnect still need further study.

This paper reports fabrication and characterization of TSVs that use combined air-gap/SiO 2 as the insulators. Fabrication technologies based on reactive ion etching (RIE) of benzocyclobutene (BCB) sacrificial layers have been developed to fabricate uniform and high aspect-ratio air-gaps, and air-gaps with thickness of 2 µm and aspect-ratio of 25∶1 have been successfully fabricated. The measured capacitance-voltage (C-V) and current-voltage (I–V) curves at room temperature and high temperatures show that the TSVs with air-gap/SiO 2 liners have low capacitance and leakage current. Compared with the TSVs using a sole air-gap insulator, the additional SiO 2 liners protects the TSV from being influenced by the residues of sacrificial materials, and the electrical performance and thermal stability are improved.

Preconcentration is an important technique that can significantly improve the limit of detection (LOD) of an analytical system by preconcentrating target analytes. In this paper, we have developed a microcalorimeter with an in-situ synthesized carbon nanotube (CNT) forest and a stand-alone metal preconcentrator for detection of trace energetic chemical vapors (ECV). Both the CNT forest and the metal preconcentrator provide high-efficiency preconcentration for target chemicals, and their preconcentration factors (PF) are 2.5 and 10, respectively. Experimental results show that a microcalorimeter with two-stage concentrators is able to achieve a lower LOD and a shorter detection time than conventional microcalorimeters.

This paper presents the design, modeling, and simulation of Lead Zirconate Titanate (PZT) based micro-sensors. The PZT thin film is polarized in-plane in stead of through-thickness, and thus utilizes d33 working mode other than d31 working mode. Micro-sensors using cantilever structures and InterDigital Electrodes (IDE) are numerically analyzed by Finite Element Analysis (FEA) method. The relation between the sensitivity and the IDE configurations is presented, and some results and conclusions can be used as future design guidelines. The simulation results show that the voltage sensitivity of micro-sensors utilizing d33 mode can be several times or even tens times higher than those utilizing conventional d31 mode. The high sensitivity together with the ease of fabrication makes micro-sensors using d33 mode more competitive and attractive.

Digital force/weight sensors have some advantages over their analog counterparts. This paper describes the optimization and implementation of a novel digital force/weight sensor that uses a thickness-shear quartz crystal resonator (QCR) and a unique compliant mechanism. The compliant mechanism consists of eight flexure hinges and is used to fix the sensitive QCR and transfer the measured force. Advantages of such a sensor include inherent digital output, high resolution, high reliability, and low cost. Due to the complex structure and the multivariables of the compliant mechanism, conventional trial methods are inefficient in determining the dimensions. To solve this problem, an optimization method has been developed by employing rigid-body model, finite element method, and nonlinear programming techniques. Experimental results show that it is more efficient than trial methods in optimizing complex compliant mechanism-based sensors. This method can be used as a generic method for optimizing force sensors using compliant mechanisms, to obtain the desired specifications.

Microcantilevers-based sensors (MCSs) are a new approach to detecting and measuring physical, chemical, and biological signals in the nano- to femto-range level. Piezoresistive readout systems for MCSs have the advantages of full integration, low cost, ease of use, and the capability of manipulating large arrays. This paper presents a design method for laminated piezoresistive MCSs to obtain optimal performance by optimizing the dimensions of the microcantilevers and the doping concentration of the piezoresistors. Laminated theory was employed to deduce the closed-form solutions to static stress and natural frequency. Expressions for predicting sensitivity and resolution were derived by combining stress distribution with power densities of 1/ f noise and Johnson noise. Finite element method (FEM) was performed to verify the theoretical results. The thickness of the laminated MCSs and the doping concentration were optimized by using static analyses and power densities of noise to generate the best sensitivity and resolution. A method based on non-linear programming is given to facilitate the solving process. These methods and some conclusions are also applicable to developing other types of piezoresistive sensors that use laminated structures.