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FinFETs and ultrathin body and buried oxide fully depleted silicon on insulator (UTBB-FDSOI) are the main transistors currently used in advanced integrated circuits (ICs). The tunable electrical properties via back-biasing facilitate the threshold voltage adjustment and enable IC designers to achieve a highly efficient and low-power-consuming operation. This study compares the modulation rate before and after hot carrier stress (HCS) of bulk FinFETs, UTBB-FDSOI ( t BOX = 20 nm), and SOI FinFETs ( t BOX>150 nm) via back-biasing. Simplified back-impedance models are proposed based on the impact of back-biasing on electrical characterization. Additionally, HCS with back-biasing shows a higher impact on UTBB FDSOI than on bulk FinFETs during reliability test, implying that the t BOX plays a critical role in the modulation rate. The lifetime with HCS indicates that the bulk FinFETs exhibit faster downscaling degradation than UTBB FDSOI probably due to the nature of multigate devices whose vertical electrical field should increase faster than planer devices during scaling.

HfO2-based gate stacks with titanium (Ti) incorporated into a GeO x interfacial layer (IL) were fabricated on p-Ge substrates. X-ray photoelectron spectroscopy results, incorporating Ti, can efficiently suppress the GeO volatilization. This contributed to achievement of an equivalent oxide thickness of approximately 0.8 nm, a low interface states density $\text{D}_{\textsf {it}}$ of approximately 2.5 $\times \,\,10^{\textsf {11}}$ eV $^{-\textsf {1}}$ cm $^{-\textsf {2}}$ , and a smaller $\text{D}_{\textsf {it}}$ increment of approximately 1 $\times \,\,10^{\textsf {11}}$ eV $^{-\textsf {1}}$ cm $^{-\textsf {2}}$ after constant negative voltage stress at a field of 8 MV/cm. Therefore, Ti is appropriate for improving the quality of GeOx through high temperature annealing.

A Virtual Gate model with surface traps at gate edge of drain side is modelled for AlGaN/GaN High Electron Mobility Transistor (HEMT). This model confirms the utility of a Field Plate (FP) enhances sheet carrier density and suppress current collapse. At the gate-edge of drain side, the channel electron density with Field Plate are 2.1 × 109 cm−3, 4.68 × 109 cm−3 and 8.63 × 109 cm−3 for LFP = 0.5 μm, LFP = 1 μm and LFP = 1.5 μm is increased with respect to Length of Field Plate, whereas without the Field Plate shows much lower electron density value of 1.14 × 109 cm−3 in the device. The increase of Drain current (Ids) from 736 mA/mm to 813 mA/mm with the increase in LFP from 0 μm to 1.5 μm is observed for Drain voltage (Vds) at 40 V. Furthermore, Field Plate shows a great control over electric field and trapped carrier density at gate edge of the device. The formulated model in this paper is correlated-well with the simulation result of AlGaN/GaN HEMT.

In this paper, we demonstrated the enhancement of thermal stability of nickel germanide (NiGe) alloy up to 600 °C by using titanium nitride (TiN) metal capping. A high ${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ ratio of $2.9 \times 10^{5}$ was achieved by capping TiN metal on Ni for NiGe alloy formation at 600 °C. Detailed analyses were performed for realizing the mechanism for TiN capping on NiGe/Ge, including vertical element diffusion profile observation through depth-profiling X-ray photoelectron spectroscopy (XPS), element diffusion distribution by energy-dispersive X-ray spectroscopy mapping, and direct junction leakage current path detection by conductive atomic force microscopy. The experimental results indicated that TiN capping can reduce the risk of agglomeration and form a graded NiGe/Ge Schottky junction that is beneficial for suppressing the degradation of junction leakage. Subsequently, we compared the electrical performance of TiN/NiGe/n-Ge at various N/Ti ratios of TiNs. Based on the depth-profiling XPS results and electrical performance, TiN with an N/Ti ratio of approximately 1:1 can resist the Ni and Ge diffusion, which facilitates the suppression of the agglomeration process. However, the TiN capping layers with an N/Ti ratio of less than approximately 1:1 (Ti-rich) were not favorable for resisting Ni and Ge diffusion.

We report a low current collapse GaN-based high electron mobility transistor (HEMT) with an excellent thermal stability at 150 °C. The AlN was grown by N2-based plasma enhanced atomic layer deposition (PEALD) and shown a refractive index of 1.94 at 633 nm of wavelength. Prior to deposit AlN on III-nitrides, the H2/NH3 plasma pre-treatment led to remove the native gallium oxide. The X-ray photoelectron spectroscopy (XPS) spectroscopy confirmed that the native oxide can be effectively decomposed by hydrogen plasma. Following the in situ ALD-AlN passivation, the surface traps can be eliminated and corresponding to a 22.1% of current collapse with quiescent drain bias (V DSQ) at 40 V. Furthermore, the high temperature measurement exhibited a shift-free threshold voltage (V th), corresponding to a 40.2% of current collapse at 150 °C. The thermal stable HEMT enabled a breakdown voltage (BV) to 687 V at high temperature, promising a good thermal reliability under high power operation.

In this paper, the impact of width quantization on device characteristic and stressing induced device degradation for high-k/metal tri-gate n/p-type FinFET was investigated well including electrical characteristic clarification and simulation. Carrier conduction in the trapezoidal shape Si-fin body of FinFETs is different for devices with different Fin bottom widths ( ${W} _{\mathbf {Fin\_{}bottom}}$ ), which will impact the device performance and reliability. For n-type FinFETs, the experimental results show that the thinner ${W} _{\mathbf {Fin\_{}bottom}}$ device performs better reliability under HCI stress due to higher inversion carrier density at the center of Si-fin channel. For p-type FinFETs under negative bias stressing, the thinner ${W} _{\mathbf {Fin\_{}bottom}}$ device shows more serious degradation on drain current ( ${I} _{\mathbf {D}}$ ) and subthreshold swing (SS) with the increasing of stressing voltage due to larger electric field within the Si-fin and higher energy of inversion holes, while the thicker ${W} _{\mathbf {Fin\_{}bottom}}$ device shows almost insensitively degradation with the variation of stressing voltage.

In this paper, hot-carrier injection (HCI) stress has been used to investigate the reliability of n-channel FinFET devices with different fin numbers. Threshold voltage (V TH ) shift, subthreshold swing and transconductance variation were extracted to evaluate the degradation of the device under stress. FinFET devices with fewer fins show more serious performance degradation due to hot-carrier injection stress. It is suggested that the existing of coupling effect between neighboring fins reduces the inversion charge density and equivalent electric field in multi-fin devices, which causes better reliability than single-fin devices.

We report deposition of pure AlN and Sc x Al 1-x N thin films with different Sc concentration on DLC/Si substrate by RF and DC reactive magnetron co-sputtering method by using Al and Sc as targets. The X-ray diffraction (XRD) results showed that the films have high c-axis-orientation. Electron probe microanalyzer (EPMA) analysis reveals the presence of scandium atoms reduce the space occupied by aluminum atoms, leading to lattice distortion during the phase transition. The SEM cross-section results showed that the Sc x Al 1-x N films are highly aligned along c-axis and have columnar like morphology. The top view of SEM results indicated that the new phase formation above Sc 30.33%, however no new peak appeared in the XRD pattern. The piezoelectric coefficient (d 33 ) of Sc x Al 1-x N thin films are measured and the highest value (11.54 pC/N) is achieved at x = 30.33% increasing 14 times, as that with AlN/DLC/Si, 0.73 pC/N. Sc x Al 1-x N films on DLC/Si substrate have a great potential to be applied on high frequency SAW devices in the future.

Horizontally five stacked pure-Ge nanosheets (NSs) GAA FETs are demonstrated. In this device process, we intentionally grow large mismatch Ge/Si multilayers rather than Ge/GeSi multilayers as the starting material, because the large difference of material properties between Ge/Si is beneficial to the selective etching process. In order to avoid island growth, the flat Ge/Si multilayers are grown at a low temperature. Due to the excellent selective etching, the shape of Ge NSs almost keeps unchanged after etching. Additionally we found the dislocations in suspended Ge sheets are more easily to remove than the case that Ge layers are still tied with Si layers. Since the stacked NSs channels is tall and the pitch between channels is short, the conventional wrap-around contact (WAC) is not applicable. Here for the first time we propose the conformal monolayer doping (MLD) method for source/drain doping of tall NSs FETs.

This paper presents the first monolithic 3D two-layer reconfigurable SRAM macro capable of executing multiple Compute-in-Memory (CiM) tasks as part of data readout. Fabricated using low cost FinFET based 3D+-IC, the SRAM offers concurrent data read from both layers and write from layer 2 with 0.4V $\text{V}_{\text{dd}\min}$ 12.8x improved computation latency is achieved as compared to near memory computation of successive Boolean operations.

A high-quality HfGeO

For the first time, ultra-low power ferroelectric FinFET-based monolithic 3D+-IC technology was demonstrated for near memory computing (NMC) circuit. Key enablers are ICP-SiO 2 interfacial layer, doped hafnia ferroelectric gate dielectric layer (HfZrO 2 ), and far-infrared laser activation. The proposed stackable 3D NC-FinFETs thus fabricated exhibit record-low sub-threshold swing (NC-nFinFET: 45mV/dec and NC-pFinFET: 50mV/dec) and high I on /I off (>106) that enable ultra-low power operation $(\mathrm{V}_{\text{DD}}=100\text{mV})$ of CMOS inverter and SRAM. Moreover, above mentioned features of NC-FinFETs and the differential output of SRAM readout enable 50+% area reduction in the near-memory computing circuitry.

In this work, we use thermal-ALD to prepare ferroelectric HfZrO 2 (HZO) thin film with thickness from 3 to 7 nm for the NC-FinFET's gate stack. The subthreshold swing (SS) was as low as 5 mV/dec (SSmin) over 4 orders of I D . Lower thermal budget process, CO 2 far-infrared laser activation and 400°C Ni silicide are employed in the 2-level metal backend integration for maintaining the orthorhombic phase in HZO thin film and minimizing the hysteresis in IV. NC-FinFET inverter has 77% higher voltage gain compared to FinFET-inverter employing HfO 2 gate dielectric. NC-FinFET ring oscillator exhibit small speed and power advantages over FinFET oscillator. For the first time, NC-FET cut-off frequency (F t ) frequency is measured, 23.1 GHz or 23% higher than the control FET Ft. NC-FinFET SRAM was observed to exhibit large noise margin.

A location-controlled-grain technique is presented for fabricating BEOL monolithic 3D FinFET ICs over SiO 2 . The grain-boundary free Si FinFETs thus fabricated exhibit steep sub-threshold swing ( $385\ \mu \mathrm{A}/\mu \mathrm{m}$ ), and high I on /I off (>106). According to simulation, the thickness of the interlayer dielectric plays an important role and shall be thicker than 250nm so that the sequential pulse laser crystallization process does not heat the bottom devices and interconnects to more than 400 °C.

Parkinson's disease (PD) is a progressive nervous system disorder that affects movement, whose early signs may be mild and unnoticed. α-Synuclein has been identified as the major component of Lewy bodies and Lewy neurites, which are the characteristic proteinaceous deposits that are the hallmarks of PD. In this work, three alpha-synuclein peptides were synthesized as templates for the molecular imprinting of conductive polymers to enable recognition of alpha-synuclein via ultrasensitive electrochemical measurements. The peptide sequences encompassed specific residues where mutations are known to accelerate PD (though the target sequences, in this study, were wild-type.) The different peptide targets were all successfully imprinted, but with differing imprinting effectiveness, probably owing to differences in target carboxylic acids (which can bind to the aniline (AN) m-aminobenzenesulfonic acid (MSAN) MIP polymers.) Composition of the imprinted polymer, (the mole proportions of AN and MSAN), and the concentrations and sequences of imprinted peptide templates were optimized by measuring the electrochemical responses to target peptides. The imprinted electrode can detect alpha-synuclein at fg/mL levels, and was therefore used to measure alpha-synuclein in the culture medium of human brain organoids generated from normal and idiopathic PD patients.

We propose a new HfGeO x interfacial layer (IL) for the high- $\kappa $ gate-stacks on p-type germanium substrate with improved thermal stability as compared with that of conventional GeO x IL. We inserted an additional HfO2 layer after the formation of GeO x in the HfO2/Al2O3/GeO x /Ge gate-stack by using plasma-enhanced atomic layer deposition. Through the use of post-deposition annealing and post-metal annealing, the new system exhibited greater thermal immunity and was stable up to 600 °C. We speculate that the improvement originates from the formation of HfGeO x through the combination of HfO2 and GeO x , according to the thermodynamic data. By incorporating Hf into interfacial layer, the fabricated high- $\kappa $ gate-stack with an equivalent oxide thickness of 1.2 nm, a low interface states density ( $D_{\mathrm {it}}$ ) of approximately $3.3 \times 10^{11}$ eV $^{\mathrm {-1}}$ cm $^{\mathrm {-2}}$ , and an impressive gate leakage current of approximately $ 2.2 \times 10^{\mathrm {-6}}$ A/cm2 at $V_{\mathrm {FB}} -1\text{V}$ .

Y.-W.L. and C.M.T. contributed equally to this work. This work was in part supported by the National Science Foundation (NSF) under Award No. NSF-EFRI-1433541. C.M.T.Jr. thanks the Department of Defense SMART (Science, Mathematics, and Research for Transformation) Scholarship for graduate scholarship funding. This research was funded in part by the National Science Council of Taiwan under Contract No. NSC 103-2917-I-564-017. The authors would like to acknowledge the collaboration of this research with King Abdul-Aziz City for Science and Technology (KACST) via The Center of Excellence for Green Nanotechnologies (CEGN). K.L.W., Y.-W.L., and C.M.T.Jr. conceived the idea and designed the experiments; Y.-W.L. and C.M.T.Jr. performed the electrical measurements; L.-J.L., M.Y.L., and Y.S. synthesized and contributed the materials; C.M.T.Jr. fabricated the devices; Y.-W.L., X. Z., W.-K.Y. and S.-H.T. analyzed the data. All of the authors discussed the results and wrote the paper together.

Two parts of work are included in this paper. In the first part, the novel Ge gate-all-around field effect transistors (GAA FETs) are introduced and discussed. Fabrication of Ge GAA FETs requires only simple top-down dry etching and blanket Ge epitaxy techniques readily available in mass production. First, a novel process to etch away the defective Ge near Ge/Si interface from epitaxial Ge grown on SOI achieves a nearly defect-free channel, good gate control triangular gate, larger effective width than rectangular fin, and have low punch-through current through the Si substrate. By dislocation removal, the defect-free Ge channel can be formed on nothing. The ${p}$ -channel triangular Ge GAA FET with fin width ( ${W} _{\mathrm{ fin}}$ ) of 52 nm and Lg of 183 nm has $\text{I}_{\mathrm{ on}}/\text{I}_{\mathrm{ off}} = 10^{5}$ , SS = 130 mV/dec, and Ion = 235 $\mu \text{A}/\mu \text{m}$ at -1 V. Next, due to the highest electron mobility (2200 cm2/Vs) on (111) Ge surface, the $n$ -channel triangular Ge GAA FET with (111) sidewalls on Si and Lg = 350 nm shows 2 times enhanced Ion with respect to the devices with near (110) sidewalls. Electrostatic control of SS = 94 mV/dec (at 1 V) can be further improved if superior gate stack than EOT = 5.5 nm and Dit $= 1\times 10^{12}$ cm $^{-2} \cdot $ eV $^{-1}$ is used. The Ion can be further enhanced if the line edge roughness (LER) can be reduced. Second, a feasible pathway to scale the Ge MOSFET technology by using a novel diamond-shaped Ge GAA FET with four {111} facets is also reviewed. The proposed dry etching process involves three isotropic/anisotropic etching steps with different Cl2/HBr ratios for forming the suspended diamond-shaped channel. Taking advantages of the GAA configuration, favorable carrier mobility of the {111} surface, and nearly defect-free suspended channel, nFET and pFET with excellent performance have been demonstrated, including an $\text{I}_{\mathrm{ on}}/\text{I}_{\mathrm{ off}}$ ratio exceeding $10^{8}$ , the highest ever reported for Ge-based pFETs. The TMD FinFET devices are reviewed in the second part of this paper. The TMD FinFET channel is deposited by CVD. MoS2 covered on Si fin and nanowire resulted in improved (+25%) $\text{I}_{on}$ of the FinFET and nanowire FET. The PFETs also operated effectively and the N/P device $\text{V}_{\mathrm{ th}}$ are low and matched perfectly. The proposed heterogeneous Si/TMD 3DFETs can be useful in future electronics. Furthermore, a 4 nm thin transition-metal dichalcogenide (TMD) body FinFET with back gate control is also proposed and reviewed. Hydrogen plasma treatment of TMD is employed to lower the series resistance. The 2 nm thin back gate oxide enables 0.5 V of $\text{V}_{\mathrm{ th}}$ shift with 1.2 V change in back bias for correcting device variations and dynamically configuring a device as a high performance or low leakage device. TMD can potentially provide sub-nm thin monolayer body needed for 2 nm node FinFET.

Three-dimensional sequentially stackable high- $k$ /metal-gate-stacked tri-gate nanowire poly-Si FETs with embedded source/drain (e-S/D) and back gate were demonstrated. The highly crystallized channel, fabricated by green nanosecond laser crystallization, chemical mechanical polish, and postsurface modification processes, enhances the electrical property of the tri-gate nanowire FET. The e-S/D structure reduces the contact and series resistances caused by the nanowire structure. Thus, the fabricated n/p-type tri-gate nanowire poly-Si FETs exhibit steep subthreshold swings (96/125 mV/decade), high ON-currents (232/110 $\mu \text{A}/\mu \text{m}$ ), and $I_{{\mathrm{\scriptscriptstyle {on}}}}/I_{\mathrm{\scriptscriptstyle {OFF}}}$ ratio ( $> 10^{5})$ . Furthermore, the independent back gate with thin back gate oxide can easily adjust the threshold voltage of the tri-gate nanowire transistor and results in high gamma value (>0.05) FET realizing sequentially stacked and low $V_{\mathrm {dd}}$ (0.6 V) operable inverter.

A downconversion mixer using the double-balanced Gilbert cell structure is fabricated using 65-nm CMOS technology. The mixer maximum conversion gain is −0.93 dB, IF output power at the 1-dB compression point is −4 dBm, and IIP3 is 6.12 dBm with IF at 1 GHz. In addition, mixer reliability subjected to dynamic stress at elevated ${V}_{\mathrm{DD}}$ is examined experimentally. Transistor measurement was investigated to provide physical insight into the stress effect on device and circuit degradation.

We successfully fabricated gate stacks (ZrO2/GeO x /Ge) with a subnanometer equivalent oxide thickness (EOT) and low-leakage current on n-/p-Ge through plasma-enhanced atomic layer deposition (ALD). A 0.78-nm-thick GeO x was formed through plasma oxidation (i.e., in situ plasma interfacial passivation, followed by 3.48-nm-thick ZrO2 growth in the same ALD reactor). A subnanometer EOT of $\sim 0.9$ nm was achieved with a relatively high dielectric constant (roughly 30) of tetragonal-phase ZrO2. The gate leakage was $\sim 1 \times 10^{-4}$ A/cm2 at $\text{V}_{\mathrm {\mathbf {FB}}} - 1$ V, and roughly $5 \times 10^{-5}$ A/cm2 at $\text{V}_{\mathrm {\mathbf {FB}}} + 1$ V on p- and n-type Ge, respectively. Our ZrO2 stabilized in the tetragonal phase, when the post-deposition annealing temperature, was higher than 500 °C. Therefore, the proposed scheme is simple and effective for use in pursuing an ultralow EOT gate dielectric on Ge.

In this work, both channel coupling effect and compressive stress were found to influence the performance and reliability for p-type FinFET. With fin number increasing, the carrier density in the channel is reduced due to the coupling effect between the neighboring fins. On the other hand, with the enlarging of the area of contact etch stop layer (CESL) due to fin number increasing, hole mobility is enhanced because of active surface area (SA) induced compressive stress. As a result, multi-fin FinFET device with more fins shows lower normalized drain current due to reduced carrier density, and worse reliability could also be observed because of hotter carriers in the channel.

In this work, constant voltage stress (CVS) induced interfacial trap and its effect on subthreshold slope (SS) degradation were studied for the first time by the random telegraph noise (RTN) technique. Part of the generated traps were located in the interfacial layer (IL) under CVS. Both the trap location and trapping number show a large impact on SS degradation, and it could be demonstrated by RTN. If the trap depths are similar, more traps cause more severe SS degradation. If the trap depths are different, shallow trap shows larger impact on SS degradation than that of deep trap even if the trapping charges of deep trap are more than that of shallow trap.

In this work, the influence of interface traps at the Si 3 N 4 / (GaN) / AlGaN interface and carbon-related buffer traps on AlGaN/GaN-on-silicon high electron mobility transistors (HEMTs) has been studied using high-frequency capacitance-voltage (HFCV) and quasi-static C- $V$ (QSCV) measurement. The correlation between Ron degradation and two different traps distributions subjected to different operation conditions have been investigated. Deep-level traps from the hole-emission process of carbon-related buffer have been activated by high drain voltage under off-state in pulse-mode condition and shallow-level traps from interface states are observed with an increase in gate voltage under on-state.

We report heterogeneously integrated sub-40nm epi-like monolithic 3DIC with vertical ReRAM and memory computing (NMC) circuit. High driving current multi-channel UTB-MOSFETs (3.3/1.4 mA$/\mu \mathrm {m}$ for N/P FETs) was realized by low thermal budget super-CMP-planarized visible laser-crystallized epi-like Si channel and CO 2 far-infrared laser annealing (CO 2 -FIR-LA) activation technologies that enable driving 20nm 4-layer vertical ReRAM (Set/Reset $ \lt 1.2\mathrm {V}/1.8\mathrm {V}$, 3-bits/cell). Furthermore, the ultra-low threshold voltage of NC-FinFETs and the differential output of SRAM readout enable 50 +% area reduction in the near-memory computing circuitry. The unique TSV-free monolithic $3\mathrm {D} ^{+}$ IC process provides the superiority in 3D hetero-integration to realize low cost, small footprint, fully functionalized 3D IoTs chip.

The impact of a realistic representation of gate-oxide granularity on negative-capacitance (NC) FETs at sub-5nm node is studied by a newly developed thermodynamic energy model based on the first principle calculation (FPC). For the first time, the calculation fully couples the Landau-Khalatnikov (L-K) equation with grain-size effect equation in NC-FETs. It explains the experimental results in phase transition and reveals excellent immunity against depolarization in ferroelectric (FE) layer owing to dopant concentration and stress in thin films. A sub-5nm node (LG=10nm) NC-FET with thin FE layer (T FE ~2nm) is integrated to achieve low subthreshold slope (SS) of 52mV/dec via a 1.9GPa-tensor stressed interfacial layer (IL) and 12% Zr-doped HfO 2 .

In this work, we provide self-powered vibration sensor with broadband vibration sensing capability of 20 Hz ∼ 2000 Hz by vertical assembly of 3D coils and magnet without conventional deep-etching process, remote/ contactless temperature sensor (20 °C ∼ 160 °C) under < 1 μWatt power consumption, low power interface circuit (gain ∼70) in low threshold voltage (∼0.25V) Fin-FET, and MEMS heterogeneous packaging technology to demonstrate the capabilities of integration multi-sensor with read-out interface circuit for detecting variant physical parameter in the same chip. Comparing conventional vibration sensor with our device, the completely new design concept of the latter in this work benefits ultra-low vibration frequency detection. It deserves to be mentioned the vertical assembly technology reduces the complex integration issue to improve the chip yield. We also reveal the stability of the proposed vibration sensor to detect vibrating behavior during 1.5 hr and over one month in the dry pump of Lam 2300 etcher and the grinding-head in conventional optical lens forming machine, respectively. Therefore, the multi-functional sensing platform profits the demanded applications like IoT or smart manufacturing in Industry 4.0.

This paper presents the first monolithic 3D vertical cross-tier computing-in-memory (CIM) SRAM cell fabricated using low cost TSV-free FinFET-based 3D+-IC technology. The 9T 3D CIM SRAM cell is able to compute NAND/AND, OR/NOR and XOR/XNOR operations within a single memory cycle. We fabricated stackable multi-fin single-grained Si FinFET using low thermal-budget CO 2 far-infrared laser annealing (FIR-LA) for activation and self-aligned silicide. The proposed device achieved high Ion (320 μA/μm (n-FET) and 275 μA/μm (p-FET)) and high I on /I off (>107). The proposed scheme enables the fabrication of energy and area efficient circuits for cost-aware intelligent IoT devices. For proposed 9T CIM SRAM cell, the monolithic 3D device reduces area overhead by 51%, compared to the 2D version, thanks to the stacking of three additional transistors above the 6T SRAM cell.

This study compares the effects of n-channel double-gate FinFETs with fin widths $(W_{\rm fin} ) $ of 10 and 25 nm with those of such devices with back biases and hot carrier injection (HCI. Compared with the device with a wide $W_{\rm fin}$ , the device with a narrow $W_{\rm fin} $ exhibits a larger current tuning range but a more off-state current leakage at a positive back bias because of the forward-biased p-n junction and the higher degradation under HCI. The gate-induced drain leakage significantly deteriorates with a positive back bias after HCI because of the generation of interfacial charges. However, a negative back bias causing hot hole injection during HCI can alleviate the degradation compared with unbiased and positive-biased devices.

In this study, we investigate the impact of junction doping distribution (LDD/halo) on variations and asymmetry of device characteristics for fully depleted silicon on insulator (FDSOI) with ultrathin buried oxide layer nMOSFET. The device performance and hot carrier induced degradations have also been examined. Junction doping dose of LDD/halo affects the effective channel length, parasitic source/drain resistance, and channel mobility. High junction doping dose enhances the device's performance but degrades device stability and reliability. Compared to high junction doping FDSOI nMOSFET, low junction doping device has lower device variability, better symmetry, and reliability, but suffers lower channel mobility and device driving capability.

Viral infections have long been the biggest threat to human survival, and from a medical perspective, the development of noninvasive high-throughput screening methods that target the incubation period to either treat diseases or limit viral spread would be strikingly effective. Using this technology to target viral incubation periods would also be inexpensive to perform. The current study proposes to transform pulse signals into a rapid diagnostic test using “coincidence analysis” in the hope of preventing or reducing the symptoms of viral infections. The heart plays a critical role in calculating and supplying the needs of all tissues of the body. Pulse waves are pressurized signals in response to heart’s calculations and include all phases of the cardiac cycle, which maintains life and provides energy needed to perform tasks. Any small movement gives a corresponding signal to pulse waves. The current study investigated conclusive data on self-limiting infections, such as common cold. We used pulse wave, coincidence analysis technology to capture signals from individuals with common cold during the incubation period and investigated if particular characteristic signals could be applied to influenza during the incubation period. Preliminary work demonstrated that pulse waves could generate signals using this technology that would be worthwhile for future research. A small amount of analytical data from common cold existed previously. The data structure is based on the idea that a single pulse wave at differing physiological conditions would have slight modifications that would be amplified and presented by various geometrical shapes after extensive data are accumulated. These geometric shapes can then be sliced vertically or horizontally to extract data during different illness stages. The significance of these findings are impressive; from a personal or a public hygiene perspective, this analytical technology provides many benefits, such as rapid and precise decision-making that can be directly visualized or can be analyzed using software programs. Also, this technology also uses futuristic wearable technology that brings practical problem solving to physiology.

High-frequency operation with ultrathin, lightweight, and extremely flexible semiconducting electronics is highly desirable for the development of mobile devices, wearable electronic systems, and defense technologies. In this work, the experimental observation of quasi-heterojunction bipolar transistors utilizing a monolayer of the lateral WSe2–MoS2 junctions as the conducting p–n channel is demonstrated. Both lateral n–p–n and p–n–p heterojunction bipolar transistors are fabricated to exhibit the output characteristics and current gain. A maximum common-emitter current gain of around 3 is obtained in our prototype two-dimensional quasi-heterojunction bipolar transistors. Interestingly, we also observe the negative differential resistance in the electrical characteristics. A potential mechanism is that the negative differential resistance is induced by resonant tunneling phenomenon due to the formation of quantum well under applying high bias voltages. Our results open the door to two-dimensional material...

Amorphous silicon bolometers with different pixel patterns are investigated for far infrared detection. Devices with floating resonator structure are measured for resistances and temperature coefficient of resistance (TCR) values. The results show normal leg geometry has high TCR (∼ −4%/°C) and moderate resistance. Thus the pixel pattern is suitable for infrared detecting applications.

Three different multiple-valued logic (MVL) designs using the multiple-peak negative-differential-resistance (NDR) circuits are investigated. The basic NDR element, which is made of several Si-based metal-oxide-semiconductor field-effect-transistor (MOS) and SiGe-based heterojunction-bipolar-transistor (HBT) devices, can be implemented by using a standard BiCMOS process. These MVL circuits are designed based on the triggering-pulse control, saw-tooth input signal, and peak-control methods, respectively. However, there are some transient states existing between the multiple stable levels for the first two methods. These states might affect the circuit function in practical application. As a result, our proposed peak-control method for the MVL design can be used to overcome these transient states.

In this paper, the impact of fin number on device performance and hot carrier induced device degradation was investigated for n-channel tri-gate multi-fin FinFET with different fin numbers. The threshold voltage (VTH) shift, transconductance, and subthreshold swing degradation were extracted to determine the degradation of device. It was found that the device with fewer fins shows better device performance, but suffer from more serious hot carrier induced device degradation. It is suggested that the existed coupling effect between the fins reduces the equivalent electric field in the multi-fins devices, thus shows better reliability than the single-fin device does after hot carrier stress.

Skin is the largest organ of the human body and a physiological structure that is directly exposed to the environment. From a theoretical perspective, numerous physiological and psychological signals use the skin as a medium for input and output with the outside world. Therefore, the skin is considered an optimal signal interception point when developing noninvasive, direct, and rapid signal exploration devices. To date, skin signal interceptions are predominantly performed by measuring skin impedance. However, this method is prone to interference such as sweat secretion, salt accumulation on the skin, and muscle contractions, which may result in a substantial amount of interference and erroneous results. The present study proposes novel and effective methods for skin signal interception, such as using a nested probe as a sensor to measure capacitance to be further processed as physiological and psychological signals. The experimental results indicate that the capacitance curve for the transition between wakefulness and dozing exhibits significant changes. This change in the curve can be analyzed by computer programs to clearly and rapidly determine whether the subject has entered the initial phases of sleep.

For the first time, we report low-cost heterogeneously integrated sub-40nm epi-like Si monolithic internet of thins (IoT) 3D+-IC with wireless communication, light-electricity power management and vertical ReRAM (VRRAM) modules. High current driving multi-channel 3D+ UTB-MOSFETs (600μA/282μA@VG= ± 1V for 10-channel P/N FETs) was fabricated by low thermal budget super-CMP-planarized visible laser-crystallized epi-like Si channel and CO 2 far-infrared laser annealing (CO 2 -FIR-LA) activation technologies that support a 6.8GHz high frequency VCO circuits, 0.5V low-voltage power management circuit and drives 20nm 4-layer VRRAM (Set/Reset

Ge peaking n- and p-FinFETs have been demonstrated by adopting neutral beam etching (NBE) and anisotropic neutral beam oxidation (NBO) processes. The irradiation-free NB processes not only suppress surface roughness but also guarantee low defect generation on the etched Ge surface. The fabricated Ge peaking FinFETs possess several unique features: (1) A peaking fin configuration with a 6-nm top-gate formed by an anisotropic NBO process at room temperature. (2) Nearly defect-free three dimensional channel surfaces by NB processes. (3) Ion and Gm improvement by NB processes as compared to that by conventional inductively coupled plasma etching (ICP). (4) Recorded high Ion/Ioff ratio and low subthreshold swing (S.S. ∼ 70 mV/dec.) of Ge n-FinFETs. (5) Excellent immunity for short channel effect of Ge FinFETs.

The ability to learn from few examples, known as one-shot learning, is a hallmark of human cognition. Hyperdimensional (HD) computing is a brain-inspired computational framework capable of one-shot learning, using random binary vectors with high dimensionality. Device-architecture co-design of HD cognitive computing systems using 3D VRRAM/CMOS is presented for language recognition. Multiplication-addition-permutation (MAP), the central operations of HD computing, are experimentally demonstrated on 4-layer 3D VRRAM/FinFET as non-volatile in-memory MAP kernels. Extensive cycle-to-cycle (up to 1012 cycles) and wafer-level device-to-device (256 RRAMs) experiments are performed to validate reproducibility and robustness. For 28-nm node, the 3D in-memory architecture reduces total energy consumption by 52.2% with 412 times less area compared with LP digital design (using registers as memory), owing to the energy-efficient VRRAM MAP kernels and dense connectivity. Meanwhile, the system trained with 21 samples texts achieves 90.4% accuracy recognizing 21 European languages on 21,000 test sentences. Hard-error analysis shows the HD architecture is amazingly resilient to RRAM endurance failures, making the use of various types of RRAMs/CBRAMs (1k ∼ 10M endurance) feasible.

An atomic-scale numerical study of Si contact with transition metal dichalcogenides (TMD) semiconductor materials is proposed by first-principles simulation for the first time. The monolayer MoS 2 channel can be operated as both of n- and p-type FET by properly doping Si S/D to adjust the TMD channel potential. The gradient MoS x junction of dichalcogenide vacancies enables Si-MoS 2 contact resistance lower than 100Ω-μm for interface Schottky barrier height reduction. The compact Si-MoS 2 interface study can potentially provide monolayer TMD contact design guideline for the sub-5 nm TMD FET fabrication technology.

A footprint-efficient and power-saving BEOL compatible 3D+IC carrying monolithic 3D stackable FinFETs (3D+ FinFETs) and W interconnect were demonstrated by low thermal budget laser spike anneal technology (Tsub 7) 3D+ FinFETs exhibit steep subthreshold swing (S.S.∼65mV/dec.), record high driving current (I on per W Eff (W Eff =2H Fin +W Fin ): 386 μA/μm (n-type) and 352μA/μm (p-type)), and high I on /I off (>107), envisioning next generation low-cost heterogeneously integrated IoTs and wearable electronics.