357 results on '"Poncino, M."'
Search Results
52. Efficient Computation of Discharge Current Upper Bounds for Clustered Sleep Transistor Sizing
53. Dynamic Thermal Clock Skew Compensation using Tunable Delay Buffers
54. Low-energy RGB color approximation for digital LCD interfaces
55. Thermal resilient bounded-skew clock tree optimization methodology
56. A cross-level verification methodology for digital IPs augmented with embedded timing monitors.
57. Energy-efficient bus encoding for LCD digital display interfaces
58. RTL power estimation in an HDL-based design flow
59. Balanced reconfiguration of storage banks in a hybrid electrical energy storage system.
60. Scheduling battery usage in mobile systems
61. Discharge current steering for battery lifetime optimization
62. Post-placement temperature reduction techniques.
63. Power-gating: More than leakage savings.
64. Analysis of NBTI-induced SNM degradation in power-gated SRAM cells.
65. THERMINATOR: Modeling, control and management of thermal effects in electronic circuits of the future.
66. A novel architecture for power maskable arithmetic units
67. Systemc cosimulation and emulation of multiprocessor soc designs
68. Placement-aware clustering for integrated clock and power gating.
69. Integrating Clock Gating and Power Gating for Combined Dynamic and Leakage Power Optimization in Digital CMOS Circuits.
70. A Scalable Algorithmic Framework for Row-Based Power-Gating.
71. Multiple power-gating domain (multi-VGND) architecture for improved leakage power reduction.
72. Reducing leakage power by accounting for temperature inversion dependence in dual-Vt synthesized circuits.
73. Interactive presentation: Efficient computation of discharge current upper bounds for clustered sleep transistor sizing.
74. Locality-driven architectural cache sub-banking for leakage energy reduction.
75. Timing-driven row-based power gating.
76. Dynamic thermal clock skew compensation using tunable delay buffers.
77. Layout-driven memory synthesis for embedded systems-on-chip
78. Dynamic Management of Thermally-Induced Clock Skew: An Implementation Perspective.
79. Synchronization-Driven Dynamic Speed Scaling for MPSoCs.
80. Discharge current steering for battery lifetime optimization
81. Frame buffer energy optimization by pixel prediction.
82. Energy-efficient color approximation for digital LCD interfaces.
83. Software/network co-simulation of heterogeneous industrial networks architectures.
84. Analyzing power consumption of message passing primitives in a single-chip multiprocessor.
85. Reducing cache misses by application-specific re-configurable indexing.
86. A timing-accurate modeling and simulation environment for networked embedded systems.
87. Energy-aware design techniques for differential power analysis protection.
88. A SystemC-based framework for properties incompleteness evaluation.
89. Parameterized RTL power models for soft macros
90. Discrete-time battery models for system-level low-power design
91. Stream synthesis for efficient power simulation based on spectral transforms
92. Synthesis of power-managed sequential components based on computational kernel extraction
93. From architecture to layout
94. Wire placement for crosstalk energy minimization in address buses.
95. Virtual in-circuit emulation for timing accurate system prototyping.
96. Modeling network embedded systems with NS-2 and SystemC.
97. Legacy SystemC co-simulation of multi-processor systems-on-chip.
98. From architecture to layout.
99. Extending lifetime of portable systems by battery scheduling.
100. Low-energy encoding for deep-submicron address buses.
Catalog
Books, media, physical & digital resources
Discovery Service for Jio Institute Digital Library
For full access to our library's resources, please sign in.