Search

Copyright of Elektronik Industrie is the property of Hüthig GmbH and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

Despite the higher thermal conductivity and the higher lifetime offered by silver sintering technologies, most packaged GaN devices are attached using solders due to technological difficulties in the sintering process. In this work, a silver sintering process for a packaged GaN power transistor on a printed circuit board (PCB) was successfully developed. Different sintering paste types were examined regarding their suitability for this application. Electrical measurements, shear tests, and metallographic cross sections were used for the evaluation. Numerical analyses were used to study the internal stress distribution in the GaN package after sintering depending on the paste structure. In the final sintering process, a shear strength of 20 MPa for sintering at 15 MPa and 240°C, for 300 s with electrical functional devices could be obtained by using nanoscale sintering paste. The authors contribute this to the high initial stiffness of the silver layer, which is obtained much earlier in the sintering process compared with the stiffness of a microscale silver paste. This high initial stiffness counteracts the semiconductor device deflection from the applied sintering pressure and reduces the stresses inside the semiconductor. [ABSTRACT FROM AUTHOR]

Usually, the printed circuit board industry has to use special subtractive manufacturing methods, if small line and space dimensions down to 50 μm are desired. This drastically raises production effort and costs. In this article, a method is shown as to how the inkjet technology can be used to produce passive RF structures with minimum line and space dimensions of 25 μm. For the first time, this is possible over complete panels of low-cost printed circuit board (PCB) substrates, which have a relatively high surface roughness compared to ceramic or glass carriers. To ensure process reliability, printed lines must also be plated with an additional electroless copper layer to overcome the surface roughness with conductive layers and to lower insertion loss in the two-digit GHz range. Additionally, a surface impedance model is developed, which allows broadband first time right simulations. Finally, additively produced, passive RF filters are compared to their subtractive counterparts to show their benefits regarding production costs and electrical performance up to 80 GHz. [ABSTRACT FROM AUTHOR]

The article defines digital methods for controlling the quality of chemical processes. An architecture of a digital production line, which ensures the distribution of the computational load between the system components, is proposed. We considered the process of developing a prototype of a digital production site for servicing the etching operation during which controllable process parameters are determined; both hardware and software structures of the digital site are proposed. Studying the site operability, we determined the relationships between the process parameters, which made it possible to determine the boundaries of the designed system. [ABSTRACT FROM AUTHOR]

This paper studies demand satisfaction and decision-making for a printed circuit board (PCB) manufacturing system. A performance indicator, the system reliability, is proposed to evaluate the demand satisfaction. In particular, two important characteristics, (i) multiple production lines in parallel and (ii) multiple repair actions, are considered in this study. The PCB manufacturing system is modelled as a stochastic-flow manufacturing network (SFMN) by the graphical transformation and decomposition techniques. Based on the network-structured SFMN, this paper develops an algorithm to generate all minimal capacity vectors that workstations should provide to satisfy a given demand. In terms of all minimal capacity vectors, the system reliability is derived. In addition, the reliable production policy is determined based on each single minimal capacity vector. [ABSTRACT FROM AUTHOR]

This paper deals the scheduling identical parallel batch-processing machines (BPMs) that each machine can be process a group of jobs as a batch simultaneously. The paper presents a new bi-objective-mixed integer linear programming model for BPM in which arbitrary job size, unequal release time and capacity limits are considered as realistic assumptions occur in the manufacturing environments. The objectives are to minimise the makespan and the total weighted earliness and tardiness of jobs (just in time). After developing a new bi-objective model, anɛ-constraint method is proposed to solve the problem. This problem has been known as Np-hard. Therefore, two multi-objective optimisation methods, namely, fast non-dominated sorting genetic algorithm (NSGA-II) and multi-objective imperialist competitive algorithm (MOICA) are employed to find the pareto-optimal front for large-sized problems. The parameters of the proposed algorithms are calibrated using Response surface methodology (RSM) and the performances of the proposed algorithms on the problems of various sizes are analysed and the computational results clarify that MOICA outperform than NSGA-II in quality of solutions and computational time. [ABSTRACT FROM PUBLISHER]

The article offers information on the DVS-GMM conference "EBL - Electronic Assemblies and Printed Circuit Boards" held in Fellbach, Germany from March 5th to 6th, 2024, emphasizing sustainability and energy efficiency with smart electronics. Topics included a wide range of subjects from intelligent data processing to innovations in chip and assembly technology, and innovative training methods like mobile soldering workstations with augmented reality for remote learning.

• Multi-functional lanthanide-doped silicate glasses were synthesized by the sol-gel method. • Raman-active vibration modes confirmed the influence of lanthanides in the structural bonding that augments the electrical conductivity of the glasses. • Er3+ doped glass with the highest dielectric constant of 9.21 × 105 at 0.1 Hz demonstrates its potential for cathode plating in batteries. • Sm3+ infused glass evidencing a low dielectric constant could be suggested for microelectronic components in printed circuit boards that necessitate low signal losses. Lanthanide-doped silicate glasses were subjected to structural and temperature-dependent electrical investigations to validate their multi-functionality in the integrated microelectronic industries. Raman-active vibrations around 920 cm−1 and 1330 cm−1 confirmed the silicate and phosphate tetrahedra respectively. The Er3+ doped glass demonstrated the highest dielectric constant of 9.21 × 105, while Sm3+ infused glass exhibited the lowest dielectric constant of 4.37 × 104 at 0.1 Hz and 473 K. The Sm3+ doped glasses are prospective for plating on copper chips in printed circuit boards that necessitate low dielectric constants to minimize propagation delay. The equivalent circuitry fitted for the Nyquist impedance plot of Er3+ doped glass constituted parallel combinations of a resistor and Constant Phase Element (CPE), in series with Warburg diffusion impedance. The CPE approaching a capacitive nature in the Er3+ doped glass could be suggested for cathode plating in batteries, and fabrication of multi-layer dielectric substrates in radio frequency condensers. [Display omitted] [ABSTRACT FROM AUTHOR]

In this study, the reliability of the solder joints of a heterogeneous integration of one large chip (10 × 10 mm) and two smaller chips (735 mm) by a fan-out method with a redistribution layer-first substrate fabricated on a 5153510-mm panel is investigated. Emphasis is placed on the thermal cycling test (25°C D 125°C, 50-min cycle) of the heterogeneous integration package on a printed circuit board (PCB). The thermal cycling test results are plotted into a Weibull distribution. The Weibull slope and characteristic life at median rank are presented. At 90% confidence, the true Weibull slope and the true 10% life interval are also provided. A linear acceleration factor is adopted to map the solder joint reliability at the test condition to the solder joint reliability at an operating condition. The failure location and failure mode of the PCB assembly of the heterogeneous integration package are provided and discussed. A nonlinear, time- and temperature-dependent 3-D finite element simulation is performed for the heterogeneous integration PCB assembly and correlated with the thermal cycling test results. [ABSTRACT FROM AUTHOR]

Drawing from psychological contract, job demands-resources, and affective events theories, this paper proposes and tests a research model where employee engagement (ENG) mediates the impact of psychological contract breach (PCB) on task-related pro-environmental behaviors (TPEBs), proactive pro-environmental behaviors (PPEBs), and intent to remain with the organization (IRO). The linkages given above were assessed via structural equation modeling. Based on data obtained from hotel customer-contact employees in three waves and their immediate supervisors in China, the findings reveal that PCB is a stressor eroding employee ENG, TPEBs, PPEBs, and proclivity to remain with the organization. Employees with high ENG display pro-environmental behaviors at high levels and exhibit elevated IRO. These findings implicitly illustrate that employee ENG partly mediates the impact of PCB on TPEBs, PPEBs, and proclivity to remain with the organization. Implications of these findings are discussed, as are the limitations and avenues for future research. [ABSTRACT FROM AUTHOR]

This paper deals with a scheduling optimisation problem arising in printed circuit board (PCB) assembly. In one class of PCB assembly, light-emitting diodes are to be assembled into the placement locations on PCBs by a machine with multiple pick-and-place heads. The scheduling optimisation problem is to determine the assembly sequence of placement locations and the assignment of pick-and-place heads for locations so as to minimise the assembly time. We formulate it as a mixed integer linear programming model. To solve the problem efficiently, we classify the PCBs into two types. For the first type of PCBs, on which the locations are linearly arranged, a constructive heuristic is proposed based on the analysis of the best next location after a location is assembled. For the second type of PCBs, on which the locations are circularly arranged, a heuristic based on clustering strategy and path relinking method is proposed. Computational experiments show that the solutions obtained by the two heuristics make 2.32 and 6.82% improvements averagely for the PCBs with linearly and circularly arranged locations, respectively, as compared to the solutions used in real production, and they are also better than those obtained by a hybrid genetic algorithm. [ABSTRACT FROM AUTHOR]

In this investigation, the chip-last, redistribution-layer (RDL)-first, fan-out panel-level packaging (FOPLP) for heterogeneous integration is studied. Emphasis is placed on the materials, process, fabrication, and reliability of a heterogeneous integration of one large chip (10 3 10 mm2) and two small chips (7 3 5 mm2) by an FOPLPmethod on a 20320-mm2 RDL-first substrate fabricated on a 515 3 510 mm2 temporary glass panel. Reliability test such as the drop test of the heterogeneous integration package on a printed circuit board (PCB) is performed, and test results including failure analysis are presented. Some recommendations are also provided. [ABSTRACT FROM AUTHOR]

:The existing literature on process scheduling issues have either ignored installation times or assumed that installation times on all machines is free by association with the task sequence. This working arrangement addresses hybrid flow shop scheduling issues under which there are sequence-dependent configuration times referred to as HFS with SDST. This family of production systems are common in industries such as biological printed circuit boards, metallurgy and vehicles and automobiles making. Due to the increasing complexity of industrialized sectors, simple planning systems have failed to create a realistic industrial scheduling. Therefore, a hybrid multi-agent and immune algorithm can be used as an alternative approach to solve complex problems and produce an efficient industrial schedule in a timely manner. We propose in this paper a multi-agent and immune hybrid algorithms for scheduling HFS with SDST. The findings of this paper suggest that the proposed algorithm outperforms some of the existing ones including PSO (particle swarm optimization), GA (Genetic Algorithm), LSA (Local Search Algorithm) and NEHH (Nawaz Enscore and Ham). [ABSTRACT FROM AUTHOR]

The advancement of technology and the empowerment of the industry have made humans and robots more closely tied together, known as human-robot collaboration. A sector that specifically utilises this collaboration is the printed circuit boards industry. Therefore in this industry, proper allocation of tasks to humans and robots is crucial. This study investigates this type of allocation to minimise makespan. A Constraint Programming based (CP) approach is developed to solve the problem as the main novelty of this study. A single board problem, as the basic model, is developed by adding more assumptions including different groups of tasks, no-wait scheduling of tasks, multi-agent planning, and multiple boards sequencing. Then, different experimental instances are generated and solved to analyse the performance of CP and the sensitivity of idle time and makespan to key parameters of the problem. The superiority of the computational results of CP over mathematical programming is evident. [ABSTRACT FROM AUTHOR]

A drastically growing requirement of electronic packages with an increasing level of complexity poses newer challenges for the competitive manufacturing industry. Coupled with harsher operating conditions, these challenges affirm the need for encapsulated board-level (2nd level) packages. To reduce thermo-mechanical loads induced on the electronic components during operating cycles, a conformal type of encapsulation is gaining preference over conventional glob-tops or resin casting types. The availability of technology, the ease of automation, and the uncomplicated storage of raw material intensifies the implementation of thermoset injection molding for the encapsulation process of board-level packages. Reliability case studies of such encapsulated electronic components as a part of board-level packages become, thereupon, necessary. This paper presents the reliability study of exemplary electronic components, surface-mounted on printed circuit boards (PCBs), encapsulated by the means of thermoset injection molding, and subjected to cyclic thermal loading. The characteristic lifetime of the electronic components is statistically calculated after assessing the probability plots and presented consequently. A few points of conclusion are summarized, and the future scope is discussed at the end. [ABSTRACT FROM AUTHOR]

The printed circuit board assembly (PCBA) tends to become a bottleneck in an assembly line of electronic products. For improvement, many assembly firms have introduced chip shooter machines. This, however, in turn, raises the issue of how to best utilize these machines. To deal with the PCBA problems, swarm intelligence (SI)-based metaheuristics have been increasingly popular due to the use of guided search that can better drive solutions toward optimality. In this study, we have proposed a novel SI-based metaheuristics, termed improved shuffled frog-leaping algorithm (I-SFLA2), to deal with the feeder assignment problem (FAP), and component sequencing problem (CSP) simultaneously for a chip shooter machine. With novel features such as self-adaptive jump, push jump, direct-jump prevention, and self-adaptive variant, the I-SFLA2 can develop smart jumps for frogs to approach and search around elites quickly while avoiding being trapped in local optima. The I-SFLA2 includes the strategy of transitioning from exploration to exploitation by decreasing the number of memeplexes iteratively. Our small-sized experiments showed the I-SFLA2 had a high hit rate to the optimal solution whereas big-sized experiments showed the I-SFLA2 outperformed the basic SFLA (B-SFLA), B-SFLA(2), the improved SFLA (I-SFLA1), as well as the PSO2 proposed in previous studies. The computational times for the I-SFLA2 were found also reasonable for practical usage. Note to Practitioners—Chip shooter machines have been widely used in industry for printed circuit board assembly (PCBA). Approaches such as exact approach, simple heuristics, and metaheuristics have been proposed for PCBA planning. Although with the capability to find the optimal solution, the exact approaches are found to be computationally intractable when used to deal with a problem of a practical size. Although simple heuristics are easy to use, they usually have the difficulty to find the optimal/near-optimal solution. One recent trend is using metaheuristics to solve PCBA problems as they can avoid the computational intractability of exact approaches while improving over simple heuristics to find a better solution. In this study, we propose an improved shuffled frogs leaping algorithm (I-SFLA2), an advanced swarm intelligence (SI)-based metaheuristic to solve the CSP and FAP simultaneously for a chip shooter machine. With new features and smart jumps, the I-SFLA2 is able to find a better solution compared to some previously-proposed methods. [ABSTRACT FROM AUTHOR]

Purpose: Low relative humidity (RH) effect surface mount devices in numerous ways. The smaller size (0201) capacitor and resistor start wasting when RH is low. Due to low RH, electrostatic charges built-up on the surface of surface mount devices (SMDs) and component's reel. The positive charged SMDs stick with the negatively charged reel tape and are wasted. This paper comprehensively explores the environmental effects on 0201 size surface mount devices during mounting process. Different type and size of surface mount devices are tested in low and desired RH to validate the effectiveness of the proposed approach. This paper will also highlight high electrostatic discharge (ESD) due to low RH which can be detrimental for small size surface mount devices. The experimental and graphical illustrations will stipulate the results of success rate for mounting components. The effect on ESD, subsequently varying temperature and humidity will also be analyzed. Design/methodology/approach: In this paper, 0201 SDMs will be considered for analysis. The surface mount technology (SMT) plant temperature and humidity has been varied to examine the properties of small size SMDs. Total 5 hours production data are collected from Laptop motherboard production environment. This approach is applicable to all SMT environment. Findings: The authors reduced the wastage of 0201 chip size resistor and capacitor. Total 11 components are selected of this size, and there success rate is observed during mounting. These components are first observed in harsh environment where the temperature is first set to 20ºC and RH is set to 25 per cent. The success rate of these components is very low due to component's wastage. When the plant temperature is set to 25ºC and RH is set to 45 per cent, the success rate of mounting increased up to 100 per cent. A single component placement success rate with respect to RH is observed for one month. The results are shown in Table IV. It can be seen that the success rate is near 100 per cent when RH and temperature is maintained in production environment. To eliminate the ESD build-up in material and equipment in manufacturing environment humidification is a very effective way. When the RH is kept to 45 per cent, the moisture content of the air is a natural conductor and earths any ESD in environment. Originality/value: Experimental data have been obtained from Laptop motherboard manufacturing process to validate the effectiveness of proposed approach. [ABSTRACT FROM AUTHOR]

The topic of the given task based on the optical opposition of a mounted printed circuit board using National Instruments software. During the inspection, 7 types of resistors, 3 types of integrated circuits, barcodes and text were detected. The results of the detection have been visualized and a Microsoft Excel scan report has been exported. The optical inspection was carried out using the National Instruments Vision Development Module and LabVIEW development environments. [ABSTRACT FROM AUTHOR]

As all-printed digital circuits are in high demand to produce all-printed active devices, providing accurate and synchronized clocks to all of the printed circuits is an indispensible step. To supply the clock signal to a printed digital circuit, a printed ring oscillator has been considered as a practical solution. However, it is difficult to fully print the ring oscillators with a consistent and stable clock signal. To resolve this problem, we employed single walled carbon nanotube network (SWNTn) as active layers of printed thin film transistors (TFTs) to completely print the ring oscillator. In addition, using the extracted electronic properties from the printed SWNTn-TFTs, we designed a simulation model based on AIM-Spice Model 15 for the printed ring oscillator and compared the simulated clock signals with the experimentally measured values of the printed ring oscillator. [ABSTRACT FROM AUTHOR]

The aim of this paper is to measure production and marketing efficiencies in the printed circuit board (PCB) industry using grey relation analysis (GRA) and data envelopment analysis (DEA) techniques. A total of 32 efficiency indicators are initially considered and seven are selected. They represent five indicators for production efficiency and two for marketing efficiency. Fifteen of the 23 companies evaluated need improvement in both production and marketing efficiencies, while four companies had their priority production efficiency improvement and the remaining four companies with priority in marketing efficiency improvement. [ABSTRACT FROM AUTHOR]

Balancing setup effort and actual production time is an important issue in medium-variety, medium-volume printed circuit board (PCB) assembly. By grouping batches of similar PCB types to be processed with a common machine setup, the total time required for setting up the component feeders in the magazine of the placement machine can be reduced. On the other hand, the assembly times per PCB increase, since it is no longer possible to optimise the feeder locations in the magazine for each PCB type individually. In order to balance the savings in setup time and the increase in assembly time and to minimise the global makespan, we propose efficient grouping procedures which include machine-specific algorithms for fine-tuning the machine operations for a group of PCBs. Hence, the actual placement times are reflected much more accurately, compared with conventional grouping procedures which merely analyse the component similarity between pairs of PCBs. Two different agglomerative clustering techniques are proposed. One is based on average linkage clustering, the other on a novel hierarchical clustering approach using an inclusion tree representation of the PCB types. Both take the limited capacity of the component magazine into account. We demonstrate the effectiveness of our approach in an extensive numerical investigation of a single-gantry collect-and-place machine equipped with a rotary placement head and an interchangeable feeder trolley. Compared to conventional methodologies, the proposed group setup strategies reduce the global makespan for a given number of batches significantly. [ABSTRACT FROM AUTHOR]

The rapid growth in printed circuit board production has led to the growing importance of microdrilling. Owing to the trend for high-density circuits on printed circuit boards, the diameter of a microdrill has to be much finer than ever before. The inspection for microdrills becomes more difficult and the detection of defects is harder. An automated visual inspection scheme for detecting the major defects of microdrills is proposed. The colour images of microdrills are first derived, and the boundary of the lip relief plane is extracted. A robust K -curvature corner detection algorithm is then used to detect the corners on the blade boundaries and to split boundaries into segments. The least-squares linear regression method is used to fit the segments into linear equations. With the fitted equations, the intersections on the boundaries of two facets are located and their distances (gap or overlap) are measured. In addition, the defects of taper and flare are identified by comparing the angle measurements with predefined specifications. Two types of microdrills are used to verify the proposed inspection process. Experimental results show that the proposed scheme reliably achieves precise inspection. [ABSTRACT FROM AUTHOR]

Component placement sequencing is a challenging problem that arises in automated assembly of printed circuit boards. While for some placement machines all placement sequences are acceptable, in other cases some sequences are not allowed because of the shape of the placement head. In such cases, while the head moves down to perform a placement, it might damage a previously placed component, and the problem of determining a minimum cost and at the same time acceptable sequence leads to a Precedence Constrained Travelling Salesman Problem formulation. In this study, a solution procedure to such a formulation is developed and its implementation in a real PCB assembly environment is discussed. [ABSTRACT FROM AUTHOR]