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2,317 results on '"PACS 85.42"'

51. Memristive Logic-in-Memory Implementations: A Comparison

Author

Inglese, Pietro, Vatajelu, Elena Ioana, Di Natale, Giorgio, BEN TITO, Laurence, VDE, Architectures and Methods for Resilient Systems (AMfoRS ), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), and Université Grenoble Alpes (UGA)

Subjects
Hardware_MEMORYSTRUCTURES, PACS 85.42, [SPI.NANO] Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics
Abstract

International audience; The technology evolution addresses the demand for faster computers. Despite the achieved speed-up in terms of memory and computation performances, the communication between the memories and the processor remains a bottleneck of today’s computers. The Computation in Memory (CiM) paradigm aims at solving this problem by moving the computation directly inside the memory, eliminating thus the need for data transfer between memory and processor. Among the available CiM implementations, this study focuses on the Logic-in-Memory (LiM) solutions, i.e., digital operations to accelerate Boolean Logic. This work provides a comparison among the most prominent LiM solutions in terms of required memory resources (i.e., number of memristors) and number of operations.

Published
2021

52. Local Clock Glitching Fault Injection with Application to the ASCON Cipher

Author

Paolo Maistri, Sriram Sankaran, G Surya, Amrita Center For Cyber Security Systems and Network (Amrita University), Architectures and Methods for Resilient Systems (AMfoRS ), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), and Université Grenoble Alpes (UGA)

Subjects
business.industry, Computer science, End user, Locality, 020206 networking & telecommunications, 02 engineering and technology, Digital clock manager, Fault injection, Fault (power engineering), ASCON, Cipher, fault injection attack, Embedded system, PACS 85.42, lightweight cryptography, 0202 electrical engineering, electronic engineering, information engineering, 020201 artificial intelligence & image processing, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, business, Field-programmable gate array, clock glitching, Throughput (business)
Abstract

International audience; Lightweight ciphers such as ASCON facilitate ease of implementation as well as provide better performance over conventional ciphers, thus making it suitable for resource-constrained devices. However, hardware implementations of these ciphers are vulnerable to a multitude of physical attacks (such as fault injections) requiring dedicated countermeasures thus causing a negative impact on security, performance and power consumption. Modeling and understanding the impact of these attacks on cipher operations and end users is mandatory. Further, detection and mitigation of such fault injection attacks is challenging due to the interconnected nature of cipher design, coupled with the varying number of possible design choices and with the forced trade-offs that need to be done in order to implement expensive countermeasures at the lowest possible cost. In this work, we aim to model a fault injection attack on ASCON and analyze its impact on FPGA. In particular, we implement the ASCON cipher and propose a methodology for fault injection attacks using synchronous clock glitching by Digital Clock Manager (DCM) introducing a novel approach of locality, which can be exploited to emulate general delay faults on focused parts of the design, such those induced by pulsed EM injections.

Published
2020

53. Assessment of Machine Learning Algorithms for Near-Sensor Computing Under Radiation Soft Errors

Author

M. Garay Trindade, Rafael Garibotti, Luciano Ost, M. Letiche, R. Possamai Bastos, J. Beaucour, Architectures and Methods for Resilient Systems (AMfoRS ), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), Pontifícia Universidade Católica do Rio Grande do Sul [Porto Alegre] (PUCRS), Loughborough University, Institut Laue-Langevin (ILL), ILL, This work has been partially supported by: IRT Na- noelec (ANR-10-AIRT-05) and LabEx PERSYVAL-Lab (ANR-11-LABX-0025-01), both funded by the French government program 'Investissement d’avenir', and MultiRad project funded by Région Auvergne-Rhône-Alpes’s international ambition pack., Partly supported by Persyval project ANR-11-LABX-0025-01 and by MultiRad project (évaluation des effets des radiations cosmiques dans des systèmes informatiques multi-coeurs d'applications critiques) funded by Région Rhône-Alpes's international Ambition Pack, and ANR-11-LABX-0025,PERSYVAL-lab,Systemes et Algorithmes Pervasifs au confluent des mondes physique et numérique(2011)

Subjects
Complex data type, 021103 operations research, 010308 nuclear & particles physics, business.industry, 0211 other engineering and technologies, Automotive industry, Cloud computing, 02 engineering and technology, Fault injection, Radiation, Machine learning, computer.software_genre, 01 natural sciences, Upset, Support vector machine, PACS 85.42, 0103 physical sciences, Artificial intelligence, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Aerospace, business, computer, Algorithm, ComputingMilieux_MISCELLANEOUS
Abstract

International audience; Machine learning (ML) algorithms have been regaining momentum thanks to their ability to analyze substantial and complex data, supporting artificial intelligence decisions in cloud computing but also in near-sensor computing in endpoint devices. Both cloud and near-sensor computing are liable to radiationinduced soft errors, especially in automotive and aerospace safety-critical applications. In this regard, this paper contributes by comparing the accuracy of tw o prominent machine learning algorithms running on a lowpow er processor upset by radiation-induced soft errors. Both ML algorithms have been assessed w ith the help of a fault injectionbased method able to natively emulate soft errors directly in a development board. In addition, neutron radiation test results suggest the most critical situations in w hich mitigation solutions should address.

Published
2020

54. Analog and Mixed Signal Diagnosis Flow Using Fault Isolation Techniques and Simulation

Author

Tommaso Melis, Emmanuel Simeu, Etienne Auvray, STMicroelectronics [Grenoble] (ST-GRENOBLE), Reliable RF and Mixed-signal Systems (RMS ), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), and BEN TITO, Laurence

Subjects
diagnosis, Computer science, [SPI.NANO] Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, customer return, Mixed-signal integrated circuit, Fault detection and isolation, Flow (mathematics), Control theory, PACS 85.42, SoC, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, fault simulation, ComputingMilieux_MISCELLANEOUS, emission microscopy
Abstract

Getting accurate fault isolation during failure analysis is mandatory for success of Physical Failure Analysis (PFA) in critical applications. Unfortunately, achieving such accuracy is becoming more and more difficult with today’s diagnosis tools and actual process node such as BCD9 and FinFET 7 nm, compromising the success of subsequent PFA done on defective SoCs. Electrical simulation is used to reproduce emission microscopy, in our previous work and, in this paper, we demonstrate the possibility of using fault simulation tools with the results of electrical test and fault isolation techniques to provide diagnosis with accurate candidates for physical analysis. The experimental results of the presented flow, from several cases of application, show the validity of this approach.

Published
2020

55. A Non-Closed-Form Mathematical Model for Uniform and Non-Uniform Distributed Amplifiers

Author

Antonio Augusto Lisboa de Souza, Manuel J. Barragan, Sylvain Bourdel, Florence Podevin, Mohamad El Chaar, Laboratoire de Radio-Fréquence et d'Intégration de Circuits (RFIC-Lab ), Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Université Grenoble Alpes (UGA), Reliable RF and Mixed-signal Systems (RMS ), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), and Université Grenoble Alpes (UGA)

Subjects
computational modeling, bandwidth, Power gain, Computer science, 020208 electrical & electronic engineering, Bandwidth (signal processing), Semiconductor device modeling, Distributed amplifier, distributed amplifier, analytical model, 020206 networking & telecommunications, Context (language use), gain, 02 engineering and technology, BiCMOS, Artificial transmission line, CMOS, PACS 85.42, 0202 electrical engineering, electronic engineering, information engineering, Electronic engineering, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, semiconductor device modeling, mathematical model
Abstract

International audience; A non-closed-form general mathematical model for CMOS distributed amplifier (DA) for broadband applications is presented. Contrary to the artificial transmission line (TL) assumption made in the conventional analytical models, the proposed model treats the DA as a discrete set of cells connected together, and hence considers propagation and mismatch between inter-cells. This approach provides designers with a much more accurate first sizing of the DA compared to conventional ways and, as a result, leads to a reduced design time and complexity. The model enables both quantitative and qualitative analysis of a DA, for the purpose of aiding the designers in predicting the relations between DA performance and its multi-design parameters, especially in the context of non-uniform designs. In addition, it is well suited to Computer-Automated Design (CAutoD), to help in achieving designs having a given set of performance goals. The validation of the model is demonstrated on two designs, by a comparison with simulations done in Keysight's ADS tool and using STMicroelectronics' 55-nm SiGe BiCMOS design kit. First design is inspired from an already published non-uniform DA design while second one proposes a 100-GHz bandwidth CMOS uniform DA with 8 dB of power gain, after using it in a CAutoD process.

Published
2020

56. Miniaturization of Transmission Lines: Meandered Slow-wave CPWs

Author

Tadeu Mota-Frutuoso, Emmanuel Pistono, Manuel J. Barragan, Christophe Gaquiere, Marc Margalef-Rovira, Philippe Ferrari, Loic Vincent, Abdelhalim A. Saadi, Laboratoire de Radio-Fréquence et d'Intégration de Circuits (RFIC-Lab ), Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Université Grenoble Alpes (UGA), Centre Interuniversitaire de Micro-Electronique (CIME), Institut National Polytechnique de Grenoble (INPG), Reliable RF and Mixed-signal Systems (TIMA-RMS), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 (IEMN), Centrale Lille-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-JUNIA (JUNIA), Université catholique de Lille (UCL)-Université catholique de Lille (UCL), Puissance - IEMN (PUISSANCE - IEMN), Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF), This work has been funded by the European Union (ECSEL JU GA 737454: TowARds Advanced BiCMOS NanoTechnology platforms for RF applicatiOns -Taranto), and the General Directorate for Enterprises (DGE) in France., European Project: 737454,H2020,H2020-ECSEL-2016-1-RIA-two-stage,TARANTO(2017), and Reliable RF and Mixed-signal Systems (RMS )

Subjects
010302 applied physics, Materials science, business.industry, CPW, 020206 networking & telecommunications, Ranging, transmission line, 02 engineering and technology, Dielectric, 01 natural sciences, Microstrip, Electric power transmission, CMOS, Transmission line, Q factor, PACS 85.42, 0103 physical sciences, mm-wave, 0202 electrical engineering, electronic engineering, information engineering, Miniaturization, Optoelectronics, slow-wave, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, business
Abstract

International audience; This work presents novel transmission line structures based on Meandered Slow-wave CoPlanar Waveguides (MS-CPWs), aiming to achieve high miniaturization. As a proof-of-concept, these two kinds of transmission lines were designed and fabricated in the AMS 0.35 mu m CMOS technology together with classical straight and meandered microstrip lines. Measurement results from 70 kHz to 100 GHz of the fabricated transmission lines are presented. At 80 GHz, all the considered transmission lines present similar quality factors, ranging between 10 and 14. On the other hand, at this frequency, one of the developed MS-CPW presents an effective dielectric constant of 88, while the meandered microstrip exhibits an equivalent effective dielectric constant of 51, thus leading to higher compactness for the MS-CPW.

Published
2020

57. At-speed DfT Architecture for Bundled-data Design

Author

Ricardo Aquino Guazzelli, Laurent Fesquet, Circuits, Devices and System Integration (CDSI), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), and Université Grenoble Alpes (UGA)

Subjects
010302 applied physics, Correctness, Computer science, Design for testing, Circuit design, design for testability, 02 engineering and technology, 01 natural sciences, 020202 computer hardware & architecture, Controllability, CMOS, Computer engineering, Asynchronous communication, PACS 85.42, 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, asynchronous circuit, Electronic circuit, Voltage
Abstract

International audience; At-speed testing for asynchronous circuits is still an open concern in the literature. Due to its timing constraints between control and data paths, Design for Testability (DfT) methodologies must test both control and data paths at the same time in order to guarantee the circuit correctness. As Process Voltage Temperature (PVT) variations significantly impact circuit design in newer CMOS technologies and low-power techniques such as voltage scaling, the timing constraints between control and data paths must be tested after fabrication not only under nominal conditions but through a range of operating conditions. However, this requirement demands modifications in the control and data paths, which are not straightforward and not desirable from a commercial standpoint due to its incompatibility with conventional testing tools. Even with the available testing methodologies for asynchronous circuits in the literature - by adapting the existing techniques for synchronous or creating new ones from scratch - those methodologies usually target the control or data path. This work explores an at-speed testing approach for bundled data circuits, targeting the micropipeline template. The main target of this test approach focuses on whether the sized delay lines in control paths respect the local timing assumptions of the data paths. By adding extra controllability points in the controllers and taking advantage of scan-chain structures, this work targets to generate/stall tokens in controllers, enabling circuit verification through available scan chains.

Published
2020

58. VP Float: First Class Treatment for Variable Precision Floating Point Arithmetic

Author

Tiago Trevisan Jost, Christian Fabre, Albert Cohen, Yves Durand, Frédéric Pétrot, Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), System Level Synthesis (TIMA-SLS), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), Google Inc [Mountain View], Research at Google, ANR-18-CE46-0011,ImPreNum,Améliorer la prédictibilité des calculs numériques(2018), and System Level Synthesis (SLS )

Subjects
Coprocessor, Floating point, business.industry, Computer science, Interface (computing), variable precision arithmetic, Optimizing compiler, 010103 numerical & computational mathematics, Parallel computing, Supercomputer, computer.software_genre, 01 natural sciences, MPFR, [INFO.INFO-CR]Computer Science [cs]/Cryptography and Security [cs.CR], Software, Memory management, LLVM, PACS 85.42, compilation, Compiler, Floating point arithmetic, 0101 mathematics, business, computer, compiler optimization
Abstract

International audience; Optimizing compilers for high performance computing only support IEEE 754 floating-point (FP) types and applications needing higher precision involve cumbersome memory management and calls to external libraries. We introduce an extension of the C type system to represent variable-precision FP arithmetic, supporting both static and dynamically variable precision. We design and implement a compilation flow bridging the abstraction gap between this type system and hardware FP instructions or software libraries. We demonstrate the effectiveness of our solution by enabling the full range of LLVM optimizations and leveraging two backend code generators: one for the ISA of a variable precision FP arithmetic coprocessor, and one for the MPFR multi-precision FP library. Both targets support the static and dynamically adaptable precision of our type system. On the PolyBench suite, our optimizing compilation flow targeting MPFR is shown to outperform the Boost programming interface for the MPFR library. CCS CONCEPTS • Software and its engineering → Source code generation; Imperative languages; Data types and structures; Dynamic compilers.

Published
2020

59. Analog and mixed-signal circuits simulation for product level EMMI analysis

Author

Paul Armagnat, Tommaso Melis, Etienne Auvray, Emmanuel Simeu, STMicroelectronics [Grenoble] (ST-GRENOBLE), Reliable RF and Mixed-signal Systems (RMS ), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), and BEN TITO, Laurence

Subjects
Computer science, [SPI.NANO] Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, 02 engineering and technology, Fault (power engineering), 01 natural sciences, law.invention, law, 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, Electronic engineering, Electrical and Electronic Engineering, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Safety, Risk, Reliability and Quality, ComputingMilieux_MISCELLANEOUS, Electronic circuit, 010302 applied physics, 020208 electrical & electronic engineering, Transistor, Process (computing), Mixed-signal integrated circuit, Replicate, Condensed Matter Physics, Atomic and Molecular Physics, and Optics, Surfaces, Coatings and Films, Electronic, Optical and Magnetic Materials, PACS 8542, Product (mathematics), PACS 85.42, Mixed signal simulation
Abstract

International audience; The goal of this work is to propose a new flow that integrates the analog and mixed signal simulation of the circuits to replicate the EMMI signals. This supports the fault localization process. We explore the emission typologies of the transistors, focusing the attention on the DMOS structure. First experimental results show the benefits of this approach.

Published
2020

60. Arbiterless Event-Based Imager Architecture with temporal and spatial redundancies suppression

Author

Laurent Fesquet, Nils Margotat, Mohamed Akrarai, Gilles Sicard, Circuits, Devices and System Integration (TIMA-CDSI), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), European Project: 783127,H2020-EU.2.1.1.7. - ECSEL,OCEAN12(2018), BEN TITO, Laurence, Opportunity to Carry European Autonomous driviNg further with FDSOI technology up to 12nm node - OCEAN12 - 2018-04-01 - 2021-12-31 - 783127 - VALID, and Circuits, Devices and System Integration (CDSI)

Subjects
Pixel, arbiterless image sensor, Event (computing), Computer science, business.industry, [SPI.NANO] Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, 020208 electrical & electronic engineering, ComputingMethodologies_IMAGEPROCESSINGANDCOMPUTERVISION, 02 engineering and technology, frameless image sensor, Luminance, Kernel (image processing), PACS 85.42, 0202 electrical engineering, electronic engineering, information engineering, Redundancy (engineering), Computer vision, temporal and spatial redundancies suppression, Artificial intelligence, Image sensor, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, business, Throughput (business), Energy (signal processing)
Abstract

International audience; We present a new image sensor architecture that manages spatial and temporal redundancies with an arbiterless readout and a pixel Address-Event Representation (AER) reading system. This frameless image sensor only generates few events over time in order to target an efficient power consumption compared to the commercial CMOS image sensors. Indeed, this image sensor does not generate anymore frames but events only when a change appears in the scene. Moreover, the event throughput depends on the luminance variations of the recorded scene. This means that more activity in the scene will generate more events and vice versa. Collecting events over a period of time will define an image. It is noticeable that, at each instant, the generated events characterize the zone of interest (the active area) of the scene. Consequently, processing such images should require less computing, communication and energy.

Published
2020

61. An Effective QRS Selection Based on the Level-Crossing Sampling and Activity Selection

Author

Qaisar, S.-M., Fesquet, Laurent, University of Jeddah, Circuits, Devices and System Integration (CDSI), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), and BEN TITO, Laurence

Subjects
activity selection, [SPI.NANO] Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, PACS 85.42, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, electrocardiogram (ECG), level-crossing sampling scheme
Abstract

International audience; The Internet of Things (IoT) healthcare framework is a new trend. In this context, biomedical wearable devices are linked to the cloud. This work contributes to the development of efficient Electrocardiogram (ECG) wearables by redesigning their signal processing chain. The emphasis is on developing a system for effective and precise QRS selection. QRS complexes of heartbeats contain most important arrhythmia related information. The proposed system uses an analog band-pass filter to reduce the impact of Baseline Wander (BW) and aliasing. The band-limited signal is then digitized by using a 5-Bit resolution level-crossing A/D converter. Onward, an original activity selection algorithm is used for an effective selection of the QRS complexes. Results show that the proposed solution attains an average QRS detection sensitivity of 98.4% and positive predictive value of 100% while securing on average 4.77-fold and 2.1-fold compression gains respectively in terms of count of data samples and bits over the classical counterparts.

Published
2020

62. Study of Inter-Power Domain Failures during a CDM Event

Author

Troussier, Chloé, Bourgeat, Johan, Simeu, Emmanuel, Arnould, Jean-Daniel, Jimenez, J., Jacquier, B., STMicroelectronics [Crolles] (ST-CROLLES), Reliable RF and Mixed-signal Systems (RMS ), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), Laboratoire de Radio-Fréquence et d'Intégration de Circuits (RFIC-Lab ), Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), and Université Grenoble Alpes (UGA)-Université Grenoble Alpes (UGA)

Subjects
PACS 85.42, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, ComputingMilieux_MISCELLANEOUS
Abstract

International audience

Published
2020

63. From 1.8V to 0.19V voltage bias on analog spiking neuron in 28nm UTBB FD-SOI technology

Author

Ph. Galy, Lorena Anghel, V. Cincon, Elena Ioana Vatajelu, STMicroelectronics [Crolles] (ST-CROLLES), Architectures and Methods for Resilient Systems (AMfoRS ), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), SPINtronique et TEchnologie des Composants (SPINTEC), Centre National de la Recherche Scientifique (CNRS)-Institut de Recherche Interdisciplinaire de Grenoble (IRIG), Direction de Recherche Fondamentale (CEA) (DRF (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Direction de Recherche Fondamentale (CEA) (DRF (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Université Grenoble Alpes (UGA), ANR-19-P3IA-0003,MIAI,MIAI @ Grenoble Alpes(2019), Architectures and Methods for Resilient Systems (TIMA-AMfoRS ), BEN TITO, Laurence, and MIAI @ Grenoble Alpes - - MIAI2019 - ANR-19-P3IA-0003 - P3IA - VALID

Subjects
Spiking neural network, low power, Computer science, [SPI.NANO] Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, 020208 electrical & electronic engineering, Transistor, Spice, artificial neuron, Silicon on insulator, 02 engineering and technology, 021001 nanoscience & nanotechnology, law.invention, spiking neural network, CMOS, Neuromorphic engineering, law, PACS 85.42, 0202 electrical engineering, electronic engineering, information engineering, Electronic engineering, Artificial neuron, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, 0210 nano-technology, Voltage
Abstract

International audience; The emergence of new hardware-oriented algorithms for convolutional neural networks (CNNs) or spiking neural networks (SNNs) used for efficient data interpretation, made neuromorphic computing a very promising solution. SNNs are very attractive due to their particularly low power consumption. This paper presents a comprehensive analysis of an analog spiking neuron designed in 28 nm UTBB FD-SOI CMOS technology from STMicroelectronics. Thick oxide MOS transistors with regular VT are selected to perform a low power design enhanced by using sub-threshold bias. The neuron operation is presented and analyzed through SPICE simulations performed at 0.7 V nominal voltage bias. Several parameters control the shape of the neuron response, such as: the synaptic excitation, the spike duration, and the refractory period. The neuron under study was fabricated and characterized for bias voltages ranging from 1.8 V standard bias to the measured limit of 0.19 V. The full functionality of the analog spiking neuron in FD-SOI is demonstrated.

Published
2020

64. A Comprehensive End-to-end Solution for a Secure and Dynamic Mixed-signal 1687 System

Author

Michele Portolan, Ghislain Takam Tchendjou, Vincent Reynaud, Salvador Mir, Paolo Maistri, Emmanuel Simeu, Manuel J. Barragan, Regis Leveugle, Kalpana Senthamarai Kannan, Lorena Anghel, Renato S. Feitoza, Architectures and Methods for Resilient Systems (TIMA-AMfoRS ), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), Reliable RF and Mixed-signal Systems (TIMA-RMS), SPINtronique et TEchnologie des Composants (SPINTEC), Centre National de la Recherche Scientifique (CNRS)-Institut de Recherche Interdisciplinaire de Grenoble (IRIG), Direction de Recherche Fondamentale (CEA) (DRF (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Direction de Recherche Fondamentale (CEA) (DRF (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Université Grenoble Alpes (UGA), European Project: 172930120,PENTA,RECHADESTIMD,HADES(2017), Architectures and Methods for Resilient Systems (AMfoRS ), and Reliable RF and Mixed-signal Systems (RMS )

Subjects
010302 applied physics, Authentication, business.industry, Computer science, circuit-aging, Circuit Aging, Mixed signal testing, Embedded Test Instruments, Mixed-signal integrated circuit, 02 engineering and technology, ADCs, 01 natural sciences, automated test environment, 020202 computer hardware & architecture, Secure Access, Software, End-to-end principle, Embedded system, mixed-signal testing, Automated Test Environments, PACS 85.42, 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, business
Abstract

International audience; The disruptive potential of the IEEE 1687 standard does not come from a single innovation, but rather from its capacity of providing a unified framework where heterogeneous approaches can co-exist and interact. In this Special Session, we will present the complementary research activities performed in the TIMA laboratory covering different aspects of the standard (Mixed-Signal instrument testing, Embedded Aging Monitors and Test Access Securization), and their coordination thanks to the Manager-for SoC Test (MAST) software environment.

Published
2020

65. Automatic Fault Simulators for Diagnosis of Analog Systems

Author

Etienne Auvray, Emmanuel Simeu, Tommaso Melis, STMicroelectronics [Grenoble] (ST-GRENOBLE), Reliable RF and Mixed-signal Systems (RMS ), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), and BEN TITO, Laurence

Subjects
analog circuits, Speedup, Computer science, diagnosis, [SPI.NANO] Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Hardware_PERFORMANCEANDRELIABILITY, 02 engineering and technology, fault isolation, Fault (power engineering), Fault detection and isolation, 03 medical and health sciences, 0302 clinical medicine, Software, 0202 electrical engineering, electronic engineering, information engineering, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, fault simulation, ComputingMilieux_MISCELLANEOUS, Electronic circuit, Analogue electronics, business.industry, 020208 electrical & electronic engineering, Process (computing), Mixed-signal integrated circuit, mixed-signal circuits, failure analysis, PACS 85.42, business, 030217 neurology & neurosurgery, Computer hardware
Abstract

The failure analysis in analog and mixed signal products is mainly based on measurements performed in the laboratory without any simulation support. The fault simulators for analog circuits are starting to be available but are not designed for these needs. This work describes the integration of the simulation into the normal failure analysis flow using test software developed for analog fault simulation. We propose an innovative iterative flow for diagnosis of analog IPs and products. The results show how inserting such tools in the fault isolation step, we speed up the whole analysis process, allowing the diagnosis for analog and mixed-signal circuits

Published
2020

66. From High-Level Synthesis to Bundled-Data Circuits

Author

Yoan Decoudu, Katell Morin-Allory, Laurent Fesquet, Jean Simatic, Circuits, Devices and System Integration (TIMA-CDSI), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), HawAI.tech, European Project: 783127,H2020-EU.2.1.1.7. - ECSEL,OCEAN12(2018), Circuits, Devices and System Integration (CDSI), and HawAI.Tech

Subjects
Finite-state machine, Computer science, business.industry, circuit desynchronization, Process (computing), 020206 networking & telecommunications, 02 engineering and technology, 020202 computer hardware & architecture, Embedded system, High-level synthesis, PACS 85.42, high-level synthesis, 0202 electrical engineering, electronic engineering, information engineering, bundled-data circuit, Catapult, Relevance (information retrieval), Graphics, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, business, asynchronous circuit, Hardware_REGISTER-TRANSFER-LEVELIMPLEMENTATION, ComputingMilieux_MISCELLANEOUS, Hardware_LOGICDESIGN, Asynchronous circuit, Electronic circuit
Abstract

In order to spread asynchronous circuit design to a large community of designers, High-Level Synthesis (HLS) is promising option because it requires limited technical skills. Common HLS operations quickly provide a synchronous RTL description, which is usually split in two parts: a data-path and a control-path. In order to desynchronize such a circuit, the desynchronization process is only applied to the control-path, which is no more than a Finite State Machine (FSM). Our approach helps designers for quickly designing data-driven circuits while maintaining a reasonable cost, a similar area and a short time-to-market. To demonstrate our technique, the HLS tool, Catapult HLS from Mentor Graphics, has been used. Once the control-path has been extracted, the corresponding FSM is simply analyzed and desynchronized. On the other hand, the data-path is kept as it is. The resulting circuit is a bundled-data circuit requiring a particularly low design effort. Some samples illustrate the method and show its relevance in terms of area and performance.

Published
2020

67. Cascaded tunable distributed amplifiers for serial optical links: Some design rules

Author

Florence Podevin, A. Lisboa-de-Souza, M. El-Chaar, T. Capelli Mouvand, Sylvain Bourdel, I. Alaji, Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 (IEMN), Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF), Laboratoire de l'intégration, du matériau au système (IMS), Université Sciences et Technologies - Bordeaux 1-Institut Polytechnique de Bordeaux-Centre National de la Recherche Scientifique (CNRS), Laboratoire de Radio-Fréquence et d'Intégration de Circuits (RFIC-Lab ), Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Université Grenoble Alpes (UGA), Universidade Federal da Paraiba (UFPB), and Université Sciences et Technologies - Bordeaux 1 (UB)-Institut Polytechnique de Bordeaux-Centre National de la Recherche Scientifique (CNRS)

Subjects
bandwidth, power demand, Computer science, distributed amplifier, 02 engineering and technology, gain, law.invention, [SPI]Engineering Sciences [physics], law, design methodology, 0202 electrical engineering, electronic engineering, information engineering, Electronic engineering, Hardware_INTEGRATEDCIRCUITS, Microelectronics, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Design methods, Electronic circuit, business.industry, Transistor, Bandwidth (signal processing), Distributed amplifier, 020206 networking & telecommunications, CMOS, Logic gate, PACS 85.42, logic gates, transistor, business
Abstract

International audience; In the framework of circuits for 5G, this paper presents an innovative power efficient method to design cascaded distributed amplifiers. Validation is achieved with a 55-nm CMOS technology by ST -Microelectronics developed for the mm-wave range. Several rules are specified for analysis and design of an optimum structure, making the part between the number of trans conductances to be distributed and the number of distributed stages to be cascaded. Attention is also paid to the trade-off between power consumption and tunability. The Cadence Virtuoso tool is used to simulate the design which shows a targeted gain of 20 dB±0.8 dB over a bandwidth of 120 GHz with a power consumption of 174mW and an estimated area of 0.3 mm 2 .

Published
2020

68. Improved Pi-Delayed Harmonic Rejection N-Path Mixer for Low Power Consumption and Multistandard Receiver

Author

Florence Podevin, Estelle Lauga-Larroze, S. Ibrahim, Laurent Fesquet, A. Al Shakoush, Sylvain Bourdel, Laboratoire de Radio-Fréquence et d'Intégration de Circuits (RFIC-Lab ), Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Université Grenoble Alpes (UGA), Circuits, Devices and System Integration (TIMA-CDSI), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), European Project: 783127,H2020-EU.2.1.1.7. - ECSEL,OCEAN12(2018), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Université Grenoble Alpes (UGA)-Université Grenoble Alpes (UGA), and Circuits, Devices and System Integration (CDSI)

Subjects
Differential gain, Computer science, Amplifier, HR-NPM architecture, 020208 electrical & electronic engineering, Context (language use), 02 engineering and technology, Software-defined radio, Network topology, Harmonic rejection, improved Pi-delayed harmonic rejection, PACS 85.42, Path (graph theory), 0202 electrical engineering, electronic engineering, information engineering, Harmonic, Electronic engineering, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, harmonics suppression, ComputingMilieux_MISCELLANEOUS
Abstract

The purpose of this paper is to study the complexity of the Harmonic Rejection N-Path Mixer HRNPM based receivers. In this framework, a HR-NPM architecture has been discussed based on the π-delayed driving signals. The harmonic rejection and the system complexity have been improved with this new architecture such that the Harmonic rejection achieved by this structure is the same of the conventional HR-2NPM and the system complexity has been reduced by half, where as the number of the gain stages and the switches has been reduced. In this context, a 5-path mixer is thus proposed. It allows rejecting up to the 8th harmonic with only 2 differential gain stages by appropriately implementing the switches whereas only the 6th harmonic would be rejected with conventional HR-8PM topologies having 3 amplifier stages. Our structure shows high resilience to clocks overlapping effects.

Published
2020

69. A Novel Event Based Image Sensor with Spatial and Temporal Redundancy Suppression

Author

Akrarai, Mohamed, Margotat, N., Sicard, G., Fesquet, Laurent, Circuits, Devices and System Integration (CDSI), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), European Project: 783127,H2020-EU.2.1.1.7. - ECSEL,OCEAN12(2018), Circuits, Devices and System Integration (TIMA-CDSI), BEN TITO, Laurence, and Opportunity to Carry European Autonomous driviNg further with FDSOI technology up to 12nm node - OCEAN12 - 2018-04-01 - 2021-12-31 - 783127 - VALID

Subjects
image sensor architecture, [SPI.NANO] Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, PACS 85.42, frameless image sensor, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, ComputingMilieux_MISCELLANEOUS
Abstract

International audience

Published
2020

70. mm-Wave Through-Load Switch for in-situ Vector Network Analyzer on a 55-nm BiCMOS Technology

Author

Christophe Gaquiere, Abdelhalim A. Saadi, Philippe Ferrari, Manuel J. Barragan, Sylvain Bourdel, Emmanuel Pistono, Marc Margalef-Rovira, Reliable RF and Mixed-signal Systems (RMS ), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), Laboratoire de Radio-Fréquence et d'Intégration de Circuits (RFIC-Lab ), Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Université Grenoble Alpes (UGA), Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 (IEMN), Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF), Puissance - IEMN (PUISSANCE - IEMN), Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF), European Project: 737454,H2020,H2020-ECSEL-2016-1-RIA-two-stage,TARANTO(2017), Reliable RF and Mixed-signal Systems (TIMA-RMS), and Laboratoire commun STMicroelectronics-IEMN T1

Subjects
Materials science, 02 engineering and technology, Hardware_PERFORMANCEANDRELIABILITY, 7. Clean energy, law.invention, law, 3-dB slow-wave coupler, in-situ reflectometer, mm-wave, 0202 electrical engineering, electronic engineering, information engineering, Hardware_INTEGRATEDCIRCUITS, Insertion loss, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, NMOS logic, Load control switch, business.industry, 020208 electrical & electronic engineering, Bandwidth (signal processing), Transistor, 020206 networking & telecommunications, Biasing, switch, PACS 85.42, Power dividers and directional couplers, Optoelectronics, business, on-wafer calibration, Voltage
Abstract

International audience; In this paper, an innovative millimeter-wave (mm-wave) through-load switch for in-situ reflectometers and on-wafer calibration is proposed. This two-port device can switch between two states: (i) a through connection or (ii) a 50 Ω load for both of its ports. The through-load switch is composed of a 3-dB directional coupler and two nMOS transistors controlled through a biasing voltage applied to their gate. Measurement results of a 120-GHz 3-dB directional coupler are provided up to 145 GHz together with EM simulations and circuit-level simulations up to 220 GHz of the through-load switch. A wide bandwidth is obtained, from 73 GHz to 179 GHz, with limited insertion loss of 2 dB.

Published
2020

71. Static linearity BIST for Vcm-based switching SAR ADCs using a reduced-code measurement technique

Author

Antonio Gines, Renato S. Feitoza, Manuel J. Barragan, Salvador Mir, Reliable RF and Mixed-signal Systems (RMS ), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), Instituto de Microelectrónica de Sevilla (IMSE-CNM), Universidad de Sevilla-Centro Nacional de Microelectronica [Spain] (CNM)-Consejo Superior de Investigaciones Científicas [Madrid] (CSIC), European Project: 172930120,PENTA,RECHADESTIMD,HADES(2017), Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo, Reliable RF and Mixed-signal Systems (TIMA-RMS), and Universidad de Sevilla / University of Sevilla-Centro Nacional de Microelectronica [Spain] (CNM)-Consejo Superior de Investigaciones Científicas [Madrid] (CSIC)

Subjects
Computer science, Transistor, Linearity, Successive approximation ADC, Topology (electrical circuits), 02 engineering and technology, Converters, 020202 computer hardware & architecture, law.invention, Linearity test, law, PACS 85.42, 0202 electrical engineering, electronic engineering, information engineering, Electronic engineering, Code (cryptography), Hardware_INTEGRATEDCIRCUITS, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Linearity testing
Abstract

International audience; This work presents a reduced-code strategy for the static linearity self-testing of Vcm-based successive-approximation analog to digital converters (SAR ADCs). These techniques take advantage of the repetitive operation of SAR ADCs for reducing the number of necessary measurements for static linearity testing. In this paper we discuss the application of these techniques for the Vcm-based SAR ADC topology and present a practical BIST implementation based on an embedded incremental ADC. Electrical simulation results at transistor level are presented to validate the feasibility of the proposed on-chip reduced-code static linearity test.

Published
2020

72. System and Method for Managing Requests in an Asynchronous Pipeline

Author

Engels, Sylvain, Fesquet, Laurent, Germain, Sophie, Circuits, Devices and System Integration (CDSI), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), and BEN TITO, Laurence

Subjects
[SPI.NANO] Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, PACS 85.42, Hardware_ARITHMETICANDLOGICSTRUCTURES, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Hardware_LOGICDESIGN
Abstract

An asynchronous pipeline circuit includes: a first processing stage including a first data latch configured to generate a request signal; a second processing stage downstream the first processing stage and including a second data latch; and a programmable delay line coupled between the first data latch and the second processing stage. The programmable delay line is configured to receive the request signal from the first data latch and to generate a delayed request signal by randomly delaying the request signal on each data transfer from the first data latch to the second data latch.

Published
2020

73. Nonlinear Codes for Control Flow Checking

Author

Osnat Keren, Giorgio Di Natale, Architectures and Methods for Resilient Systems (AMfoRS ), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), Faculty of Engineering [Israel], and Bar-Ilan University [Israël]

Subjects
010302 applied physics, Instruction stream, business.industry, Computer science, 02 engineering and technology, 01 natural sciences, 020202 computer hardware & architecture, Nonlinear system, Control flow, PACS 85.42, 0103 physical sciences, Basic block, 0202 electrical engineering, electronic engineering, information engineering, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, business, Encoder, Computer hardware
Abstract

International audience; A hardware-based control flow monitoring technique enables to detect both errors in the control flow and the instruction stream being executed on a processor. However, as was shown in recent papers, these techniques fail to detect malicious carefully-tuned manipulation of the instruction stream in a basic block. This paper presents a non-linear encoder and checker that can cope with this weakness.

Published
2020

74. On-chip reduced-code static linearity test of Vcm -based switching SAR ADCs using an incremental analog-to-digital converter

Author

Renato S. Feitoza, Antonio Gines, Manuel J. Barragan, Salvador Mir, Reliable RF and Mixed-signal Systems (TIMA-RMS), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), Instituto de Microelectrónica de Sevilla (IMSE-CNM), Universidad de Sevilla / University of Sevilla-Centro Nacional de Microelectronica [Spain] (CNM)-Consejo Superior de Investigaciones Científicas [Madrid] (CSIC), European Project: 172930120,PENTA,RECHADESTIMD,HADES(2017), Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo, Reliable RF and Mixed-signal Systems (RMS ), and Universidad de Sevilla-Centro Nacional de Microelectronica [Spain] (CNM)-Consejo Superior de Investigaciones Científicas [Madrid] (CSIC)

Subjects
Computer science, 020208 electrical & electronic engineering, Analog-to-digital converter, Successive approximation ADC, Topology (electrical circuits), 02 engineering and technology, Hardware_PERFORMANCEANDRELIABILITY, Converters, 020202 computer hardware & architecture, law.invention, Linearity test, law, PACS 85.42, 0202 electrical engineering, electronic engineering, information engineering, Electronic engineering, Code (cryptography), Hardware_INTEGRATEDCIRCUITS, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics
Abstract

International audience; This paper describes a BIST technique for the static linearity test of $V_{cm}$ -based successive-approximation analog-to-digital converters (SAR ADCs). We discuss the application of reduced-code techniques for the $V_{cm}$ -based SAR ADC topology and present a practical on-chip implementation based on an embedded incremental ADC. Simulation results are provided for validating the feasibility and performance of the proposed on-chip reduced-code static linearity test.

Published
2020

75. Implementation and Evaluation of a Hardware Decentralized Synchronization Lock for MPSoCs

Author

Maxime France-Pillois, Jérôme Martin, Frederic Rousseau, Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), System Level Synthesis (SLS ), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), System Level Synthesis (TIMA-SLS), and BEN TITO, Laurence

Subjects
systèmes multiprocesseur en grappe, Computer science, business.industry, synchronization lock, [SPI.NANO] Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, 020206 networking & telecommunications, 02 engineering and technology, verrou de synchronisation, MPSoC, Lock (computer science), Synchronization, 020202 computer hardware & architecture, Shared memory, PACS 85.42, Scalability, 0202 electrical engineering, electronic engineering, information engineering, Latency (engineering), [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, business, cluster based MPSoC, Computer hardware
Abstract

International audience; Each generation of shared memory Multi-Processor System-on-Chips (MPSoCs) tend to embed more and more computing units. The cores of modern MPSoCs are often grouped into clusters communicating with each other through Networks on Chip (NoCs). Having efficient scalable synchronization mechanisms is then mandatory to benefit from the high parallelism they offer.In this work we propose an innovative hardware support for synchronization locks. First of all, a non-intrusive measurement tool-chain allows us to prove a fundamental hypothesis as to optimization of the lock mechanism: although a lock may be used, at runtime, by various cores belonging to different clusters, it is often reused by the last core which has released it. Based on this observation, we provide a hardware decentralized solution to manage dynamic re-homing of locks in a dedicated memory, close to the latest access-granted core. This reduces overall access latency and network traffic in case of reuse of the lock within the same cluster.This paper presents our solution, called Lockality, and its performance evaluation on a characteristic MPSoC running on a hardware emulator. Experiments show large gains at low level (physical lock acquisition) as well as at the application level.

Published
2020

76. A Self-Timed Ring based PUF

Author

Abdelkarim Cherkaoui, Laurent Fesquet, Gregoire Gimenez, IC'ALPS (IC'ALPS), Circuits, Devices and System Integration (CDSI), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), and HawAI.Tech

Subjects
Ring (mathematics), Propagation time, Computer science, business.industry, 020208 electrical & electronic engineering, Physical unclonable function, 02 engineering and technology, Ring oscillator, Chip, PACS 85.42, physically unclonable function (PUF), Self-Timed-Rings (STR), 0202 electrical engineering, electronic engineering, information engineering, 020201 artificial intelligence & image processing, Uniqueness, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Field-programmable gate array, business, ComputingMilieux_MISCELLANEOUS, Randomness, Computer hardware
Abstract

A new type of physical unclonable function (PUF) is presented in this paper. It leverages the sub-gate-delay phase resolution of self-timed ring oscillators to efficiently extract the randomness due to the chip manufacturing process. The main advantage of the presented technique is its ability to fine tune the measurement resolution in order to find the best trade-off between the PUF stability and its uniqueness. We show that on-the-fly evaluation of the propagation time through delay elements can be achieved, enabling the extraction of a unique identifier per chip. This approach can efficiently replace the methods based on time-consuming frequency estimations. The first results, based on an FPGA implementation, are given. They show decent and configurable stability, uniqueness and randomness properties while outperforming the response latency of the traditional ring oscillator PUF.

Published
2020

77. FPU Bit-Width Optimization for Approximate Computing: A Non-Intrusive Approach

Author

Katell Morin-Allory, Noureddine Ait Said, Mounir Benabdenbi, Architectures and Methods for Resilient Systems (AMfoRS ), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), and Circuits, Devices and System Integration (CDSI)

Subjects
Source code, Computer science, media_common.quotation_subject, [INFO.INFO-OH]Computer Science [cs]/Other [cs.OH], floating-point unit, 02 engineering and technology, CPU-architecture, RISC-V ISA, Software, Arbitrary-precision arithmetic, word-length optimization, 0202 electrical engineering, electronic engineering, information engineering, Overhead (computing), dynamic binary translation, Real-time operating system, media_common, business.industry, transprecision computing, Floating-point unit, 020207 software engineering, computer.file_format, approximate computing, 020202 computer hardware & architecture, Computer engineering, PACS 85.42, Memory footprint, Executable, business, computer
Abstract

International audience; Floating-Point Units (FPUs) count as a significant part of computing resources in modern general-purpose and application-specific processors. Full-precision FPUs can be a source of extensive hardware overhead (power consumption, area, memory footprint etc.). On the other hand, several applications feature the inherent ability to tolerate precision loss. This has lead to the development of a new computing paradigm: Transprecision Computing (TC), where variable and arbitrary precision hardware FPUs have been introduced. Many tools and libraries have been proposed to simulate the effects of approximation on applications, to help designers to select the most optimized FPU architecture adequate for a given application. However, existing techniques require developers to rewrite part or all of their existing software stacks (applications, libraries, operating systems ...), which is often infeasible, complex or at least a very time-consuming development effort. This work proposes a non-intrusive approach, which does not need source code modification, by introducing approximations at the low-level in assembly. This allows approximating virtually all kinds of executable binaries (bare-metal applications, single- /multi-threaded user applications, OS/RTOS, etc.). We implement the approach on top of the well known QEMU dynamic binary translator. We perform experiments on a set of benchmarks from the literature, and we demonstrate how the approach further simplifies evaluating the impact of FP approximations on numerical applications outputs, without being intrusive to the source code.

Published
2020

78. Advanced on-chip test solutions for industrial mixed-signal/RF circuits

Author

Mir, S., Reliable Mixed-signal Systems [2020-….] (RMS [2020-….]), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés [2020-….] (TIMA [2020-….]), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2020-....] (UGA [2020-....])-Institut polytechnique de Grenoble - Grenoble Institute of Technology [2020-....] (Grenoble INP [2020-....]), Université Grenoble Alpes [2020-....] (UGA [2020-....])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2020-....] (UGA [2020-....])-Institut polytechnique de Grenoble - Grenoble Institute of Technology [2020-....] (Grenoble INP [2020-....]), Université Grenoble Alpes [2020-....] (UGA [2020-....]), and European Project: 172930120,PENTA,RECHADESTIMD,HADES(2017)

Subjects
PACS 85.42, Hardware_INTEGRATEDCIRCUITS, Hardware_PERFORMANCEANDRELIABILITY, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Design-for-Test (DfT), DfT
Abstract

International audience; This talk will describe on-chip test solutions for mixed-signal circuits that have been developed in the last years in the frame of joint development work between TIMA Laboratory and STMicroelectronics. These solutions that are today of industrial application are aimed at ADCs, PLLs and CMOS imagers. They all use fully or mostly digital test circuitry, making them highly portable across different technologies. We will also draw some recent work on on-chip test solutions for RF circuits.

Published
2020

79. Parametric faults detection and concealment on imager with FPGA implementation

Author

Ghislain Takam Tchendjou, Emmanuel Simeu, Reliable RF and Mixed-signal Systems (RMS ), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), and BEN TITO, Laurence

Subjects
Computational complexity theory, Computer science, [SPI.NANO] Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, ComputingMethodologies_IMAGEPROCESSINGANDCOMPUTERVISION, image quality assessment, parametric fault, 02 engineering and technology, 01 natural sciences, 010309 optics, Computer Science::Multimedia, 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, Median filter, Computer vision, Image sensor, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Field-programmable gate array, Parametric statistics, Block (data storage), defective pixel self-healing, image sensor, Pixel, business.industry, 020206 networking & telecommunications, Peak signal-to-noise ratio, FPGA implementation, Computer Science::Computer Vision and Pattern Recognition, PACS 85.42, Artificial intelligence, business
Abstract

International audience; This paper presents an online and integrated solution for self-healing of parametric faults on an image sensor. This self-healing is based on the detection and concealment of the parametric faults in the image sensor. Three detection methods are considered. The first one is based on the distance between the pixel under test and its neighboring pixels, the second method is based on the median of the block of pixels around the pixel under test, and the third method is based on the local dispersion parameters in the image. The concealment method is based on the median filter, which consists of the substitution of the defective value by the median value of the pixel block. The metrics used for comparison of the experimental results are phi-coefficient, peak signal to noise ratio (PSNR) and a full reference image quality assessment method based on machine learning techniques (FrIQA). The detection and concealment processes are implemented on an FPGA platform to evaluate the computational complexity and to confirm the feasibility of integrating the proposed solutions in an image sensor.

Published
2020

80. Accurate and Efficient Continuous Time and Discrete Events Simulation in SystemC

Author

Fernandez-Mesa, B.J., Andrade Porras, Liliana Lilibeth, Pétrot, Frédéric, Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA), System Level Synthesis (SLS ), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), and BEN TITO, Laurence

Subjects
[INFO.INFO-OH] Computer Science [cs]/Other [cs.OH], continuous time, SystemC-AMS, evenements discrets, discrete events, temps continu, PACS 85.42, [INFO.INFO-OH]Computer Science [cs]/Other [cs.OH], SystemC, simulation
Abstract

International audience; The AMS extensions of SystemC emerged to aid the virtual prototyping of continuous time and discrete event heterogeneous systems. Although useful for a large set of use cases, synchronization of both domains through a fixed timestep generates inaccuracies that cannot be overcome without penalizing simulation speed. We propose a direct, optimistic, and causal synchronization algorithm on top of the SystemC kernel that explicitly handles the rich set of interactions that occur in the domain interface. We test our algorithm with a complex nonlinear automotive use case and show that it breaks the described accuracy and efficiency trade-off. Our work enlarges the applicability range of SystemC AMS based design frameworks.

Published
2020

81. Body-Bias Micro-Generators for Activity-Driven Power Management

Author

Fesquet, Laurent, Decoudu, Yoan, Iga Jadue, Rodrigo, Ferreira de Paiva Leite, Thiago, Rolloff, O., Diallo, Mamadou, Possamai Bastos, Rodrigo, Morin-Allory, Katell, Engels, Sylvain, Circuits, Devices and System Integration (CDSI), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), STMicroelectronics [Crolles] (ST-CROLLES), European Project: 783127,H2020-EU.2.1.1.7. - ECSEL,OCEAN12(2018), BEN TITO, Laurence, Opportunity to Carry European Autonomous driviNg further with FDSOI technology up to 12nm node - OCEAN12 - 2018-04-01 - 2021-12-31 - 783127 - VALID, Circuits, Devices and System Integration [2020-….] (CDSI [2020-….]), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés [2020-….] (TIMA [2020-….]), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2020-....] (UGA [2020-....])-Institut polytechnique de Grenoble - Grenoble Institute of Technology [2020-....] (Grenoble INP [2020-....]), Université Grenoble Alpes [2020-....] (UGA [2020-....])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2020-....] (UGA [2020-....])-Institut polytechnique de Grenoble - Grenoble Institute of Technology [2020-....] (Grenoble INP [2020-....]), Université Grenoble Alpes [2020-....] (UGA [2020-....]), and Circuits, Devices and System Integration (TIMA-CDSI)

Subjects
[SPI.NANO] Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, PACS 85.42, local body-biasing techniques, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, asynchronous circuit, ComputingMilieux_MISCELLANEOUS, FDSOI
Abstract

International audience

Published
2020

82. Low Power Tiny Binary Neural Network with improved accuracy in Human Recognition Systems

Author

Frédéric Pétrot, Gian Domenico Licciardo, Luigi Di Benedetto, Antonio De Vita, Alfredo Rubino, Danilo Pau, Università degli Studi di Salerno (UNISA), STMicroelectronics [Agrate Brianza] (ST-AGRATE), System Level Synthesis (SLS ), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), and ANR-19-P3IA-0003,MIAI,MIAI @ Grenoble Alpes(2019)

Subjects
[INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], human activity recognition, Computer science, 02 engineering and technology, Accelerometer, Activity recognition, Inertial measurement unit, digital AI acceleration, 0202 electrical engineering, electronic engineering, information engineering, Field-programmable gate array, FPGA, Artificial neural network, business.industry, Deep learning, 020206 networking & telecommunications, Ranging, binarized neural networks, inertial sensors, low power hardware implementation, PACS 85.42, Hardware acceleration, 020201 artificial intelligence & image processing, Artificial intelligence, business, Computer hardware
Abstract

International audience; Human Activity Recognition requires very high accuracy to be effectively employed into practical applications, ranging from elderly care to microsurgical devices. The highest accuracies are achieved by Deep Learning models, but these are not easily deployable in handheld or wearable devices with very constrained resources. We therefore present a new HAR system suitable for a compact FPGA implementation. A new Binarized Neural Network (BNN) architecture achieves the classification based on data from a single tri-axial accelerometer. From our experiments, the effect of gravity and the unknown orientation of the sensor cause a degradation of the accuracy. In order to compensate for these issues, we propose a HW-friendly algorithm to pre-process the raw acceleration signal. Moreover, the very low power and hardware friendly BNN has been trained and validated on the PAMAP2 dataset, for which the pre-processing operations increase the accuracy from 51% to 99% in the best case. A iming for a low-power design, we designed both a custom circuit to perform the pre-processing operations and a hardware accelerator for the BNN. The design on FPGA features a power dissipation of 72 mW and occupies 6788 LUTs.

Published
2020

83. Latest Trends in Hardware Security and Privacy

Author

Di Natale, G., Regazzoni, F., Albanese, V., Lhermet, F., Loisel, Y., Sensaoui, A., Pagliarini, S., Dilillo, L., Psarakis, M., Siddiqua, T., BEN TITO, Laurence, IEEE, Architectures and Methods for Resilient Systems (AMfoRS ), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), Università della Svizzera italiana = University of Italian Switzerland (USI), SiFive France (SiFive France), Tallinn University of Technology (TTÜ), and System and Network Engineering (IVI, FNWI)

Subjects
Hardware security module, business.industry, Computer science, [SPI.NANO] Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, 05 social sciences, 02 engineering and technology, Computer security, computer.software_genre, Field (computer science), 020202 computer hardware & architecture, Software, 050903 gender studies, PACS 85.42, 0202 electrical engineering, electronic engineering, information engineering, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, 0509 other social sciences, business, computer
Abstract

International audience; In the last two decades we have witnessed a massive development of technologies (both hardware and software) which have enabled the creation of billions of connected devices. These devices are nowadays used in a very wide range of applications, and they all contain different types of valuable assets, which have been the target of an increasing number of cyber attacks. Both scientific and industrial communities have focused their attention to implement new design processes to reduce the risk of cybersecurity breaches. This paper includes two different contributions in the field of hardware security and privacy

Published
2020

84. Efficient Implementation of Convolution and Winograd on ASMP Embedded Multicore Vector Processor

Author

Stephane Mancini, Jean-Paul Henriques, Claude Delnondedieu, Nicolas Leclaire, BEN TITO, Laurence, MIAI @ Grenoble Alpes - - MIAI2019 - ANR-19-P3IA-0003 - P3IA - VALID, STMicroelectronics [Grenoble] (ST-GRENOBLE), Circuits, Devices and System Integration (CDSI), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), and ANR-19-P3IA-0003,MIAI,MIAI @ Grenoble Alpes(2019)

Subjects
Multi-core processor, Coprocessor, Computer science, business.industry, [INFO.INFO-TS] Computer Science [cs]/Signal and Image Processing, 0211 other engineering and technologies, 021107 urban & regional planning, Cloud computing, Context (language use), 02 engineering and technology, Convolutional neural network, 020202 computer hardware & architecture, Vector processor, Convolution, Memory management, Computer engineering, [INFO.INFO-TS]Computer Science [cs]/Signal and Image Processing, PACS 85.42, 0202 electrical engineering, electronic engineering, information engineering, business, ComputingMilieux_MISCELLANEOUS
Abstract

Efficient inference of Convolutional Neural Network (CNN) is a challenging task and design choices heavily rely on the target context and size of the CNN model. Many devices are available, each one targeting a specific class of application. The most famous ones target the server-side of cloud applications and some focus on embedded applications. In this paper we show how to exploit the low-level hardware features of an embedded multicore called STxP70 ASMP, each core being equipped with a vector coprocessor. This work shows how to adapt the algorithm to the platform and vice-versa, and provides an original algo rithmic transform to optimize internal resources. Experiments are made to study the effect of numerous design parameters and CNN configurations. The results show the benefits of the proposed strategy and outline the low-level hardware features required to further optimize CNN inference.

Published
2020

85. Modeling Novel Non-JTAG IEEE 1687-Like Architectures

Author

Michele Portolan, B.G. Van Treuren, Martin Keim, M. Abdalwahab, Al Crouch, M. Laisne, Jeff Rearick, H. M. von Staudt, BEN TITO, Laurence, Dialog Semiconductor GmbH [Munich], Amida Technology Solutions (Amida), Architectures and Methods for Resilient Systems (AMfoRS ), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), Mentor Graphics Corporation, NXP Semiconductors, VT Enterprises, Advanced Micro Devices [Austin] (AMD), and Advanced Micro Devices

Subjects
Interface (Java), business.industry, Computer science, Controller (computing), [SPI.NANO] Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Interoperability, 020206 networking & telecommunications, 02 engineering and technology, Data flow diagram, Vector graphics, PACS 85.42, 020204 information systems, Embedded system, Retargeting, 0202 electrical engineering, electronic engineering, information engineering, Callback, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, business, Block (data storage)
Abstract

International audience; Many modern devices have a very limited number of digital pins, yet they are often quite complicated internally. Such These ICs can’t afford the luxury of a traditional JTAG TAP controller and the associated 4 or 5 extra pins. Nonetheless, these devices often contain significant digital and analog content. This complexity makes testing very challenging. Moreover, IP-based design might often results in having an instrument buried deep inside a device, whose the access of which requires transitioning through multiple interfaces and controllers. This is exactly the situation DfT and test engineers face when designing and implementing tests for embedded IP. Techniques proposed for IEEE P1687.1 enable an automated mechanism for retargeting tests through a variety of non-TAP interfaces. This makes these products ideal candidates for IJTAG and IJTAG.1 test strategies.In this paper, we focus on demonstrating how on-chip test functions and IP can be successfully controlled and observed through non-TAP interfaces by controlling data flow using RVF (Relocatable Vector Format) and callbacks. This unique and novel approach ensures tool interoperability and allows tools to view model interfaces in the same way, without requiring special descriptions for each one. The paper proposes an automated tool flow for retargeting the tests and provides example implementations on several specialized designs including I2C, IEEE 1149.7, TPSP (2 pin Serial Port)an In-System TAP, IEEE 1149.7-like interface, and a security block

Published
2020

86. Chisel Usecase: Designing General Matrix Multiply for FPGA

Author

Frederic Rousseau, Olivier Muller, Bruno Ferres, System Level Synthesis (SLS ), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), Fernando Rincón, Jesús Barba, Hayden K. H. So, Pedro Diniz, and Julián Caba

Subjects
[INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], 010302 applied physics, business.industry, Computer science, Circuit design, Chisel, 02 engineering and technology, 01 natural sciences, Matrix multiplication, 020202 computer hardware & architecture, multiplication de matrice, PACS 85.42, Embedded system, 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, General matrix, matrix multiply, Field-programmable gate array, business, Implementation, FPGA
Abstract

International audience; To ease developers work in an industry where FPGA usage is constantly growing, we propose an alternative methodology for architecture design. Targeting FPGA boards, we aim at comparing implementations on multiple criteria. We implement it as a tool flow based on Chisel, taking advantage of high level functionalities to ease circuit design, evolution and reutilization, improving designers productivity.We target a Xilinx VC709 board and propose a case study on General Matrix Multiply implementation using this flow, which demonstrates its usability with performances comparable to the state of the art, as well as the genericity one can benefit from when designing an application-specific accelerator. We show that we were able to generate, simulate and synthesize 80 different architectures in less than 24 h, allowing different trade-offs to be quickly and easily studied, from the most performant to the less costly, to easily comply with integration constraints.

Published
2020

87. State of the art in hardware-accelerated neural networks

Author

Frédéric Pétrot, Lorena Anghel, Liliana Lilibeth Andrade Porras, BEN TITO, Laurence, MIAI @ Grenoble Alpes - - MIAI2019 - ANR-19-P3IA-0003 - P3IA - VALID, System Level Synthesis (SLS ), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), Architectures and Methods for Resilient Systems (AMfoRS ), and ANR-19-P3IA-0003,MIAI,MIAI @ Grenoble Alpes(2019)

Subjects
[INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-AR] Computer Science [cs]/Hardware Architecture [cs.AR], PACS 85.42, ComputingMilieux_MISCELLANEOUS
Abstract

Vidéo de la présentation: https://www.youtube.com/watch?v=zU7vtDDgUic; International audience

Published
2020

88. PUF Enrollment and Life Cycle Management: Solutions and Perspectives for the Test Community

Author

Bertrand Cambou, Amir Ali Pour, Naghmeh Karimi, Sylvain Guilley, Vincent Beroulle, Giorgio Di Natale, Jean-Luc Danger, David Hely, BEN TITO, Laurence, IEEE, Département Communications & Electronique (COMELEC), Télécom ParisTech, Secure and Safe Hardware (SSH), Laboratoire Traitement et Communication de l'Information (LTCI), Institut Mines-Télécom [Paris] (IMT)-Télécom Paris-Institut Mines-Télécom [Paris] (IMT)-Télécom Paris, Institut Mines-Télécom [Paris] (IMT)-Télécom Paris, Architectures and Methods for Resilient Systems (AMfoRS ), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), Laboratoire de Conception et d'Intégration des Systèmes (LCIS), Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Université Grenoble Alpes (UGA), Northern Arizona University [Flagstaff], University of Maryland [Baltimore County] (UMBC), and University of Maryland System

Subjects
Stan- dardization, Standardization, Computer science, [SPI.NANO] Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, 02 engineering and technology, On Line Test, Master key, Enrollment, 0202 electrical engineering, electronic engineering, information engineering, Physically Unclonable Functions (PUF), Challenge/Response Pair Database Management, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, ComputingMilieux_MISCELLANEOUS, business.industry, Chip, 020202 computer hardware & architecture, Test (assessment), [SPI.TRON]Engineering Sciences [physics]/Electronics, Identification (information), ComputingMilieux_MANAGEMENTOFCOMPUTINGANDINFORMATIONSYSTEMS, Product life-cycle management, Embedded system, Authentication protocol, PACS 85.42, 020201 artificial intelligence & image processing, business
Abstract

International audience; Physically Unclonable Functions (PUFs) allow to extract unique fingerprints from silicon chips. The applications are numerous: chip identification, chip master key extraction, authentication protocol, unique seeding, etc. However, secure usage of PUF requires some precautions. This paper reviews industrial concerns associated with PUF operation, including those occurring before and after market. Namely, starting from PUF “secure”specifications, aligned with state-of-the-art standards, we explore innovative techniques to handle enrollment and subsequent PUF queries, in nominal as well as in adversarial environment.

Published
2020

89. Machine learning and hardware security : challenges and opportunities

Author

Naofumi Homma, Amir Ali Pour, Ihab Alshaer, Seetal Potluri, Ville Yli-Mayry, David Hely, Paul D. Franzon, Dirmanto Jap, Aydin Aysu, Priyank Kashyap, Ilia Polian, Elena Ioana Vatajelu, Furkan Aydin, Giorgio Di Natale, Rei Ueno, Vincent Beroulle, Francesco Regazzoni, Shivam Bhasin, Akira Ito, Temasek Laboratories @ NTU, Università della Svizzera italiana = University of Italian Switzerland (USI), Nanyang Technological University [Singapour], Architectures and Methods for Resilient Systems (AMfoRS ), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), North Carolina State University [Raleigh] (NC State), University of North Carolina System (UNC), Laboratoire de Conception et d'Intégration des Systèmes (LCIS), Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Université Grenoble Alpes (UGA), Tohoku University [Sendai], University of Stuttgart, IEEE, and BEN TITO, Laurence

Subjects
021110 strategic, defence & security studies, Hardware security module, Post-quantum cryptography, Artificial neural network, business.industry, Computer science, [SPI.NANO] Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, 0211 other engineering and technologies, Cryptography, 02 engineering and technology, Machine learning, computer.software_genre, Public-key cryptography, Machine Learning, Quantum cryptography, PACS 85.42, 0202 electrical engineering, electronic engineering, information engineering, Computer science and engineering [Engineering], 020201 artificial intelligence & image processing, Hardware Security, Artificial intelligence, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, business, Digital watermarking, computer
Abstract

International audience; Machine learning techniques have significantly changed our lives. They helped improving our everyday routines, but they also demonstrated to be an extremely helpful tool for more advanced and complex applications. However, the implications of hardware security problems under a massive diffusion of machine learning techniques are still to be completely understood. This paper first highlights novel applications of machine learning for hardware security, such as evaluation of post quantum cryptography hardware and extraction of physically unclonable functions from neural networks. Later, practical model extraction attack based on electromagnetic side- channel measurements are demonstrated followed by a discussion of strategies to protect proprietary models by watermarking them.

Published
2020

90. Circuit and Method for Protecting Asynchronous Circuits

Author

Fesquet, Laurent, Cherkaoui, A., Gimenez, Grégoire, Frisch, Raphael, BEN TITO, Laurence, Circuits, Devices and System Integration (CDSI), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), and Dolphin Integration

Subjects
PACS 85.42, [SPI.NANO] Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Hardware_PERFORMANCEANDRELIABILITY, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics
Abstract

The present disclosure relates to a fault detection circuit comprising: sampling elements (SE_1 to SE_L) configured to sample signals present at a plurality of nodes (n1 to nL) of an asynchronous circuit (100); a logic circuit (110) configured to determine a number of tokens (Ν' ) in the asynchronous circuit based on the sampled signals; and a comparator (112) configured to compare the determined number of tokens with a reference value (N), a fault being detected based on said comparison.

Published
2020

91. A Novel Event Based Image Sensor Architecture

Author

Akrarai, Mohamed, Sicard, G., Fesquet, Laurent, Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), European Project: 783127,H2020-EU.2.1.1.7. - ECSEL,OCEAN12(2018), BEN TITO, Laurence, and Opportunity to Carry European Autonomous driviNg further with FDSOI technology up to 12nm node - OCEAN12 - 2018-04-01 - 2021-12-31 - 783127 - VALID

Subjects
image sensor architecture, [SPI.NANO] Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, PACS 85.42, frameless image sensor, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, ComputingMilieux_MISCELLANEOUS
Abstract

International audience

Published
2019

92. Desynchronizing Circuits Synthesized with CatapultC

Author

Decoudu, Yoan, Simatic, Jean, Morin-Allory, Katell, Fesquet, Laurent, Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), HawAI.Tech, European Project: 783127,H2020-EU.2.1.1.7. - ECSEL,OCEAN12(2018), and HawAI.tech

Subjects
circuit desynchronization, PACS 85.42, high-level synthesis, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, ComputingMilieux_MISCELLANEOUS
Abstract

International audience

Published
2019

93. Reliability of neuromorphic computing

Author

Vatajelu, Elena Ioana, Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), BEN TITO, Laurence, Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA), and Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)

Subjects
[SPI.NANO] Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, PACS 85.42, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, ComputingMilieux_MISCELLANEOUS
Abstract

National audience

Published
2019

94. Multiple heater-sensor microsystems on a single glass slide to monitor cell culture temperature

Author

Garraud, A., Debontride, G., Blachier, D., Basrour, Skandar, Peyrade, D., Laboratoire des technologies de la microélectronique (LTM ), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), CIME, INPG, Grenoble (CIME), Institut National Polytechnique de Grenoble (INPG), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), and BEN TITO, Laurence

Subjects
[SPI.NANO] Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, PACS 85.42, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, ComputingMilieux_MISCELLANEOUS
Abstract

International audience

Published
2019

95. Coherence State Awareness in Way-Replacement Algorithms for Multicore Processors

Author

Alcantara Souza, M., Cota Freitas, H., Pétrot, Frédéric, Universidade Federal de Minas Gerais [Belo Horizonte] (UFMG), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), and Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019])

Subjects
[INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], PACS 85.42, ComputingMilieux_MISCELLANEOUS
Abstract

International audience

Published
2019

96. IEEE European Test Symposium (ETS)

Author

Elena Ioana Vatajelu, Jaan Raik, Matteo Sonza Reorda, Mehdi B. Tahoori, Maria K. Michael, Artur Jutman, Stephan Eggersgluss, Said Hamdioui, Mentor Graphics Corp. (USA), Computer Engineering - Delft University of Technology (CE), Delft University of Technology (TU Delft), Testonica Labs (Testonica Labs), University of Cyprus [Nicosia], Tallinn Technical University, Politecnico di Torino [Torino] (Polito), Karlsruhe Institute of Technology (KIT), Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA), Politecnico di Torino = Polytechnic of Turin (Polito), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), and Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019])

Subjects
Engineering, business.industry, 020204 information systems, PACS 85.42, 0202 electrical engineering, electronic engineering, information engineering, Library science, 020206 networking & telecommunications, 02 engineering and technology, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, business, ComputingMilieux_MISCELLANEOUS, Test (assessment)
Abstract

International audience; This paper is dedicated to the IEEE European Test Symposium (ETS). It offers an overview of all the European Test Workshop and Symposium events, from its first edition in 1996 to the next edition in 2020.

Published
2019

97. Gathering Memory Hierarchy Statistics in QEMU

Author

Deschamps, Cl., Pétrot, Frédéric, Burton, M., Jenn, Eric, GreenSocs, System Level Synthesis (SLS ), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), IRT Saint Exupéry - Institut de Recherche Technologique, and BEN TITO, Laurence

Subjects
cache simulation, traduction binaire dynamique, [INFO.INFO-CR]Computer Science [cs]/Cryptography and Security [cs.CR], simulation de cache, PACS 85.42, dynamic binary translation, [INFO.INFO-CR] Computer Science [cs]/Cryptography and Security [cs.CR]
Abstract

International audience; Fast functional verification using Transaction Level Modeling of hardware/software systems typically makes use of fast, dynamic binary translation based, processor models. When it comes to estimating performance figures, either higher level analytical models, or lower level cycle-accurate/approximate models are generally used. However, we believe that metrics relative to the memory hierarchy can be relatively accurately acquired while working with fast processor simulators at transaction level. This, of course, sacrifices some speed for accuracy, but lets the designer work in their usual environment and the resulting model only sacrifices about 30% in terms of performance, for a single core model. In this paper, we detail our level one cache modeling strategy and how we implement it. We then measure simulation speed overheads and compare our statistics with information gathered on the Cortex R5 PMU of Xilinx UltraScale-Plus board running the same benchmark.

Published
2019

98. Multi-Triggered Embedded Software Code Generation for Electrical Metering and Protection Applications

Author

Roland Bohrer, Benoit Leprettre, Frederic Rousseau, Frédéric Pétrot, Louis Bonicel, Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), Schneider Electric ( SE), and BEN TITO, Laurence

Subjects
[INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-AR] Computer Science [cs]/Hardware Architecture [cs.AR], business.industry, Computer science, media_common.quotation_subject, 020208 electrical & electronic engineering, Overhead (engineering), 02 engineering and technology, Embedded software, Embedded system, PACS 85.42, 0202 electrical engineering, electronic engineering, information engineering, 020201 artificial intelligence & image processing, Quality (business), Metering mode, Code generation, business, ComputingMilieux_MISCELLANEOUS, media_common
Abstract

Code generation can be an effective way to improve quality of a product and reduce development time. But applied naively to multi-triggered applications such as electrical metering and protection algorithms, performance can be drastically degraded. In this paper we present a solution to model a multi-triggered application in Mathworks Simulink for efficient code generation using a buffering mechanism specified in the model, with little overhead in usage of resources. The performance of the presented solution is compared with different modeling approaches and with a reference manually-coded implementation.

Published
2019

99. A Distributed Body-Biasing Strategy for Asynchronous Circuits

Author

Katell Morin-Allory, T. Ferreira de Paiva Leite, M. Diallo, Laurent Fesquet, Sylvain Engels, Yoan Decoudu, O. Rolloff, A. R. Iga Jadue, R. Possamai Bastos, Circuits, Devices and System Integration (CDSI), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), STMicroelectronics [Crolles] (ST-CROLLES), BEN TITO, Laurence, Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA), and Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)

Subjects
Standard cell, Power management, Handshake, Computer science, [SPI.NANO] Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Transistor, 02 engineering and technology, 021001 nanoscience & nanotechnology, 020202 computer hardware & architecture, law.invention, law, Asynchronous communication, Robustness (computer science), PACS 85.42, 0202 electrical engineering, electronic engineering, information engineering, Electronic engineering, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, 0210 nano-technology, ComputingMilieux_MISCELLANEOUS, Hardware_LOGICDESIGN, Electronic circuit, Asynchronous circuit
Abstract

The fast evolving pace of electronic mobile devices have made mandatory to reduce power consumption without compromising the circuit performance or its robustness. Asynchronous circuits have demonstrated to be an excellent solution to help designing robust and energy-efficient circuits required for the Internet-of-Things and the mobile applications. Their local synchronization mechanisms, based on handshake protocols, make them perfectly suitable for exploiting dynamic power management techniques, such as Adaptive Body Biasing (ABB) in FD-SOI technologies. Indeed, the circuit activity is simply detected by using the already existing handshake signals, enabling the application of different ABB strategies with almost no modification to the original asynchronous circuit. As the synchronization mechanisms are local to small logic blocks, the ABB strategy is able to target from small to large body bias domains. In order to manage such a technique, an analog dedicated standard cell has been designed to body bias small regions. Depending on the body bias domain granularity, an appropriated number of these specific cells is inserted exactly as logic standard cells during the back-end operations. Additionally, the robustness of asynchronous circuits makes possible changing the transistor threshold voltage on-the-fly, a requirement for applying ABB schemes without complex power management issues.

Published
2019

100. Energy savings and thermal comfort benefits of shading devices: case study of a typical moroccan building

Author

Mohamed Tabaa, Badr Chegari, Fouad Moutaouakkil, Emmanuel Simeu, Hicham Medromi, Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), Ecole Marocaine des Sciences de l'Ingénieur (EMSI), Ecole Nationale Supérieure d'Electricité et de Mécanique [Casablanca] (ENSEM), Université Hassan II [Casablanca] (UH2MC), and BEN TITO, Laurence

Subjects
business.industry, [SPI.NANO] Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Environmental engineering, Thermal comfort, Energy consumption, TRNSYS, Work (electrical), Air conditioning, PACS 85.42, HVAC, Environmental science, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, business, Tertiary sector of the economy, Efficient energy use
Abstract

International audience; The building sector in Morocco represents about 25% of the country's total energy consumption, including 18% for the residential sector and 7% for tertiary sector. This energy consumption is expected to rise due to the significant rise of household equipment rates in HVAC facilities, mainly air conditioners. This work presents the effect of the use of solar protection (overhangs and wings) on the thermal comfort as well as the energy performance of a typical Moroccan building R+1 (Ground floor + First floor) in three different climates, namely Marrakech, Casablanca and Tangier. This was achieved through the use of the dynamic thermal simulation, which is performed by the TRNSYS software. The results show that the use of solar protection has made a positive contribution, first, to the thermal comfort and, secondly, to the energy performance of the studied building. This is reflected in reductions in heating and cooling demand, which represent 5.57%, 4.41% and 3.95% respectively in Casablanca, Marrakech and Tangier.

Published
2019

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