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This brief introduces a simple circuit solution to secure loop stability of an analog-domain fast-frequency offset cancellation loop (OCL). The OCL is composed of a low-IF receiver, phase-domain frequency offset detector (OD), and fractional-N phase-locked loop (PLL). Since the OCL uses a phase-domain OD, a stability concern is essentially needed for its practical use. From the frequency-domain analysis, a PLL bandwidth adaptation by controlling charge-pump currents is proposed to achieve a strong stability with phase-margin of more than 60[degrees]. Additionally, a tradeoff between the OCL accuracy and hardware complexity is discussed, and a design example is shown for the 2.4-GHz ZigBee application. With 4-MHz IF, designed for an 0.18-[micro]m CMOS process, our circuit takes 30[micro]s to reject the frequency offset of +200 kHz within the accuracy of [+ or -] 5 ppm, with 60-DFFs for a time-to-digital converter. Index Terms--Frequency offset, frequency synthesizer, low intermediate frequency, stability, time-to-digital converter (TDC).

In this paper, we present a new technique by combining the Taylor series expansion with the Arnoldi method to automatically develop reduced-order models for coupled energy domain nonlinear microelectromechanical devices. An electrostatically actuated fixed-fixed beam structure with squeeze-film damping effect is examined to illustrate the model-order reduction method. Simulation results show that the reduced-order nonlinear models can accurately capture the device dynamic behavior over a much larger range of device deformation than the conventional linearized model. Compared with the fully meshed finite-difference method, the model reduction method provides accurate models using orders of magnitude less computation. The reduced MEMS device models are represented by a small number of differential and algebraic equations and thus can be conveniently inserted into a circuit simulator for fast and efficient system-level simulation. [890] Index Terms--Macromodeling, microelectromechanical systems (MEMS), microsystems, model-order reduction, nonlinear, simulation.

Design and modeling of a micromachined high-Q tunable capacitor with large tuning range and a vertical planar spiral inductor, implemented in a microelectromechanical system, is described and discussed.

In this paper, we describe parallel dynamic logic (PDL) which exhibits high speed without charge sharing problem. PDL uses only parallel-connected transistors for fast logic evaluation and is a good candidate for high-speed low-voltage operation. It has less back-bias effect compared to other logic styles, which use stacked transistors. Furthermore, PDL needs no signal ordering or tapering. PDL with speed-enhanced skewed static logic renders straightforward logic synthesis without the usual area penalty due to logic duplication. Our experimental results on two 32-bit carry lookahead adders using 0.25-/[micro]m CMOS technology show that PDL with speed-enhanced skewed static (SSS) logic reduces the delay over clock-delayed(CD)-domino by 15%-27% and the power-delay product by 20%-37%. Index Terms--Adder, dynamic logic, low-power, skewed logic.

The results of two techniques for optical carrier regeneration and wavelength reuse using semiconductor optical amplifiers (SOAs) are presented in this paper. The main objective is to recover an optical carrier by erasing its amplitude modulation. The first technique employs gain compression of deeply saturated SOAs. The second technique uses a feed-forward approach, where a delayed current signal is injected into the SOA with the same shape of the incoming optical pulse. The second technique could be capable to recover the optical carrier with less than 3-dB noise. However, it was observed that the SOA gain recovery time limits the maximum usable bit rate. Theoretical simulation showed good agreement with experimental results. Index Terms--Optical carrier regeneration, optical pulse reshaping, optical wavelength reuse, semiconductor optical amplifier.