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Amorphous diamond films have been prepared by filtered cathodic arc deposition of carbon. The filtered arc is well suited for the growth of amorphous diamond, as it provides carbon ions with optimum kinetic energies at practical deposition rates. These films contain no hydrogen and are therefore structurally different from diamond‐like carbon films generated by plasma chemical vapor deposition. Diamond‐type bonding of carbon is quantitatively determined by electron energy loss spectroscopy, as an sp3 content up to 83% is measured. Data on the macroscopic properties are provided by optical transmittance, ellipsometry, Rutherford backscattering, elastic recoil scattering, and resistivity measurements. The films exhibit high optical transparency and an optical gap of 2.4 eV. Trends in the optical gap and refractive index as a function of deposition energy are consistent with semiconductor theory and indicates a change in the average bond length.

We imaged nanoscale lattice strain in a multilayer semiconductor device prototype with a new X-ray technique, nanofocused Bragg projection ptychography. Applying this technique to the epitaxial stressor layer of a SiGe-on-SOI structure, we measured the internal lattice behavior in a targeted region of a single device and demonstrated that its internal strain profile consisted of two competing lattice distortions. These results provide the strongest nondestructive test to date of continuum modeling predictions of nanoscale strain distributions.

Spatially resolved electron energy-loss spectroscopy has been used to interrogate the chemistry and bonding at grain boundaries in hot isostatically pressed (HIPed) high purity silicon nitride ceramics nominally doped with either 0, 100, 300 or 500 at. ppm calcium. Analysis of the nanometer thick glassy films between grains, shows that there is a monotonic increase in impurity segregation with dopant concentration. The predominant constituents of the grain boundary films are Si, O and N, forming a silicon oxynitride phase ranging in composition from SiO 2 to Si 2 N 2 O. The energy-loss near-edge structure indicates the structure of the glass is composed predominantly of tetrahedra but also suggests the presence of a small concentration of molecular N 2 , possibly as sub-microscopic bubbles. There is still no data on the composition gradients on a sub-nanometer level, though it is shown that in the detection limit set by counting statistics, near single atom sensitivity with a spatial resolution of 0.22 nm is achievable.

High-resolution electron microscopy and nano-beam analytical electron microscopy have been used to characterize both the intergranular silicate film thickness and its local composition in a series of high-purity Si3N4 ceramics doped with 0–450 at. ppm Ca. Calcium was detected at both two-grain junctions and triple junctions, even in the 80-ppm-Ca-doped specimen. The thickness of the intergranular film at two-grain junctions was found to depend sensitively on Ca content. In undoped material, the thickness was 1.0 ± 0.1 nm. With increasing Ca content, the thickness decreased in the dilute region (80 ppm Ca), but then increased. The variation in film thickness can be qualitatively understood in terms of the balance of three long-range forces acting normal to the film, namely the van der Waals dispersion force, a structural “steric” force, and an electrical-double-layer force. By comparing the measured thicknesses to those predicted, estimates for the structural correlation length and the inverse Debye length can be made. These estimates have values of ∼ 0.22 nm and approximately 0.3–0.5 nm, respectively, for the calcia-free and 80 ppm calcia materials.

We demonstrate the potential for ultrathin aluminum-oxide films as alternate gate dielectrics for Si complementary metal–oxide–semiconductor technology. Films are deposited in ultrahigh vacuum utilizing atomic beams of aluminum and oxygen on Si(100) surfaces. We show device-quality Si(100)/Al2O3 interfaces with interfacial trap densities in the 1010 cm−2 eV−1 range, and with leakage current densities five orders of magnitude lower than what is observed in SiO2 insulators at the same equivalent electrical thickness. As-grown films possess an amorphous-to-microcrystalline structure, depending upon the deposition temperature, and any interfacial layers between the Si(100) and Al2O3 layer are

The high current density induced failure in Ge 2 Sb 2 Te 5 (GST)-based phase change memory (PCM) is investigated. A strong dependence of cycling endurance on the polarity of the operation current is observed and reported for the first time. The cycling endurance is reduced by 4 orders of magnitude when the current polarity is reversed. Careful TEM analysis of failed cells revealed a thin void in GST over the bottom electrode, but only in the reverse polarity samples. This phenomenon can be explained by hole-induced electromigration at the electrode/GST interface. The impact of electromigration on scaled phase change memory is discussed.

In this work we present a potential solution for forming ultra-shallow junctions with extremely low contact resistivities in which dopants are implanted into silicides and diffused to the semiconductor interface using low temperature anneals. Conventional silicide process requires a fine tuning of silicide thickness and deep source/drain doping profile to achieve low contact resistance and low source/drain diffusion sheet resistance. With the silicide implantation approach, we show that they can be engineered independently, providing a larger design space for the reduction of total external resistance. We demonstrate that contact resistance for NiPt silicide can be significantly reduced down to 7×10−9 Ω-cm2 for p+ Si and 6×10−9 Ω-cm2 for n+ Si by using Schottky Barrier Height (SBH) tuning through the implantation of B/As into pre-formed NiPtSi followed by low-temperature drive-in annealing (see Fig. 1 for the process flow). Moreover, we find that the same low contact resistance can be achieved for both heavily and moderately doped junctions, which grants an additional degree of freedom in junction design to reduce series resistance. With this technology, the ultra-shallow junction process can be simplified to the formation of ultra-thin silicide followed by shallow implantation and low temperature RTA (

Carbon is energetically deposited by pulsed laser vaporization, cathodic arc and ion beam sputtering to provide amorphous diamond films with varying degrees of diamondlike quality. Laser and arc films prepared at normal particle incidence are high in sp3 content and electrical resistivity, and exhibit optical behavior comparable to diamond. As the incident angle of the depositing species becomes increasingly oblique, the diamondlike character is progressively degraded. This is verified by decreases in sp3 fraction, resistivity, and optical transmittance. These changes are accompanied by a roughening of the microstructure, but no apparent variation in the transmission electron diffraction pattern. For deposition at the most oblique angles, the development of biaxial stress anisotropy is observed, as the compressive stress measured along the direction of incidence decreases at a greater rate than along the perpendicular direction. The implications of these results on the mechanisms proposed for amorphous di...

Carbon thin films have been prepared by 248 nm excimer laser vaporization of graphite targets. The effect of a variety of process parameters on the film properties is investigated. Deposition at or below room temperature yields diamond‐like films with low hydrogen content, high optical transmission, and high resistivity. Electron energy loss spectra indicate sp3 bond fractions of 70–85%. Detailed analyses of the pseudodielectric functions, measured using spectroscopic ellipsometry, show the films to have normal dispersion and an index of refraction of 2.5 in the visible wavelength region. The effects of a low pressure hydrogen background and the use of auxiliary pulsed and dc plasma enhancements are also examined.

We demonstrate a novel “remote interfacial layer (IL) scavenging” technique yielding a record-setting equivalent oxide thickness (EOT) of 0.42 nm using a HfO 2 -based MOSFET high-к gate dielectric. Intrinsic effects of IL scaling on carrier mobility are clarified using this method. We reveal that the mobility degradation observed for La-containing high-к is not due to the La dipole but due to the intrinsic IL scaling effect, whereas an Al dipole brings about additional mobility degradation. This unique nature of the La dipole enables aggressive EOT scaling in conjunction with IL scaling for the 16 nm technology node without extrinsic mobility degradation.

A new type of chrome-on-glass (COG) photomask defect was observed in 2006. Absorber material migrated into vias on dark field masks, partially obscuring the incident 193nm light and thereby causing the imaged photoresist to be underexposed. Through detailed characterization of new and defective photomasks and their histories it was determined that the migration is not caused by any unusual line events or faulty mask handling procedures. Rather, it is an inevitable result of mask use under specific conditions. Four essential elements have been identified: the presence of Cr, 193nm light exposure, charge, and water vapor and their roles elucidated through modeling studies and existing literature. We have reproduced Cr migration in the laboratory, demonstrating that these four elements are necessary and sufficient for this type of defect to occur. The only way to avoid Cr migration is to avoid reactions with water vapor.

Trends in recently reported data on high sp3 fraction (up to 85%), nonhydrogenated amorphous diamond‐like carbon films deposited by ion beam sputtering and laser vaporization are examined. The degree of diamondlike film character is found to depend upon the deposition technique as well as the substrate temperature and thermal diffusivity. The data suggest that the combination of incident particle kinetic energy and surface accommodation determine the physical properties of the resultant film. A model is proposed for the condensation of energetic carbon atoms into diamondlike films in which a quench‐type surface accommodation mechanism is operative.

We show for the first time that electron-energy-loss measurements of atomic absorption are different from the soft-x-ray photoyield data in the region influenced by the core exciton. We suggest that the core-exciton envelope function is influenced by the swift electron and its associated charge-density wake. Solving Schrodinger's equation for a model transition potential including the swift electron, we find that the observed differences for SiO x , diamond, and Si can be reproduced. Spectra from aluminum are included as a comparison when the exciton is absent

Thin films of carbon have been deposited at temperatures ranging from 77 to 1073 K. It has been found that diamond‐like properties of the films change with the deposition temperature and the thermal conductivity of the substrate. Densities as high as 2.9 g/cc with an sp3 bond content >40% have been observed. Substrates that have been investigated include graphite, NaCl, Si, Al2O3, fused quartz, and diamond. Density measurements have been made using Rutherford backscattering spectrometry and electron‐energy‐loss spectroscopy while hydrogen profiling was conducted using forward recoil spectrometry.

A process to deposit in situ a dual electron injector structure (DEIS) with 5‐nm SiO2 between two Si‐rich SiO2 (SRO) layers of ∼20 nm each has been developed. The excess silicon, as evaluated by Auger spectroscopy and Rutherford backscattering, was of the order of 15%–17%, in agreement with previously reported values under similar deposition conditions. Thin cross‐sectioned samples of DEIS structures, both as‐deposited and annealed at 1000 °C with Ar in an oxygen and water‐moisture‐free atmosphere, were examined by spatially resolved energy‐loss spectroscopy (EELS) in a scanning transmission electron microscope. The analysis has shown that the excess silicon is present either as nanometer‐sized silicon islands or as submicroscopic silicon oxides of varying stoichiometry resulting from intermediate oxidation states (i.e., Si+3, Si+2, and Si+1). Additionally, the thermal anneal at 1000 °C did not appear to have any effect on silicon island size of the SRO layer in contact with the silicon substrate. This su...

This paper shows ultra-low contact resistivities with standard NiPt silicide process that can reach 1times10-8 Omega-cm2 for both n+ and p+ Si by using novel test structures of small silicided contact with varied areas from 20-nm diameter to 260-nm diameter by e-beam lithography fabricated on highly doped substrate made by conventional source drain implantation. It demonstrates that NiPt silicide can fulfill CMOS technology requirements down to the ITRS 22nm node.

This paper shows ultra-low contact resistivities with standard NiPt silicide process that can reach below 10-8 Omega-cm2 for both n+ and p+ Si and demonstrates that NiPt silicide can fulfill CMOS technology requirements down to the ITRS 22 nm node.

We have successfully demonstrated a novel "pore" phase change memory cell, whose critical dimension (CD) is independent of lithography. Instead, the pore diameter is accurately defined by intentionally creating a "keyhole" with conformal deposition. Fully integrated 256 kbit test chips have been fabricated in 180nm CMOS technology. We report SET times of 80 ns, RESET currents less than 250 muA, and accurate sub-lithographic CDs that can be less than 20% the size of the lithographically -defined diameter.

III–V nanoscale devices were monolithically integrated on silicon-on-insulator (SOI) substrates by template-assisted selective epitaxy (TASE) using metal organic chemical vapor deposition. Single crystal III–V (InAs, InGaAs, GaAs) nanostructures, such as nanowires, nanostructures containing constrictions, and cross junctions, as well as 3D stacked nanowires were directly obtained by epitaxial filling of lithographically defined oxide templates. The benefit of TASE is exemplified by the straightforward fabrication of nanoscale Hall structures as well as multiple gate field effect transistors (MuG-FETs) grown co-planar to the SOI layer. Hall measurements on InAs nanowire cross junctions revealed an electron mobility of 5400 cm2/V s, while the alongside fabricated InAs MuG-FETs with ten 55 nm wide, 23 nm thick, and 390 nm long channels exhibit an on current of 660 μA/μm and a peak transconductance of 1.0 mS/μm at VDS = 0.5 V. These results demonstrate TASE as a promising fabrication approach for heterogeneou...

The emergence of multiple core, high speed microprocessors in sub 90nm node technologies present challenges for defect localization, especially in SRAM logic circuits involving Array Built In Self Test (ABIST). Voltage sensitive, temperature sensitive and frequency sensitive soft defects in these ABIST logic circuits can spell the difference between pass and failure, especially for Silicon on Insulator (SOI) designs. High density SRAM arrays with ever shrinking critical dimensions in multiple core, high speed microprocessor designs dictate an increased number of ABIST logic circuits of complex hierarchical design. Scan chain diagnostics to pinpoint the failing scan latch logic circuit following ABIST testing frequently results in ever greater uncertainty; increased number of suspect circuits related to the failure. A case study analysis successfully applied to pinpointing a voltage sensitive logic circuit defect in a 90nm SOI design is described here, followed by root cause TEM analysis.

Thermally stable dual work function metal gates are demonstrated using a conventional CMOS process flow. The gate structure consists of poly-Si/metal nitrides (MN/sub x/) SiON (or high-k)/Si stack with atomic layer deposition (ALD)-TaN/sub x/ for the NFET and ALD-WN/sub x/ for the PFET. Much enhanced drive current (I/sub d/) and transconductance (G/sub m/) values, and reduced off current (I/sub off/) characteristics were attained with ALD-MN/sub x/ gated devices over control poly-Si and PVD-MN/sub x/ devices within controllable V/sub t/ shifts. Excellent scalability of dual work function MN/sub x//high-k gate stack was demonstrated: the EOT was down to 6.6/spl Aring/ with low leakage in a low thermal budget device scheme.

As MOSFET device gate lengths shrink below the 130 nanometer node, the effects of short channel effects (SCE) and gate line edge roughness (LER) have an increasingly more pronounced affect on device performance [1-8, 10]. The 2001 International Technology Roadmap for Semiconductors (ITRS) predicts increasingly tighter critical dimensions (CD) control limits on LER from 2.7 nm in 2004 to 1.3 nm in 2010 [9,11]. As gate lengths shrink, resist etch processes emerge as the most significant contributor to LER [1-8, 11]. In addition, another contributing factor to SCE is junction implant defects. Examples of gate LER effects and junction defects in 130 nanometer node SOI SRAM MOSFET devices identified by sub-micron electrical characterization with analysis by high resolution transmission electron microscopy (TEM) are discussed.

A variable magnification electron holography, applicable for two-dimensional (2-D) potential mapping of semiconductor devices, employing a dual-lens imaging system is described. Imaging operation consists of a virtual image formed by the objective lens (OL) and a real image formed in a fixed imaging plane by the objective minilens. Wide variations in field of view (100-900 nm) and fringe spacing (0.7-6 nm) were obtained using a fixed biprism voltage by varying the total magnification of the dual OL system. The dual-lens system allows fringe width and spacing relative to the object to be varied roughly independently from the fringe contrast, resulting in enhanced resolution and sensitivity. The achievable fringe width and spacing cover the targets needed for devices in the semiconductor technology road map from the 350 to 45 nm node. Two-D potential maps for CMOS devices with 220 and 70 nm gate lengths were obtained.

This work reports on a methodology for achieving high drive current and low gate delay that can be used for the 70 nm technology node. A combination of optimized device design and aggressive gate oxide scaling has been applied to fabricate transistors with saturation currents of 1080 uA/um (NFET, 1171 uA/um dynamic) and 490 uA/um (PFET, 507 uA/um dynamic) at I/sub off/ levels of 100 nA/um for 1.1 volt operation. The physical gate length (L/sub poly/) for these devices is 39 nm. The saturation currents increase to 1180 uA/um and 540 uA/um at I/sub off/ levels of 300 nA/um, which corresponds to gate delays of 0.61 ps and 1.25 ps for NFET and PFET, respectively. These are among the lowest CV/I values ever reported for conventional CMOS scaling. These devices also exhibit excellent high-frequency response, which makes this technology ideally suited for system-on-chip applications that require both high-frequency signal processing and high-speed digital logic. A record high NFET f/sub max/ of 193 GHz has been demonstrated along with an f/sub T/ of 178 GHz.

Extended abstract of a paper presented at Microscopy and Microanalysis 2011 in Nashville, Tennessee, USA, August 7–August 11, 2011.

Strontium titanate, SrTiO3 (STO), thin films incorporated with lanthanum are grown on Si (001) substrates at a thickness range of 5–25 nm. Atomic layer deposition (ALD) is used to grow the LaxSr1−xTiO3 (La:STO) films after buffering the Si (001) substrate with four-unit-cells of STO deposited by molecular beam epitaxy. The crystalline structure and orientation of the La:STO films are confirmed via reflection high-energy electron diffraction, X-ray diffraction, and cross-sectional transmission electron microscopy. The low temperature ALD growth (∼225 °C) and post-deposition annealing at 550 °C for 5 min maintains an abrupt interface between Si (001) and the crystalline oxide. Higher annealing temperatures (650 °C) show more complete La activation with film resistivities of ∼2.0 × 10−2 Ω cm for 20-nm-thick La:STO (x ∼ 0.15); however, the STO-Si interface is slightly degraded due to the increased annealing temperature. To demonstrate the selective incorporation of lanthanum by ALD, a layered heterostructure ...

Extended abstract of a paper presented at Microscopy and Microanalysis 2010 in Portland, Oregon, USA, August 1 – August 5, 2010.

Extended abstract of a paper presented at Microscopy and Microanalysis 2010 in Portland, Oregon, USA, August 1 – August 5, 2010.

Extended abstract of a paper presented at Microscopy and Microanalysis 2010 in Portland, Oregon, USA, August 1 – August 5, 2010.

Thin carbon films were deposited by ion beam sputtering at temperatures of 77–1073 K. Using Rutherford backscattering spectrometry and electron energy loss spectroscopy, the trends in film density and bonding were examined as a function of deposition conditions. It has been found that film density and sp3 bonding character unexpectedly increased with increased substrate thermal conductivity and decreasing substrate temperature, reaching values of 2.9 g/cc and 50%, respectively.

Extended abstract of a paper presented at Microscopy and Microanalysis 2008 in Albuquerque, New Mexico, USA, August 3 – August 7, 2008

Detailed analysis of a buried layer of GaAs in 〈100〉 Si was carried out using electron energy loss spectroscopy, Rutherford backscattering spectroscopy, and ion channeling. The layer was formed by 200 keV dual ion implantation of Ga plus As ions, followed by furnace annealing at 600 and 950 °C. It consists of GaAs particles which are surrounded by fully recrystallized silicon. Beneath it is a dislocation network, made up of a mixture of edge and screw dislocations.

Radioactive tracer diffusion data is presented which illustrates some of the more interesting questions that need to be further understood. For example, in Al, Cu and Au alloys, solute decreases the activation energy, Ql, for lattice diffusion while increasing Qb for boundary diffusion in the same test samples. Secondly, this is true only for diffusion in the alloy itself; for example, Qb for Cu in pure Al boundaries is 0.4 eV while for Cu in All%Cu alloy boundaries is 0.73 eV. Also, for Qb, Sn in pure Cu is 0.8 eV, Cu in pure Cu is 0.92 eV, but in the Cu2%Sn alloy Sn is 1.2 eV and Cu 1.39 eV quite substantial changes. Of note is the observation that solute atomic size does not appear to be the deciding feature. The systems selected for study represent smaller, larger and similar solute size for Cu in Al, Sn in Cu and Ta in Au, respectively. Preliminary work has been accomplished on measuring the electron energy loss (EELS) of Cu in Al2%Cu grain boundaries, specifically to observe the electronic structure...

Atomic layer deposition (ALD) of epitaxial c-axis oriented BaTiO3 (BTO) on Si(001) using a thin (1.6 nm) buffer layer of SrTiO3 (STO) grown by molecular beam epitaxy is reported. The ALD growth of crystalline BTO films at 225 °C used barium bis(triisopropylcyclopentadienyl), titanium tetraisopropoxide, and water as co-reactants. X-ray diffraction (XRD) reveals a high degree of crystallinity and c-axis orientation of as-deposited BTO films. Crystallinity is improved after vacuum annealing at 600 °C. Two-dimensional XRD confirms the tetragonal structure and orientation of 7–20-nm thick films. The effect of the annealing process on the BTO structure is discussed. A clean STO/Si interface is found using in-situ X-ray photoelectron spectroscopy and confirmed by cross-sectional scanning transmission electron microscopy. The capacitance-voltage characteristics of 7–20 nm-thick BTO films are examined and show an effective dielectric constant of ∼660 for the heterostructure.

Dual lens dark field electron holography and Moire fringe mapping from dark field scanning transmission electron microscopy are used to map strain distributions at high spatial resolution in Si devices processed with stress memorization techniques (SMT). It provides experimental evidence that strain in the Si channel is generated by dislocations resulting from SMT. The highest value of strain, up to 1.1% (1.9 GPa in stress) occurs at the Si surface along the channel direction: ⟨110⟩. An increase of ∼0.2% strain in the channel is observed after removing the poly-Si gate through the replacement high-k metal gate process.

Using density functional theory, we analyze the wetting conditions for Pt on the (001) surface of ferroelectric BaTiO3 (BTO). We estimate the surface energy of (100), (110), and (111) Pt to be 2.42, 2.49, and 2.00 J/m2, respectively. We find the BTO surface energy to vary between 0.26 and 2.28 J/m2 depending on termination, polarization, and chemical environment. The interface energy between TiO2-terminated out-of-plane polarized BTO and (100) Pt is found to be between 1.64 and 2.62 J/m2, indicating that (100) Pt cannot wet BTO for this interface. A similar result is found for an interface with (110) Pt. Cross-sectional transmission electron microscopy of Pt films grown on BTO by molecular beam epitaxy with a low flux at high deposition temperature shows Volmer-Weber islands, consistent with first principles calculations.

We demonstrate a catalyst-free growth technique to directly integrate III-V semiconducting nanowires on silicon using selective area epitaxy within a nanotube template. The nanotube template is selectively filled by homo- as well as heteroepitaxial growth of nanowires with the morphology entirely defined by the template geometry. To demonstrate the method single-crystalline InAs wires on Si as well as InAs-InSb axial heterostructure nanowires are grown within the template. The achieved heterointerface is very sharp and confined within 5-6 atomic planes which constitutes a primary advantage of this technique. Compared to metal-catalyzed or self-catalyzed nanowire growth processes, the nanotube template approach does not suffer from the often observed intermixing of (hetero-) interfaces and non-intentional core-shell formation. The sequential deposition of different material layers within a nanotube template can therefore serve as a general monolithic integration path for III-V based electronic and optoelectronic devices on silicon.

not Available.

An epitaxial layer of SrTiO3 grown directly on Si may be used as a pseudo-substrate for the integration of perovskite oxides onto silicon. When SrTiO3 is initially grown on Si (001), it is nominally compressively strained. However, by subsequent annealing in oxygen at elevated temperature, an SiOx interlayer can be formed which alters the strain state of SrTiO3. We report a study of strain relaxation in SrTiO3 films grown on Si by molecular beam epitaxy as a function of annealing time and oxygen partial pressure. Using a combination of x-ray diffraction, reflection high energy electron diffraction, and transmission electron microscopy, we describe the process of interfacial oxidation and strain relaxation of SrTiO3 on Si (001). Understanding the process of strain relaxation of SrTiO3 on silicon will be useful for controlling the SrTiO3 lattice constant for lattice matching with functional oxide overlayers.

Spatially resolved electron energy loss spectroscopy analysis has been conducted on planar inversion domain boundaries in aluminum nitride. The defects were found to contain 1.5 monolayers of oxygen, in agreement with the most recent structural model of Westwood. From variations in near-edge structure, the local atomic environments of both oxygen and aluminum are compared with α-A1203, γ-A1203 and γ-AION standards. Based upon this study the stnrcture of the inversion domain boundary is found to resemble that of the cubic γ-AION spinel, and eliminates from consideration those structural models based upon ai-Al203. Furthermore, quantification of the shape resonances provided Al-O bond-length data from the inversion domain boundary interface. These distances closely agree with the Youngman Model that has recently been further refined by Westwood et al.

Yttrium lanthanum silicate was formed in direct contact with silicon after a rapid thermal annealing at 1000 °C in metal-oxide-semiconductor capacitors leading to an equivalent oxide thickness (EOT) of 7.7 A. This represents one of the lowest EOT value reported for a gate-first process with non Hf-based dielectric. The silicate is formed by interdiffusion of La2O3 and YOx layers and interfacial SiO2 consumption. Yttrium incorporation reduces the leakage current density as well as the large negative flatband voltage (Vfb) shift that is associated with lanthanide-based dielectrics. The Vfb value can be appropriately tuned for n-type field-effect transistor operation by changing the silicate composition.

A detailed comparison of high-k/metal gate stacks fabricated on the (100)- and (110)-oriented substrates has been made. We have verified that there is no structural difference between the gate stacks on the two substrates. The orientation independence of our gate stacks with the high-quality high-k/silicon interface for both substrates reveals the intrinsic effects of the crystal orientation on the high-k/metal gate devices. This is the first direct evidence that the inversion carrier quantization dependency on the crystal orientations dominates the total gate capacitance in the high-k/metal gate system. The analysis of the electron and hole mobilities highlights the fact that the scattering mechanisms inherent in the high-k/meta gate stacks limit the mobility enhancement and reduction driven by the effective mass change. No significant difference in the threshold voltage instability under the positive or negative gate bias stress is observed for the two substrates. Therefore, the optimized high-k/metal gate stacks enable us to gain certain benefits from the limited modulation of the mobility without sacrificing the stability of the threshold voltage.

The influence of the crystal orientation difference between (100) and (110) silicon substrates on characteristics of La2O3- and Al2O3-capped HfO2 dielectric metal–oxide–semiconductor field-effect transistors has been investigated. We observed that the equivalent oxide thickness of the capped devices varies according to the crystal orientation, indicating that the two substrates are not equal in the gate stack scalability within a sub-nanometer regime. We found that the mobility dependency on the crystal orientation is reduced by additional scattering associated with the capping films, suggesting the difficulty to derive maximum benefit from an inherent difference in the mobility depending on the crystal orientation.

LaxLu1−xO3 thin films were deposited on 300 mm silicon wafers by physical vapor deposition and fabricated into field-effect transistors using a gate-first process flow. The films were characterized using transmission electron microscopy, Rutherford backscattering spectrometry, and synchrotron x-ray diffraction. The results show the films remain amorphous even at temperatures of 1000 °C. The dielectric properties of LaxLu1−xO3 (0.125≤x≤0.875) thin films were evaluated as a function of film composition. The amorphous LaxLu1−xO3 thin films have a dielectric constant (K) of 23 across the composition range. The inversion thickness (Tinv) of the LaxLu1−xO3 thin films was scaled to

We discuss the structural and electrical properties of scaled 2 nm HfO2/SrO gate stacks. Thin SrO layers are deposited by molecular beam epitaxy onto (001) p-Si substrates as alternative passivating interfacial layers (ILs) to SiO2. X-ray photoelectron spectroscopy and transmission electron microscopy show that, despite some HfO2–SrO intermixing, the SrO IL acts as a barrier against HfxSiy and SiO2 formation during high-κ deposition. Electrical measurements on metal-oxide-semiconductor capacitors with TiN metal gates integrated in a low-temperature process flow reveal an equivalent oxide thickness of 5 A with competitive leakage current and hysteresis and a negative flat band voltage shift, suitable for n-channel transistors.

We demonstrate metal-gate-induced interfacial layer (IL) scaling using a HfO2 dielectric and clarify the kinetics underlying this process. The intrinsic IL scaling effect on electron mobility is separated from La and Al-induced dipole effects. We find that the mobility degradation for La-containing high-κ dielectrics is not due to the La-induced dipole but due to the intrinsic IL scaling effect, whereas the Al-induced dipole brings about additional mobility degradation. This unique nature of the La-induced dipole enables aggressive equivalent oxide thickness scaling down to 0.42 nm without extrinsic mobility degradation when combined with IL scaling.

We report on the stability of high-permittivity (high-k) TiO2 films incorporated in metal-oxide-silicon capacitor structures with a TiN metal gate electrode, focusing on oxygen migration. Titanium oxide films are deposited by either Ti sputtering [physical vapor deposition (PVD)] followed by radical shower oxidation or by plasma-enhanced atomic layer deposition (PEALD) from titanium isopropoxide (Ti{OCH(CH3)2}4) and O2 plasma. Both PVD and PEALD films result in near-stoichiometric TiO2 prior to high-temperature annealing. We find that dopant activation anneals of TiO2-containing gate stacks at 1000 °C cause 5 A or more of additional SiO2 to be formed at the gate-dielectric/Si-channel interface. Furthermore, we demonstrate for the first time that oxygen released from TiO2 diffuses through the TiN gate electrode and oxidizes the poly-Si contact. The thickness of this upper SiO2 layer continues to increase with increasing TiO2 thickness, while the thickness of the regrown SiO2 at the gate-dielectric/Si inter...