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The reliability degradation of HfO2-based devices under heavy ion irradiation is still an open question. In this letter, the ultrathin amorphous HfO2 gate stacks were irradiated by different types of swift heavy ions (SHIs). The fine structure of latent track in amorphous HfO2 is crystalline phase along the particle trajectory. The effects of latent track on the electrical properties were characterized by the high frequency capacitance-voltage (C-V) and the leakage current density-voltage (J-V) measurements. The quantitative relationship between microstructure changes and electrical properties provides a new method to estimate the threshold of the electronic energy loss ( ${(}\textit {dE}/\textit {dx}{)}_{\textsf {e}}$ ) for crystallization and allows for prediction of device sensitivity to SHIs irradiation.

Gamma-ray radiation effects on the SiO2/HfO2/Al2O3/HfO2/Al2O3 based charge trapping memory have been investigated. Capacitance–voltage (C–V) and deep level transient spectroscopy (DLTS) measurements were applied to study the change in electrical properties from total dose radiation. C–V results showed a negative shift of flat-band voltage while dc memory window degraded after gamma-ray radiation. For DLTS result, two original peaks were found degraded while two new peaks appeared after radiation. Both C–V and DLTS results show that Gamma ray leads to the degradation of trapping effect.

The performance of the ultra-thin body and buried oxide fully-depleted silicon-on-insulator metal-oxide-semiconductor field-effect-transistors based on a 22 nm technology node is investigated in this paper over an ultra-wide temperature range from 6 K to 550 K. The current–voltage (I–V) characteristics under wide temperature range conditions are shown, including the influence of the back-gate bias (V bg). The important electrical parameters, such as threshold voltage (V t), subthreshold swing, ON-state current (I on), and OFF-state current (I off), are extracted with temperature changes. From 550 K to 6 K, V t increased by 0.21 V, I off decreased nearly six orders of magnitude, and the gate-induced drain leakage current decreased by nearly eight orders of magnitude. The main physical mechanisms for the changing electrical performance with temperature are the variation of carrier concentration, mobility, and energy band. By utilizing a technology computer-aided design simulation, the temperature dependence of the device performance is discussed and analyzed.

For the state-of-art quantum technology applications, the effective control and high-speed reading of a large number of qubits require a combination of complementary metal-oxide-semiconductor (CMOS) circuits in cryogenic temperatures environments. In this letter, the electrical responses of bulk fin field effect transistor (FinFET) devices that could be applied in quantum controllers have been investigated under cryogenic conditions. The devices under test are high-k metal gate bulk FinFETs with 35 nm channel length. The electrical properties of the FinFET device are greatly optimized at cryogenic temperatures. As the temperature decreases, the FinFET exhibits a larger saturation current, smaller subthreshold swing, larger maximum transconductance, and smaller gate-induced drain leakage current. These results provide experimental evidence for the implementation of the FinFET in control systems for quantum chips in cryogenic environments.

N-type tunnel field effect transistors (TFETs) with Si1−xGex/Si hetero-junction in the ultra-shallow N+ pocket region have been fabricated. This paper investigates the total ionization dose (TID) effects on the electrical characteristics of these N-type TFET devices, including transfer and output characteristics, via a 60Co γ-ray irradiation source. TID has little impact on the on-state current for TFETs with and without P well. With the increase in total dose, however, a shift in the transfer characteristics, such as the off-state current and subthreshold slope is observed. Under the same TID condition, TFETs with P well exhibit more robustness as compared to TFETs without P well. The characteristics under room temperature and high temperature annealing conditions after irradiation are also investigated. The underlying mechanisms, such as the interplay among bulk trapped charge in gate oxide-induced inversion and interface trap-induced trap-assisted-tunneling, are identified by TCAD simulation and are discussed in detail.

The electrical responses of 55 nm silicon-oxide-nitride-oxide-silicon (SONOS) memory cells have been investigated under cryogenic conditions, and the changes of the read curves of SONOS in AC mode (programmed/erased with pulse voltage) and DC mode (programmed/erased with direct voltage sweeping) at low temperatures are compared. The experimental results show that with the decrease of temperature, the subthreshold swing of SONOS decreases, whereas the on-state current of SONOS increases. The difference in AC and DC operations causes the threshold voltage of the read curve to drift accordingly, leading to the different change in the memory window. However, in both modes of operations, the efficiencies of programming and erasing decrease at cryogenic temperatures. It is analysed that the reduction of programming efficiency at cryogenic temperatures is caused by the decrease in the quantity of pre-tunnelling electrons. The reduction in erasing efficiency is attributable to the suppression of the Poole-Frenkel effect at low temperatures, which makes it more difficult for electrons to be de-trapped.

Gamma-ray (γ-ray) irradiation effects on HfO2-based MOS capacitors have been studied. The capacitance-voltage (C-V) characteristic was measured at room temperature (300 K) to study the change of electrical properties in capacitors before and after irradiation with different doses. The shifts of midgap and flatband voltage and the decrease of accumulation capacitance shown that defects in the oxide and interface traps were indeed created during the gamma irradiation. Deep level transient spectroscopy (DLTS) was used to characterize the interfacial states introduced by irradiation. The activation energies, capture cross-sections and interface state densities were EC-0.1697 eV, EC-0.1929 eV; 7.371 × 10−16 cm2, 1.158 × 10−14 cm2; 1.814 × 1013 eV−1 cm2, 5.042 × 1013 eV−1 cm2 for the 1 Mrad(Si) and 5 Mrad(Si) samples, respectively. The peak shifted toward lower temperature when increasing pulse voltages (VP) in measuring DLTS spectra with fixed reverse voltage (VR). It indicated that interface defects have been formed during irradiation. With the increasing of irradiation dose, both of the capture cross section (σn) and the interface state density (Dit) increased. These results provide the basis to the researches and applications for the HfO2-based devices in the field of high-κ materials, irradiation effect, devices in radiation working environment.

The dependence of single event upset (SEU) on heavy ion energy was investigated for partially depleted silicon-on-insulator static random access memories. An unexpected phenomenon has been shown that the SEU cross sections decrease 70% with the increase of 12C ion linear energy transfer (LET) from 1.7 to 3.0 MeV/(mg/cm2). Furthermore, data from angled irradiations show that the SEU cross sections almost remain unchanged with the increase of effective LET in the subthreshold LET region. Geant4 simulation indicates that this anomalous trend of SEU cross sections is mainly attributed to energy effects of nuclear reactions between primary ions and material atoms. The SEU cross sections at subthreshold LET values are closely related to the energy of incident ions. Secondary Mg and Al ions produced by primary 12C ion nuclear reactions are the main ions to introduce the SEUs. A method is proposed for calculating the SEU cross sections induced by low LET heavy ions. The SEU cross sections calculated by Geant4 simulation with low LET heavy ions match well with the experimental results. The energy dependence of SEUs produced by low LET heavy ions implies that at accelerator-based SEU tests, the high-energy heavy ions with low LETs need to be utilized to estimate the contribution of indirect ionization to SEU cross sections for hardened devices with high-LET thresholds.

In this paper, we carried out detailed technology computer aided design simulations to investigate the radiation effects, e.g. total ionizing dose (TID) and single-event effects (SEEs), on direct current (DC) and radio frequency (RF) characteristics of the gate-all-around (GAA) nanosheet field-effect transistor (FET). The simulation model used is composed of seven-layer stacked GAA nanosheet FET with L g = 22 nm, which was implemented in this study. The open current and the drain-induced barrier lowering of the device are ∼3 mA μm−1 and 47 mV V−1, respectively. The results indicate that the TID have little influence on the DC and RF characteristics when the transistor is working in an open state. During the SEEs simulation, we considered three incident directions for the high energy particle, including the lateral direction of the channels, the vertical direction of the channels and the top of the channels. The influence of the particle injecting along the lateral and vertical directions of the channels shows stronger relation with the distance from the incident point compared to the influence of the particle from the top. Besides, the general influence of the particle injecting along the lateral directions of the channels is higher than the other two directions. The total injected charge of the particle injecting along the lateral direction, along the vertical direction and from the top are 3 fC, 1.4 fC and 2.1 fC, respectively. As compared to the fin FET, the GAA nanosheet has superior RF performances and less sensitivity to TID effect. This work can provide a guideline for the GAA nanosheet devices in aerospace and avionic RF applications.

Single-event-effects (SEEs) in integrated circuits (ICs) caused by galactic single ions are the major cause of anomalies for a spacecraft. The main strategies to decrease radiation failures for spacecraft are using SEEs less-sensitive devices and design radiation hardened ICs. High energy ion microbeam is one of the powerful tools to obtain spatial information of SEEs in ICs and to guide the radiation hardening design. The microbeam facility in the Institute of Modern Physics (IMP), Chinese Academy of Science (CAS) can meet both the liner energy transfer (LET) and ion range requirements for SEEs simulation experiments on ground. In order to study SEEs characteristics of ICs at this microbeam platform, a SEEs analysis system was developed. This system can target and irradiate ICs with single ions in micrometer-scale accuracy, meanwhile it acquires multi-channel SEE signals and maps the SEE sensitive regions online. A 4-Mbit NOR Flash memory was tested with this system using 2.2 GeV Kr ions, the radiation sensitive peripheral circuit regions for SEEs of 1 to 0 and 0 to 1 upset, multi-bit-upset and single event latchup have been obtained.

In this paper, a p-type tunnel field-effect transistor with source-pocket junction (SPTFET) has been presented. The source-pocket junction was formed at the interface between source and channel region using BF 2 high-angle implantation, which is helpful to reduce the tunneling distance and increase the carriers’ tunneling probability. Compared with the TFET without source-pocket junction, the fabricated SPTFET exhibits better electrical characteristics, such as large on-state current and small subthreshold swing.

In this paper, a p-type source-pocket tunnel field-effect (SPTFET) has been fabricated. The main feature of the device is that the p-type pocket was formed at the interface between source and channel region using BF 2 high-angle implantation. The source-pocket tunnel junction is helpful to reduce the tunneling distance and increase the tunneling probability. Compared with the TFET without source-pocket junction, the fabricated SPTFET exhibits better electrical characteristics, such as higher on-state current, larger on-off current ratio, smaller subthreshold swing and so on.

In this paper, a radiation-hardened resistive random-access memory (RRAM)-based non-volatile (NV) latch with a dual-interlocked storage cell is proposed and analyzed. The single-event effects (SEEs) of the proposed non-volatile latch are simulated and discussed. Simulations of the proposed element are based on a 0.18-μm complementary metal-oxide-semiconductor (CMOS) design kit for the peripheral circuit and the voltage threshold adaptive memristor (VTEAM) model for the RRAM. The simulation results indicate that the injected charge to induce a single-event upset (SEU) of the proposed NV latch is above 4.5 pC. As compared to the traditional RRAM based NV latch, the proposed NV latch is relatively immune to an SEU. This immunity from the SEU originates from the redundant storage nodes and interlocked feedback mechanism. Moreover, the area overhead of the proposed NV latch (8 transistors in the core storage element) are much lower than other radiation-hardened technology, e.g., TMR or FERST.

This work investigates the different sensitivities of an ion-sensitive field-effect transistor (ISFET) based on fully depleted silicon-on-insulator (FDSOI). Using computer-aided design (TCAD) tools, the sensitivity of a single-gate FDSOI based ISFET (FDSOI-ISFET) at different temperatures and the effects of the planar dual-gate structure on the sensitivity are determined. It is found that the sensitivity increases linearly with increasing temperature, reaching 890 mV/pH at 75 °C. By using a dual-gate structure and adjusting the control gate voltage, the sensitivity can be reduced from 750 mV/pH at 0 V control gate voltage to 540 mV/pH at 1 V control gate voltage. The above sensitivity changes are produced because the Nernst limit changes with temperature or the electric field generated by different control gate voltages causes changes in the carrier movement. It is proved that a single FDSOI-ISFET can have adjustable sensitivity by adjusting the operating temperature or the control gate voltage of the dual-gate device.

The effects of proton radiation on TiN/Zr-doped-HfO2(HZO)/Al2O3/P+-Ge ferroelectric tunneling junctions are investigated in the present work. The electrical characteristics are measured before and after different proton fluences. The remanent polarization exhibits negligible change, which demonstrates the proton radiation immunity of the ferroelectric material HZO. However, the capacitance, leakage current, endurance, and read current characteristics show obviously changed with the increase of proton fluence. The main reason for this is that proton radiation causes positive fixed charges to form in the Al2O3 layer, interface charges to form in Al2O3/Ge and the effective carrier concentration to reduce in the Ge substrate.

A novel vertical tunnelling field-effect transistor (TFET) based on silicon-oxide-nitride-oxide-silicon (SONOS) non-volatile memory device, named as VT-SONOS, is proposed and investigated using TCAD simulations. Different from traditional planar TFET-based SONOS memory, the VT-SONOS device is programmed via band-to-band tunnelling for vertical pocket and Fowler–Nordheim tunnelling for both pocket/bottom oxide (OXb) and channel/OXb regions, which leads to a steeper subthreshold swing (SS) and a larger on-state current (I ON). The device structure is constructed using Sentaurus TCAD tools, and I D–V G characteristics were extracted using TCAD tools. Obtained SS value is 102.09 mV dec−1, while the I ON was 3.02 × 10−4 A. The memory window was 2.95 V, showing more dependence on programming pulse height (V gp) than erasing pulse height (V ge). Furthermore, 10-year retention characteristics were studied to investigate critical reliability issue. About 60% of the initial trapped charges remained in the device after unbiased 3.15 × 108 s (10 years) storage.

A novel radiation-hardened-by-design (RHBD) structure to reduce the single event transient (SET) amplitude in analog circuits is presented in this paper. This structure features an SET isolation technique, which contains a sensor and a switch. The sensor turns off the switch when it detects a voltage transient at the sensitive node, in which case the core circuit is temporarily isolated from the output. Once the voltage at the sensitive node recovers, the sensor turns on the switch again in order to connect the core circuit to the output. This RHBD technique was validated based on a typical bandgap reference circuit, which was fabricated in the IBM 130 nm technology. The simulation results demonstrated a significant reduction in the SET amplitude, which was further verified with the pulsed laser. The additional sensor and the switch in the circuit only produce a minor amount of additional power dissipation if they are properly chosen. The area overhead is rendered negligible by means of selecting the appropriate sizes of transistors for the RHBD structure.

The single event effects (SEEs) on ferroelectric Hf0.5Zr0.5O2 capacitor-based non-volatile static random access memory (nvSRAM) were investigated by simulation. A nvSRAM cell integrated with two ferroelectric Hf0.5Zr0.5O2 capacitors is proposed in this study. A macro-model of the ferroelectric Hf0.5Zr0.5O2 capacitor, extracted from the real fabricated devices, is utilized for simulation analysis. Fundamental store and recall operations of the proposed nvSRAM design have been demonstrated. An independent double exponential current source was utilized and injected into specific circuit nodes to simulate the heavy ion induced single event transient current. The simulation results show that the transient pulse current is possible to upset the logic state of the memory cell from 1 to 0, but whether it can recover in a short time period after the upset errors depends on the exact value of linear energy transfer for the injected particles. In addition, increasing the remnant polarization (P r) and decreasing the coercive voltage (V c) and film thickness of ferroelectric capacitors can mitigate the influence of SEEs, which provides guidance for process hardening techniques aiming at space applications.

Tunnel field-effect transistors (TFETs) are strong candidates for ‘Internet of Things’ electronic devices, due to their ultra-low power consumption. In this work, we propose a novel nanoscale silicon-on-insulator double-gate ferroelectric tunneling field-effect transistor (SOI DG-FeTFET), and single-event-transient (SET) effects are investigated by means of two-dimensional technology computer-aided design simulations. In addition, we perform systematic analysis and comparison with a silicon-on-insulator double-gate ferroelectric field-effect transistor (SOI DG-FeET) . The simulation results show that the peak value of the drain transient current achieved by our DG-FeTFET is up to 2.72 × 10–4 A at 10 MeV·cm2 mg−1, which is much higher than the on-state current (I on) ∼ 7.63 × 10−5 A at V d = 0.5 V. Moreover, our results show that the DG-FeTFET is more susceptible to SET effects than FeFET. The results also show that the bipolar amplification effect can be neglected, and that the drift-diffusion mechanism is dominant in the carrier collection process in the DG-FeTFET. The transient responses of the single event effect are also strongly correlated with the strike location of heavy ions, with the most sensitive part being close to the area where interband tunneling occurs and the electric field is the strongest. These analyses may prove relevant for applications SOI DG-FeTFETs/FeFETs in environments where radiation is present.

In this paper, a portable real-time sensing device was built for Concanavalin A (Con A) and glucose detection using a smartphone. The ion-sensitive field-effect transistor (ISFET) functioning at a low working point was selected as a small-size, low-power transducer, and dextran-capped silver nanoparticles (Dex-AgNPs) served as sensitive nanoprobes on the ISFET gate. Using the affinity between Con A and carbohydrates, Con A can be captured, and thus directly detected by the ISFET/Dex-AgNPs unit; then glucose can be determined indirectly by removing Con A from the ISFET/Dex-AgNPs/Con A unit via competition with dextran. The mechanism of this competition does less harm to the sensor, allows the reusability of the sensing device, and overcomes the Debye screening of the FET device in saline solutions. Powered by a button cell, the handheld device attains excellent Con A (0.16 ng mL−1) and glucose (10 nM) detection limit, and can practically be used for at least 20 days.

This work studied the effect of annealing process and mechanical clamping process on the electrical properties of Hf 0.5 Zr 0.5 O 2 (HZO) ferroelectric capacitors under electrical tests, and the physical mechanism was analyzed.

International audience; The synergetic effects of High Temperature Gate Bias (HTGB) (0 h, 162 h, 332 h) and Total Ionization Dose (TID) radiation (0 kGy, 1 kGy, 3 kGy, 5 kGy, 10 kGy) response of 1200 V commercial SiC power MOSFETs were studied, along with annealing characteristics at room temperature. Electrical parameters were investigated with Current-Voltage (I-V) and Capacitance-Voltage (C-V) measurements. Results show that Gate Threshold Voltage (Vth) is sensitive to combination of HTGB and TID. Gate Leakage Current (Igss) and Vth increase while Input Capacitance (Ciss) decrease after HTGB stress. Drain-Source Leakage Current (Idss) and Igss rise up due to TID radiation while Ciss and Vth decrease. HTGB mitigates the shift of parameters due to radiation to some extent, especially Idss. No obvious annealing effect was observed at room temperature for one week on all Device Under Tests (DUTs) in this work.

Total ionizing dose (TID) induced upset errors in Hf02-based resistive-random-access-memory (RRAM) with 1T1R storage cell structure are investigated. Radiation-induced leakage current in the access transistors on the same bit-lines causes a read decision failure and bit errors observed during TID irradiation experiments. This is verified by testkeys and HSPICE simulations based on the actual circuit structure of the 1 Mb RRAM.

Electronic systems tend to observe single event upsets (SEUs) when exposed to radiation environments in space. In order to detect and position these errors in on-orbit systems such as Field-programmable gate array (FPGA) and System on chip (SoC), we present a novel independent SEU detector which can be placed anywhere on the printed circuit board (PCB). By utilizing both the column single event effect (SEE) current sensor and the row SEE current sensor in the system, the location of high-energy particles can be precisely located with the accuracy better than 50 μm. By changing the clock frequency, we can greatly improve the time resolution of monitoring high energy particles. Combined with the counting position of particles, the incident rate of space high-energy particles can be obtained. By changing the critical charge of SEE current sensor or the width of depletion layer, the LET value of high-energy particle in the incident space can be effectively improved, and the resolution of linear energy transfer (LET) value can reach 1MeV*cm2/mg. we are able to obtain such information as incident position, incident time, fluence, flux and LET value of high-energy particles.

An experimental investigation of the single event upset (SEU) susceptibility for heavy ions at tilted incidence was performed. The differences of SEU cross-sections between tilted incidence and normal incidence at equivalent effective linear energy transfer were 21% and 57% for the silicon-on-insulator (SOI) static random access memories (SRAMs) of 0.5 μm and 0.18 μm feature size, respectively. The difference of SEU cross-section raised dramatically with increasing tilt angle for SOI SRAM of deep-submicron technology. The result of CREME-MC simulation for tilted irradiation of the sensitive volume indicates that the energy deposition spectrum has a substantial tail extending into the low energy region. The experimental results show that the influence of edge effects on SEU susceptibility cannot be ignored in particular with device scaling down.

This paper designed a 1-Mb HfOx-based embedded Resistive Random Access Memory (RRAM) device with a one-transistor-one-resistor (1T1R) structure, and systematically investigated its working temperature range. It noted that this embedded RRAM macro has a 1.6X working temperature range than previous design for some extreme environment. Using the peripheral-assisted technique, it can enable the error rate of the RRAM macro under 0.5% which can reduce the complexity of ECC function. Experimental results show that, the RRAM macro achieves a wider work temperature range (between −55°C and 150°C), which improves the reliability of the entire embedded RRAM macro and has a high robustness as well.

TID and SEE effects on 1 Mb HfO2-based RRAM with 1T1R structure are investigated. TID-induced leakage current causes ‘0-1’ type error bits. SELs in peripheral circuits occur, but no SEUs in memory array have been observed.

This paper presents a new SEU-tolerant latch design based on Quatro and NMOS feedback transistors. By using these feedback transistors, the SEU susceptibility is decreased because of the cutoff feedback loop. Simulation results demonstrate that the proposed design is immune to static single node upsets. The proposed latch and the reference Quatro were designed and fabricated on a 130 nm process. The test chip was exposed to heavy ions at the TAMU Cyclotron facility. The testing results show that the proposed design has a higher upset LET threshold and lower cross-section when compared to the reference latch. Its lower SEU vulnerability comes with small area penalty.

Single-event upsets in 1T1R Resistive Random Access Memory (RRAM) structures are experimentally demonstrated by generating current transients in the access transistors of the memory cells. The relationship between the single-event upset threshold of the RRAM and the applied voltage is exponential, which is verified using TPA laser analysis and heavy-ion irradiation. Multiple-Event Upsets (MEUs) also occur, where individual ions incrementally change the RRAM's resistance until their cumulative effect causes an upset. Single-event models are presented that allow direct correlation of the voltage across the RRAM, caused by the ion-generated current transient, and the change in RRAM resistance. The RRAM is vulnerable only in the high resistance state, when a voltage capable of writing to the cell is applied to the bit line. This is approximately 0.5% of the memory element's operation time, leading to relatively low projected upset rates.

The total ionizing dose (TID) effects of X-ray irradiation on graphene/HfO2/Si (Gr/HfO2/Si) Schottky diodes were investigated. The I-V characteristics were studied in detail with different bias conditions during TID irradiation. An increase in the ideality factor and decrease in the Schottky barrier height were observed. Compared with traditional graphene/Si (Gr/Si) Schottky structures, the degradation of electrical characteristics can be effectively suppressed by adding a HfO2 insertion layer between graphene and the Si substrate.

A high-read-reliability and ultra-low-power consumption sense amplifier for the read path of a spin-transfer torque magnetic random-access memory is presented. The reliability in this research represents read accuracy of the memory. The basic concept is that power is supplied by capacitors. The proposed circuit uses 28 nm CMOS technology with an 1.2 V power supply. Simulation results show that when the bit-line voltage is 200 mV, the sensing margin is about 100 mV with reading data “0” and 160 mV with reading data “1”. The read energy is about 1 pJ/bit, which is 10 times lower than that achieved using the traditional scheme.

Experiments on total ionizing dose (TID) by cobalt-60 and single event effects (SEE) by pulsed laser and heavy ions were conducted on a 4 Mb commercial ReRAM from Fujitsu. The bit cell features two-transistor-two-resistor (2T2R) architecture and a TaOx-based ReRAM stack. The TID failure levels and recovery trend after annealing are strongly related to operation modes. The static mode tolerates a TID dose up to 130 krad(Si), whereas the dynamic mode fails during a TID range from 20 to 70 krad(Si). The cross-section of single event function interruption (SEFI) in ReRAM was determined by heavy ions and confirmed with a pulsed laser sensitivity scan. The threshold LET for the most sensitive region is less than 5 MeV∙cm2/mg. Failure mechanisms are discussed in detail. These results and discussions are useful for developing radiation-hard ReRAM for use in space applications.

The effects of γ-ray irradiation on graphene/n–Si Schottky diodes are investigated. The electrical characteristics are measured before and after serial radiation doses in a dark environment. Experimental results show an increase of reverse current and ideality factor, while the Schottky barrier height decreases. The XPS results indicate that γ-ray irradiation mainly leads to a break in Si–O and C=C bonds; the C dangling bonds can combine with dangling O on the surface of SiO2 while leaving Si dangling bonds in SiO2. These Si dangling bonds seriously degrade the electrical performance of the device.

This paper investigates total-ionizing dose effects on the electrical characteristics of HfO2/Hf-based bipolar resistive-random-access-memory (RRAM) devices. 10-keV x-ray irradiation does not cause significant changes in resistance at levels up to 7 Mrad( SiO2). Excess carriers generated by x-ray irradiation in the HfO2 layer recombine or are trapped at defect sites in the HfO2 layer or at interfaces between layers. They have no effect, however, on the conductive path of the RRAM devices. 1.8 MeV proton irradiation causes resistance degradation through simultaneous introduction of oxygen vacancies and displacement damage. TRIM simulations are used to explain the physical mechanisms of the radiation-induced damage. The devices are promising for radiation-hardened memory applications.

The effects of X-ray and proton radiation on a LiNbO2 analog memristor are investigated by I-V hysteresis, Electrochemical Impedance Spectroscopy, low-frequency AC voltage, and X-ray diffraction analysis. Both electrical and structural characterization of an irradiated memristor show that irradiation leads to an increased level of defects in the LiNbO2 crystalline lattice. These radiation-induced defects facilitate faster lithium movement as shown by electrochemical impedance spectroscopy measurements on the as-grown and irradiated memristor. X-ray radiation improves ionic motion in the bulk of the device and increases the ionic resistance at the LiNbO2-metal interface. In the case of proton radiation, the memristance response improves due to an increase in ionic motion in the bulk and at the interfaces. It is also shown by Monte Carlo simulations that proton irradiation of LiNbO2 results in structural damage, which was verified experimentally by an X-ray diffraction study.

A new model for assessing NBTI and PBTI induced time-dependent variability under practical operation workloads is proposed. The model is based on a realistic understanding of different types of defects and has excellent predictive capability, as validated by comparison with experimental data. In addition, a new fast wafer-level test scheme for parameter extraction is developed, reducing test time to 1 hour/device and significantly improving the efficiency for variability tests of nanoscale devices. The model is implemented into a commercial simulator and its applicability for circuit level simulation is demonstrated.

This paper presents the 3 MeV proton irradiation results of a 16Mb commercial MRAM. The total ionizing dose(TID) effects induced by proton irradiaton and the following room temperature annealing behaviors are analyzed in detail. Read bit errors and electrical failures were observed when the proton fluence was accumulated to 2.5×1011 particles/cm2. The peripheral circuits are more sensitive to proton irradiation. These results are useful for hardening MRAM designs aiming at space-borne applications.

The sensitivities of a Monte Carlo simulation tool (PRESTAGE) to variation of input parameters are studied. When calculating the single event upset cross-section induced by proton direct ionization, PRESTAGE calculation results significantly change with changes in the sensitive volume and passivation layer thicknesses. When calculating cross-sections induced by proton indirect ionizations, PRESTAGE is not sensitive to the change of the passivation over layer thickness, and the calculation results stay constant as the thickness of the sensitive volume varies within the range of 0.05∼2 µm. In other ranges, the calculated cross-section decreases with the increasing of the sensitive volume thickness. These study results provide important references for the engineering application of PRESTAGE.

The impacts of total ionizing dose by cobalt60 on the 4 Mb Serial Peripheral Interface NOR Flash memory are studied in detail. Electrical parameters degradation and unidirectional upsets are demonstrated with physical explanations.

In this summary, the resistive random access memory (RRAM) with the structure of Pt/HfO 2 /Ti is investigated for applications in radiation circumstance. The heavy ion 86Kr26+ of HIRFL (The Heavy Ion Research Facility in Lanzhou) is used as the radiation source. The energy of 86Kr26+ is 25 MeV/u, the LET is 37.6 MeV/(cm2/mg), and the fluence of 5e11 is achieved after 2 hours radiation. Basic performance of the Pt/HfO 2 /Ti is compared before and after radiation. An obvious decrease is shown in the original resistance value after radiation, and the forming process is no longer needed. The HRS, LRS, transition voltage and endurance are still stable after radiation.

The effects of irradiation on graphene nano-disc (GND) non-volatile memory devices were investigated by 60Co γ-rays. The electrical characteristics of the devices were measured before and after γ-irradiation with doses ranging from 50 to 1000 krad (Si). The electrical properties of the devices in the pristine and erased states were nearly unchanged in response to ionizing doses up to 1 Mrad (Si). However, the electrical properties of the devices in the programmed states were significantly degraded with increasing dose levels. The degradation was mainly the result of photoemission, positive charge traps in the surrounding oxides, and holes injected into the GND trapping layer. This study improves the understanding of radiation effects on graphene-based nano-electronic devices.

Upset errors in 90-nm 64 Mb NOR-type floating-gate Flash memory induced by accelerated 129Xe and 209Bi ions are investigated in detail. The linear energy transfer covers the range from 50 to 99.8 MeV/(mg/cm2). When the memory chips are powered off during heavy ions irradiation, single-event-latch-up and single-event-function-interruption are excluded, and only 0->1 upset errors in the memory array are observed. These error bit rates seem very difficult to achieve and cannot be simply recovered based on the power cycle. The number of error bits shows a strong dependence on the linear energy transfer (LET). Under room-temperature annealing conditions, the upset errors can be reduced by about two orders of magnitude using rewrite/reprogram operations, but they subsequently increase once again in a few minutes after the power cycle. High-temperature annealing can diminish almost all error bits, which are affected by the lower LET 129Xe ions. The percolation path between the floating-gate (FG) and the substrate contributes to the radiation-induced leakage current, and has been identified as the root cause of the upset errors of the Flash memory array in this work.

RRAM exhibit highly stable characteristics under TID radiation. But different radiation effects are shown in the RRAM based different oxide. The radiation effects in RRAM based HfO2 and SiO2 are test and analyzed.

Body bias effects on the laser-induced transient current peak, duration, collected charge and amplification factor are experimentally evaluated. The results are promising for radiation-hardened circuit design.

Extra charge will be generated and deposited into the cell when an energetic ion strikes the SOI SRAM. The sensitive regions will collect the deposited charge. This may upset the logic values stored in SRAM. The Geant4 is a very useful tool to simulate the process above. The GDML (Geometry Description Markup Language) file can be used to model the geometry of device or circuit in Geant4. In the paper, we used the GDML file to construct the 3-D geometry model of SOI SRAM for the simulation of heavy ion irradiation. And the Single Event Upset (SEU) Cross-Section is used to estimate the hardening levels of SRAM.