Heavy ion induced upset errors in 90-nm 64 Mb NOR-type floating-gate Flash memory

Upset errors in 90-nm 64 Mb NOR-type floating-gate Flash memory induced by accelerated 129Xe and 209Bi ions are investigated in detail. The linear energy transfer covers the range from 50 to 99.8 MeV/(mg/cm2). When the memory chips are powered off during heavy ions irradiation, single-event-latch-up and single-event-function-interruption are excluded, and only 0->1 upset errors in the memory array are observed. These error bit rates seem very difficult to achieve and cannot be simply recovered based on the power cycle. The number of error bits shows a strong dependence on the linear energy transfer (LET). Under room-temperature annealing conditions, the upset errors can be reduced by about two orders of magnitude using rewrite/reprogram operations, but they subsequently increase once again in a few minutes after the power cycle. High-temperature annealing can diminish almost all error bits, which are affected by the lower LET 129Xe ions. The percolation path between the floating-gate (FG) and the substrate contributes to the radiation-induced leakage current, and has been identified as the root cause of the upset errors of the Flash memory array in this work.