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This paper investigates the thermodynamic driving force of transient negative capacitance (NC) in the series circuit of the resistor and ferroelectric capacitor (R-FEC). We find that the widely used Landau-Khalatnikov (L-K) theory, that is, the minimum of the Gibbs free energy, is inapplicable to explain the transient NC. The thermodynamic driving force of the transient NC phenomenon is the minimum of the difference between the elastic Gibbs free energy and the electric polarization work. The appearance of the transient NC phenomenon is not due to the widely accepted view that the ferroelectric polarization goes through the negative curvature region of elastic Gibbs free energy landscape (Ga). Instead, the transient NC phenomenon appears when the energy barrier of Ga disappears. The transient NC is dependent on both the intrinsic ferroelectric material parameters and extrinsic factors in the R-FEC circuit., 31 pages, 7 fiures, 1 table

Heavily doped polysilicon layers have been widely used in the fabrication of microelectromechanical systems (MEMS). However, the investigation of high selectivity, anisotropy, and excellent uniformity of heavily doped polysilicon etching is limited. In this work, reactive ion etching of undoped and heavily doped polysilicon-based hydrogen bromide (HBr) plasmas have been compared. The mechanism of etching of heavily doped polysilicon is studied in detail. The final results demonstrate that the anisotropy profile of heavily doped polysilicon can be obtained based on a HBr plasma process. An excellent uniformity of resistance of the thermocouples reached &plusmn, 2.11%. This technology provides an effective away for thermopile and other MEMS devices fabrication.

We experimentally investigate the effect of post-deposition annealing on the charge distribution of a metal-oxide-semiconductor capacitor with a TiN/HfO2/SiO2/Si gate structure. We decoupled interfacial charges at the SiO2/Si and HfO2/SiO2 interfaces; bulk charges in HfO2; and the dipole formation at the HfO2/SiO2 interface. The interfacial charges at the HfO2/SiO2 interface decreased and the dipole increased after H2 or N2 annealing. Oxygen dangling bonds are the physical origin of the charges at the HfO2/SiO2 interface. The interfacial charges at the SiO2/Si interface and the bulk charges in HfO2 are almost unchanged.

Semiconductor nanowires have great application prospects in field effect transistors and sensors. In this study, the process and challenges of manufacturing vertical SiGe/Si nanowire array by using the conventional lithography and novel dry atomic layer etching technology. The final results demonstrate that vertical nanowires with a diameter less than 20 nm can be obtained. The diameter of nanowires is adjustable with an accuracy error less than 0.3 nm. This technology provides a new way for advanced 3D transistors and sensors.

The international technology roadmap of semiconductors (ITRS) is approaching the historical end point and we observe that the semiconductor industry is driving complementary metal oxide semiconductor (CMOS) further towards unknown zones. Today’s transistors with 3D structure and integrated advanced strain engineering differ radically from the original planar 2D ones due to the scaling down of the gate and source/drain regions according to Moore’s law. This article presents a review of new architectures, simulation methods, and process technology for nano-scale transistors on the approach to the end of ITRS technology. The discussions cover innovative methods, challenges and difficulties in device processing, as well as new metrology techniques that may appear in the near future.

Ge has been an alternative channel material for the performance enhancement of complementary metal–oxide–semiconductor (CMOS) technology applications because of its high carrier mobility and superior compatibility with Si CMOS technology. The gate structure plays a key role on the electrical property. In this paper, the property of Ge MOSFET with Al2O3/GeO x /Ge stack by ozone oxidation is reviewed. The GeO x passivation mechanism by ozone oxidation and band alignment of Al2O3/GeO x /Ge stack is described. In addition, the charge distribution in the gate stack and remote Coulomb scattering on carrier mobility is also presented. The surface passivation is mainly attributed to the high oxidation state of Ge. The energy band alignment is well explained by the gap state theory. The charge distribution is quantitatively characterized and it is found that the gate charges make a great degradation on carrier mobility. These investigations help to provide an impressive understanding and a possible instructive method to improve the performance of Ge devices.

This paper proposed, for the first time, that the band-edge effective work functions (EWFs) are achieved by employing PH3 plasma doping (PLAD) TiN metal gate for nMOS device application under replacement metal gate and high dielectric constant (k) dielectric/metal gate last nMOS device. The effects of PLAD energy, dose, gas mixture, and postdoping cleaning procedure on the EWF, EOT, and properties of TiN/HfO2/ILSiO2 gate-stack are investigated; the corresponding possible mechanisms are discussed. Suitable low threshold voltages of nMOSFETs are obtained, while shrinking the EOT. It reduces the corner effect on trench gate doping uniformity, which is induced by shadowing effect in the beam-line implantation technology, to a minimum. It has the potential for the further aggressively scaled 3-D CMOS device and beyond application.

We study the influence of the thermodynamic coefficients on transient negative capacitance for the Zr-doped HfO2 (HZO) ferroelectric capacitors by the theoretical simulation based on the Landau–Khalatnikov (L-K) theory and experimental measurement of electrical properties in the resistor-ferroelectric capacitor (R-FEC) circuit. Our results show that the thermodynamic coefficients α, β and γ also play a key role for the transient NC effect besides the viscosity coefficient and series resistor. Moreover, the smaller coefficients α and β, the more significant the transient NC effect. In addition, we also find that the thermodynamic process of transient NC does not obey the generally accepted viewpoint of Gibbs free energy minimization.

The HfO2-based ferroelectric field effect transistors (FeFET) have been widely studied for their ability in breaking the Boltzmann limit and the potential to be applied to low-power circuits. This article systematically investigates the transient response of negative capacitance (NC) fin field-effect transistors (FinFETs) through two kinds of self-built test schemes. By comparing the results with those of conventional FinFETs, we experimentally demonstrate that the on-current of the NC FinFET is not degraded in the MHz frequency domain. Further test results in the higher frequency domain show that the on-state current of the prepared NC FinFET increases with the decreasing gate pulse width at pulse widths below 100 ns and is consistently greater (about 80% with NC NMOS) than the on-state current of the conventional transistor, indicating the great potential of the NC FET for future high-frequency applications.

The charge neutrality level of SiO2 is experimentally extracted by investigating conduction band offset (CBO) of SiO2/Si stack with different SiO2 thicknesses using X-ray photoelectron spectroscopy. The CBO is found to be dependent on SiO2 thickness. The CNL of SiO2 is determined to be 4 eV above valence band maximum by modeling the CBO vs. thickness of SiO2 using gap states and charge neutrality level based model.

This paper presents a numerical simulation study investigating the effect of buried oxide on surface roughness scattering limited hole mobility ( $\mu _{\mathsf {SR}}$ ) in ultrathin germanium-on-insulator (GeOI) MOSFETs, for the first time. The simulation considers wave function penetration at channel/oxide interface and nonlinear dependence of scattering matrix element on surface fluctuation. Three types of buried oxide materials are compared (GeO2, SiO2, and Si3N4). The $\mu _{\mathsf {SR}}$ increases in the order of SiO2 $\mu _{\mathsf {SR}}$ on buried oxide material is due to surface fluctuation scattering from backside Ge/buried oxide interface. Our simulation results show that Si3N4 and GeO2 are beneficial as buried oxide for mobility enhancement in GeOI MOSFETs, compared with conventional SiO2 as buried oxide. Our findings provide an insight into further improving mobility characteristic.

Oxidation kinetics of germanium surface by ozone at low temperature (≤400 °C) is experimentally investigated. The growth process contains two regions: initial linear growth region and following parabolic growth region. The GeOx thickness vs. oxidation time plot obeys the well-known Deal-Grove or linear parabolic model. The linear growth region contains reaction of oxygen atoms with surface bond and back bonds of outmost Ge layer. And the activation energy is experimentally estimated to be 0.06 eV. Such small activation energy indicates that the linear growth region is nearly barrier-less. The parabolic growth region starts when the oxygen atoms diffuse into back bonds of second outmost Ge layers. And the activation energy for this process is found to be 0.54 eV. Furthermore, in the ozone oxidation it is not O3 molecules but O radicals that go through the GeOx film.

The origin of fixed charges and dipole in GeO x /Al 2 O 3 gate stack deposited by atomic layer deposition was experimentally investigated. Three kinds of charges in the gate stacks: the Ge/GeO x interface charges $Q_{\mathit{1}}$ , GeO x /Al 2 O 3 interface charge $Q_{\mathit{2}}$ , and GeO x /Al 2 O 3 interface dipole $Q_{dipole}$ were obtained by C-V characteristics. The XPS was used to explore the interfacial defect at both the Ge/GeO x and GeOx/Al 2 O 3 interfaces. It is found that positive charges $Q_{\mathit{1}}$ at the Ge/GeO x interface is due to the oxygen vacancy, negative charges $Q_{\mathit{2}}$ at the GeO x /Al 2 O 3 interface is due to the oxygen dangling bonds, $Q_{dipole}$ is due to the band alignment at the GeO x /Al 2 O 3 hetero-interface, respectively.

Hole mobility degradation due to the Coulomb scattering from the Geo x /Al 2 O 3 gate stack of Ge pMOSFET is investigated. There are fixed charges at the Ge/GeOxand Geo x /Al 2 O 3 interfaces and dipole at the Geo x /Al 2 O 3 interface. These charges can be changed by N 2 and O 2 PDA. The hole mobility is mainly affected by the Ge/GeO x interface charges and Geo x /Al 2 O 3 interface dipole.

We comprehensively studied the interfacial charges origin in the GeO x /Al 2 O 3 stack based on Ge substrate by ozone oxidation. The X-ray photoelectron spectroscope (XPS) was used to explore the interfacial defect at both the Ge/GeO x and GeO x /Al 2 O 3 interfaces. The results show that oxygen vacancies at the Ge/GeO x interface, while oxygen dangling bonds at the GeO x /Al 2 O 3 interface. This work is valuable to enhance the interface quality and performance of Ge-based devices.

Electrostatic potential distribution of Al2O3/Ge structure is investigated vs. Al2O3 thickness by X-ray photoelectron spectroscopy (XPS). The electrostatic potential distribution is found to be Al2O3 thickness dependent. This interesting phenomenon is attributed to the appearance of gap states on Al2O3 surface (GSAl2O3) and its higher charge neutrality level (CNL) compared with the CNL of gap states at Al2O3/Ge interface (GSAl2O3/Ge), leading to electron transfer from GSAl2O3 to GSAl2O3/Ge. In the case of thicker Al2O3, fewer electrons transfer from GSAl2O3 to GSAl2O3/Ge, resulting in a larger potential drop across Al2O3 and XPS results.

In this paper, the technology of recessed embedded SiGe (e-SiGe) source/drain (S/D) module is optimized for the performance enhancement in 22 nm all-last high-k/metal-gate (HK/MG) pMOSFETs. Different Si recess-etch techniques were applied in S/D regions to increase the strain in the channel and subsequently, improve the performance of transistors. A new recess-etch method consists of a two-step etch method is proposed. This process is an initial anisotropic etch for the formation of shallow trench followed by a final isotropic etch. By introducing the definition of the upper edge distance (D) between the recessed S/D region and the channel region, the process advantage of the new approach is clearly presented. It decreases the value of D than those by conventional one-step isotropic or anisotropic etch of Si. Therefore, the series resistance is reduced and the channel strain is increased, which confirmed by the simulation results. The physical reason of D reducing is analyzed in brief. Applying this recess design, the implant conditions for S/D extension (SDE) are also optimized by using a two-step implantation of BF2 in SiGe layers. The overlap space between doping junction and channel region has great effect on the device’s performance. The designed implantation profile decreases the overlap space while keeps a shallow junction depth for a controllable short channel effect. The channel resistance as well as the transfer ID–VG curves varying with different process conditions are demonstrated. It shows the drive current of the device with the optimized SDE implant condition and Si recess-etch process is obviously improved. The change trend of on–off current distributions extracted from a series of devices confirmed the conclusions. This study provides a useful guideline for developing high performance strained PMOS SiGe technology.

As an emerging developing technique for next-generation lithography, directed self-assembly (DSA) of block copolymer (BCP) has attracted numerous attention and has been a potential alternative to supplement the intrinsic limitations of conventional photolithography. In this work, the self-assembling properties of a lamellar diblock copolymer poly(styrene-b-methylmethacrylate) (PS-b-PMMA, 22k-b-22k, L 0 = 25 nm) on Si substrate and an atomic layer deposition (ALD)-assisted pattern transfer technology for the application of DSA beyond 16/14 nm complementary metal oxide semiconductor (CMOS) technology nodes, were investigated. Firstly, two key processing parameters of DSA, i.e . annealing temperatures and durations of BCP films, were optimized to achieve low defect density and high productivity. After phase separation of BCP films, self-assembling patterns of low defect density should be transferred to the substrate. However, due to the nano-scale thickness and the weak resistance of BCP films to dry etching, it is nearly impossible to transfer the BCP patterns directly to the substrate. Therefore, an ALD-based technology was explored in this work, in which deposited Al 2 O 3 selectively reacts with PMMA blocks thus hardening the PMMA patterns. After removing PS blocks by plasma etching, hardened PMMA patterns were left and transferred to underneath SiO 2 hard mask layer. Using this patterned hard mask, nanowire array of 25 nm pitch were realized on Si substrate. From this work, a high-throughput DSA baseline flow and related ALD-assisted pattern transfer technique were developed and proved to have good capability with the mainstream CMOS technology.

TiAlX (X = N or C) films are developed by thermal atomic layer deposition (ALD) technique as metal gate. The TiAlX films are deposited by using four different combinations of precursors: A: TiCl4–NH3–TMA–NH3, B: TiCl4–TMA–NH3, C: TiCl4–NH3–TMA and D: TiCl4–TMA. The physical characteristics of the TiAlX films such as chemical composition, growth rate, resistivity and surface roughness are estimated by X-ray photoemission spectroscopy, scanning electron microscope, four point probe method and atomic force microscopy respectively. Additionally, the electrical characteristics of the TiAlX films are investigated by using metal–oxide–semiconductor (MOS) capacitor structure. It is shown that NH3 presence in the reaction makes the film more like TiAlN(C) while NH3 absence makes the film more like TiAlC. The TiAlC film deposited by TiCl4–TMA has effective work function close to mid-gap of Si, which is rather potential for low power FinFET device application.

Attainment of dual band-edge effective work functions by using a single metal gate and single high k gate dielectric via P/BF 2 implantation into a TiN metal gate for HP HKMG CMOS device applications are investigated under a gate-last process flow for the first time. The flat band voltage ( V FB ) modulations of about −750 mV/570 mV for N-/P-type MOS device with P/BF 2 implanted TiN/HfO 2 /ILSiO 2 gate stack are obtained respectively in the experiment range. Suitable low threshold voltages of CMOSFETs are gotten while simultaneously shrinking the EOT. The effects of P/BF 2 ion implantation energy, dose and TiN gate thickness on the properties of implanted TiN/HfO 2 /ILSiO 2 gate stack are studied, the possible mechanisms are discussed. This technique has been successfully integrated into the fabrications of aggressively scaled HP HKMG CMOSFETs and 32 CMOS frequency dividers under a gate-last process flow.

This paper proposed, for the first time, that the dual band-edge effective work functions are achieved by employing a single metal gate (MG) and single high- $k$ (HK) dielectric via ion implantation into a TiN MG for HP CMOS device applications under a gate-last process flow. The P/BF2 ion-implanted TiN/HfO2/ILSiO2 gate-stack does not degrade the gate leakage, reliability, and carrier mobility, and reduces the effective oxide thickness. The impact of P/BF2 ion implant energy, dose, and TiN gate thickness on the properties of implanted TiN/HfO2/ILSiO2 gate-stack is studied, and the corresponding possible mechanisms are discussed. This technique has been successfully applied to the replacement MG and HK/MG last process flow to fabricate HP CMOSFETs and CMOS 32 frequency dividers with a minimum gate length of 25 nm.

The dominant key to achieve superior Ge surface passivation by GeO x interfacial layer is investigated based on ozone oxidation. The interface state density ( D it ) measured from low temperature conduction method is found to decrease with increasing the GeO x thickness (0.26–1.06 nm). The X-ray photoelectron spectroscopy (XPS) is employed to demonstrate the interfacial structure of GeO x /Ge with different GeO x thicknesses. And the XPS results show that Ge 3+ oxide component is responsible to the decrease of the D it due to the effective passivation of Ge dangling bonds. Therefore, the formation of Ge 3+ component is the dominant key to achieve low D it for Ge gate stacks. Our work confirms that the same physical mechanism determines the Ge surface passivation by the GeO x regardless of the oxidation methods to grow the GeO x interfacial layer. As a result, to explore a growth process that can realize sufficient Ge 3+ component in the GeO x interlayer as thin as possible is important to achieve both equivalent oxide thickness scaling and superior interfacial property simultaneously. This conclusion is helpful to engineer the optimization of the Ge gate stacks.

Energy band lineup at hetero-interface and its physical origin have been always a fascinating issue, and are being intensely investigated. The understanding of the influence of an interlayer on the band lineup of hetero-interface provides a view of studying the band lineup of hetero-interface. Thus in this paper, the Al2O3/GeOx/Ge structure is employed, and the effect of interlayer GeOx thickness on band lineup of Al2O3/GeOx/Ge structure is studied by X-ray photoelectron spectroscopy technique. The valence band offset of Al2O3/Ge hetero-interface is found to be nearly identical (3.5 eV) for different GeOx thicknesses (0.2 nm ~ 1.2 nm). The gap states model is employed to successfully explain these results. The interfacial dipole in Al2O3/GeOx/Ge structure is nearly unchanged with GeOx thickness based on the gap states model. This indicates that the band lineup of Al2O3/GeOx/Ge structure is independent on GeOx thickness. Thus these further verify that the gap state model is feasible in elucidating energy band lineup at hetero-interfaces.

In this paper, a fin-on-insulator (FOI) FinFET structure with a metallic source and drain (MSD) and HKMG-last processes was investigated extensively. FOI FinFETs demonstrated ten times of leakage current reduction compared with conventional bulk FinFET using p-n junction. In contrast to bulk FinFETs, MSD FOI FinFETs demonstrate a greatly improved control of short channel effects (SCEs) (∼47% DIBL and ∼32% SS reductions for 20-nm-Lg PMOS) compared to conventional bulk FinFET. The drive ability of 20-nm-Lg FOI transistor is increased about 30 times with full Ni(Pt) silicide process, up to 547 μA/μm for NMOS and 324 μA/μm for PMOS at V DD = 0.8 V. However, the excellent controls of SCEs and channel leakage were also obtained. No obvious increase of leakage happens in FOI FinFETs using fully Ni(5%Pt) silicide process.

In this work, tantalum nitride (TaN) was chosen as the wet etch stop layer (WESL) for its application in the 22 nm and beyond nodes CMOS technology. TaN WESL prevents the attacking of titanium nitride (TiN)/hafnium dioxide (HfO 2 ) stack covering n-channel MOS (nMOS) regions from selectively stripping work function metals of p-channel MOS (pMOS) gate, i.e. TiN & titanium (Ti), by ammonia hydrogen peroxide mixture (APM) solution. In terms of etching selectivity to TiN & Ti, gate filling capability and work function tuning for both nMOS and pMOS, the properties of TaN films prepared by different methods such as physical vapor deposition (PVD) and atomic layer deposition (ALD) were investigated systematically.

The architecture, size and density of metal oxide field effect transistors (MOSFETs) as unit bricks in integrated circuits (ICs) have constantly changed during the past five decades. The driving force for such scientific and technological development is to reduce the production price, power consumption and faster carrier transport in the transistor channel. Therefore, many challenges and difficulties have been merged in the processing of transistors which have to be dealed and solved. This article highlights the transition from 2D planar MOSFETs to 3D fin field effective transistors (FinFETs) and then presents how the process flow faces different technological challenges. The discussions contain nano-scaled patterning and process issues related to gate and (source/drain) S/D formation as well as integration of III-V materials for high carrier mobility in channel for future FinFETs.

Oxidation mechanism and passivation of Ge surface by ozone is experimentally investigated. The GeOx oxidation process contains two regions: initial linear growth region and following parabolic growth region. The linear growth region contains reaction of oxygen atoms with surface bond and back bonds of outmost Ge layer. The parabolic growth region starts when the oxygen atoms diffuse into back bonds of second outmost Ge layers. Furthermore, in the ozone oxidation it is not O 3 molecules but O radicals that go through the GeO x film. The interface state density (D it ) is found to decrease with increasing the GeOx thickness (0.26–1.06 nm). X-ray photoelectron spectroscopy (XPS) results show that Ge3+ oxide component is responsible to the decrease of D it .

The large parasitic resistance has become a critical limiting factor to on current (I ON ) of FinFET and nanowire devices. Fully metallic source and drain (MSD) process is one of the most promising solutions but it often suffers from intolerant junction leakage in bulk FETs. In this paper, fully MSD process on fin-on-insulator (FOI) FinFET is investigated extensively for the first time. By forming fully Ni(Pt) silicide on physically isolated fins, about 90% reduction in contacted resistivities (R c s) and 55% reduction in sheet resistances (R s s) are achieved without obvious junction leakage degradation. As a consequence, Ion of transistor, with gate length (L g ) of 20nm, is increased 30 times, up to 547μA/μm for NMOS and 324 μA/μm for PMOS, respectively. Excellent controls of SCE and channel leakage with 47% DIBL, 32% SS and 2.5% device leakages reductions over the counterpart of conventional bulk FinFETs are also obtained. Meanwhile, the fully MSD process induces clear tensile stress into narrow fin-channel, resulting in enhanced electron mobility in NMOS. A further improvement in PMOS drive ability (486μA/μm) by using Schottky barrier source and drain (SBSD) technology is also explored.

P-type Schottky barrier height (p-SBH) at TiN/HfO2 interface of TiN/HfO2/SiO2/Si stack is systematically investigated by XPS. And p-SBH is found to increase with thicker HfO2 thickness. Fig. 1 shows the binding energy of Hf 4f core level of TiN/HfO2/SiO2/Si stack with three different thicknesses of HfO2, together with the spectrum of Fermi edge of TiN metal gate. In addition, the distance between the Hf 4f and valence band maximum of HfO2 is experimentally determined to be 14.2 eV. Then the p-SBH of TiN/HfO2 interface of TiN/HfO2/SiO2/Si stack is calculated to be 3.17 eV for 3.5 nm HfO2, 3.34 eV for 15.2 nm HfO2, and 3.38 eV for 18.7 nm HfO2. Thus it can be concluded that the p-SBH of TiN/HfO2 interface is affected by the thickness of HfO2. This experimental phenomenon cannot be explained by considering only the metal/dielectric contact itself as shown in Fig. 3(a). This is due to that for MOS stack with metal/high-k/SiO2/Si structure the high-k/SiO2 interface also impacts the band lineup of metal/high-k interface shown in Fig. 2. Furthermore, various charges at interfaces or in high-k dielectric can also affect the band alignment of metal/high-k interface. Thus the band alignment of TiN/HfO2 interface should be considered based on the band alignment of whole gate stack. Then a model considering the band alignment of whole stack is proposed to interpret the referring experimental phenomenon as shown in Fig. 3(b). The p-type SBH at the metal/high-k interface of metal/high-k/SiO2/Si stack is found to be dependent on the Q0, which is the sum of charges in the whole stack except the charges at TiN/HfO2 interface. Based on our previous work on the band alignment of entire gate stack [1], the dependence of Q0 on the HfO2 thickness is calculated as shown in Fig. 4. With thicker HfO2 thickness Q0 is lager, resulting in larger p-SBH. Also shown in Fig. 4 are dependences of the theoretical and experimental p-SBH increases on HfO2 thicknesses. Fig. 5 shows n-type SBH versus metal vacuum workfunction Φm based on conventional model and our model. In addition, the intercept (I) of VFB-EOT of metal/11.7 nm HfO2/terraced SiO2/Si stack is experimentally investigated with respect to Φm, as shown in Fig. 5. Also shown in Fig. 5 are the calculated results of I versus Φm based on considering the band alignment of whole gate stack. It can be seen from Figs. 4 and 5 that the calculation data based on our model are in good agreement with the experimental results. These further confirm our model.

The Electric and TDDB characteristics of Si/SiO2/HfO2/TiN gate MOS capacitor (EOT ~ 9.3 A ) with different RTO temperatures are systematically studied. The TDDB characteristics are sensitive to the RTO temperatures (700oC, 800oC and 900oC), and the higher RTO temperature is, the larger Weibull Slope is shown because of thicker EOT. Compared to 700oC and 900oC RTO, the 800oC RTO has the best TDDB lifetime for 63% failure.

HfLaON is one of the most promising high-k dielectrics because of its higher crystallization temperature and ability to tune the work function of the metal gates from Si midgap to around 4eV, meeting the requirement of nMOSFETs. In this paper, HfLaON was prepared using reactive sputtering that alternates between Hf and HfLa targets in N2/Ar ambient, followed by a post-deposition anneal. Before deposition of HfLaON film, SiO2 interfacial layer was grown to improve the interface properties. HfLaON/SiO2 gate stack exhibited good physical and electrical characteristics, including good thermal stability, excellent interface properties, small equivalent oxide thickness and low gate-leakage current. Further studies found that the excellent characteristics of the gate stack have close relation to the grown method of SiO2 interfacial layer. In order to investigate their relationship, the different grown methods of SiO2 interfacial layer were adopted and compared in the fabrication of HfLaON/SiO2 gate stacks, such as oxidation in O3/H2O solution, rapid thermal anneal in N2 or N2/O2 mixed gas.

Band alignment of TiN/HfO2/SiO2/Si stack is systematically investigated by X-ray photoelectron spectroscopy. The differences of binding energies of Si 2p core level between SiO2 and Si substrate are experimentally found to decrease with the sequence of 5 nm SiO2/Si, 4 nm HfO2/5 nm SiO2/Si and 2 nm HfO2/5 nm SiO2/Si stacks. The p-type Schottky barrier heights at TiN/HfO2 interface of TiN/HfO2/SiO2/Si stack are experimentally estimated to increase with thicker HfO2 thickness. A physical model based on band alignment of TiN/HfO2/SiO2/Si stack is employed to successfully explain these experimental results. The flatband voltage (VFB) of TiN/HfO2/SiO2/Si stack is demonstrated by the proposed model based on band alignment of entire gate stack. The positive VFB shift of TiN/HfO2/SiO2/Si stack and Fermi level pinning are also physically demonstrated by this model and attributed to interface induced gap states at TiN/HfO2 and HfO2/SiO2 interfaces.

In order to improve the HKMG interface states density and electrical characteristics, four different interface layers have been studied in this paper. They are 7Aå thickness of SiO2 produced by rapid thermal annealing process at 1000°C, 4Aå thickness of SiO2 produced by rapid thermal annealing process at 700°C, 10Aå thickness of silicon nitride produced by LPCVD process at 620°C, and 20Aå thickness of SiO2 produced by traditional horizontal furnace process at 830°C. It was found that there were two samples, the interface layers of 7Aå SiO2 and 10Aå silicon nitride, having excellent interface state density (1.5~1.7×1011cm-2ev-1) and gate leakage (3.1~3.5×10-7A). Considering the thinner equivalent oxide thickness (Eot), we choose 10Aå silicon nitride as the best one

This letter investigates the mitigation of reverse short-channel effect (RSCE) using multilayer atomic layer deposition (ALD) TiN/PVD Ti/CVD TiN metal gates (MG) for the p-channel metal-oxide-semiconductor field-effect transistors fabricated the by gate-last process. It is found that work function (WF) of multilayer ALD titanium nitride/physical vapor deposition titanium/chemical vapor deposition titanium nitride (ALD TiN/PVD Ti/CVD TiN) MG in devices of short channels is larger than in devices of long channels. This mainly results from different ALD TiN crystal orientations for devices with different gate lengths, that is, TiN(100) for devices with short gate length, whereas TiN(111) for devices with long gate length. The WF of ALD TiN(100) is larger than TiN(111). Meanwhile, because of the property of PVD sputtering, the Ti layer is thinner in devices of short channels than in devices of long channels. Our results on MOSCAP show that the flat-band voltage (V fb ) for TiN MG with a Ti layer is reduced by 0.2 V. Taking all the aforementioned into account, V th roll-up is suppressed as the gate length shrinks, leading to the mitigation of RSCE.