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Cryogenic microsystems that utilize different 3D integration techniques are being actively developed, e.g., for the needs of quantum technologies. 3D integration can introduce opportunities and challenges to the thermal management of low temperature devices. In this work, we investigate sub-1 K inter-chip thermal resistance of a flip-chip bonded assembly, where two silicon chips are interconnected by compression bonding via indium bumps. The total thermal contact area between the chips is 0.306 mm2, and we find that the temperature dependence of the inter-chip thermal resistance follows the power law of α T − 3 , with α = 7.7 – 15.4 K4μm2/nW. The T − 3 relation indicates phononic interfacial thermal resistance, which is supported by the vanishing contribution of the electrons to the thermal conduction, due to the superconducting interconnections. Such a thermal resistance value can introduce a thermalization bottleneck in particular at cryogenic temperatures. This can be detrimental for some applications, yet it can also be harnessed. We provide an example of both cases by estimating the parasitic overheating of a cryogenic flip-chip assembly operated under various heat loads as well as simulate the performance of solid-state junction microrefrigerators utilizing the observed thermal isolation. [ABSTRACT FROM AUTHOR]

Flexible and stretchable materials have attracted significant interest in wearable electronics and bioengineering fields. Recent developments also incorporate embedded microwave circuits and systems with engineered flexible materials that operate over a broad frequency range (≈1–100 GHz). Herein, a simple flip‐chip technique is used to evaluate frequency‐dependent electromagnetic properties of flexible materials and applied to evaluate engineered microwave absorbers based on self‐biased barium hexaferrite composites. On‐wafer error correction and de‐embedding techniques are applied to determine broadband electromagnetic properties of the material‐loaded transmission lines by placing the materials on top of coplanar waveguide transmission lines. Finite‐element simulations along with broadband measurements were employed to estimate the electromagnetic material properties. To demonstrate, flexible polydimethylsiloxane (PDMS) composites are fabricated with barium hexaferrite nanoparticles and complex permittivity and permeability of the composites are quantified under zero magnetic field bias up to 110 GHz. Frequency‐dependent composite permeability is fitted to models describing the ferromagnetic resonance of the self‐biased barium hexaferrite nanoparticles in polydimethylsiloxane, and constituent nanoparticle properties are estimated using the Maxwell–Garnett mixing model. This study paves the way to exploit a wide range of engineered materials in flexible, wearable, and biomedical electronics applications and presents a convenient methodology to extract important broadband electromagnetic properties of nanoparticles for customized electromagnetic applications. [ABSTRACT FROM AUTHOR]

Shortwave infrared (SWIR) imaging devices have gained increasing importance in various fields, including security monitoring, biomedical imaging, advanced driver assistance, and semiconductor industry. However, complex technological processes of epitaxial growth and flip‐chip bonding hinder the development of high‐performance and low‐cost SWIR imaging devices. Herein, a novel organic–inorganic hybrid optical up‐conversion (OUC) imaging device by stacking a phosphorescent organic light‐emitting diode (OLED) with a NiSix/Si Schottky barrier diode (SBD) is developed. The pyramidal microstructures of silicon are utilized to greatly enhance light absorption of the NiSix/Si SBD, enabling the device to respond to a broadband SWIR light of 1064, 1310, and 1550 nm that are beyond the bandgap limit of silicon. Significantly, the device demonstrates excellent up‐conversion imaging behaviors at SWIR light with an ultra‐fast refresh rate of over 3000 Hz and a high‐resolution imaging capability of 508 ppi. This work paves the way toward the fabrication of high‐performance, low‐cost silicon‐based OUC devices for SWIR imaging applications. [ABSTRACT FROM AUTHOR]

In this theoretical study, we explore the use of quantum code-based memories to enhance the lifetime of qubits and exceed the break-even point, which is critical for the implementation of fault-tolerant quantum computing. Specifically, we investigate the quantum phase-flip repetition code as a quantum memory and theoretically demonstrate that it can preserve arbitrary quantum information longer than the lifetime of a single idle qubit in a dephasing-time-limited system, e.g. in semiconductor qubits. Our circuit-based analytical calculations show the efficiency of the phase-flip code as a quantum memory in the presence of relaxation, dephasing, and faulty quantum gates. Moreover, we identify the optimal repetition number of quantum error correction cycles required to reach the break-even point by considering the gate error probabilities of current platforms for quantum computing. Our results provide guidelines for developing quantum memories in semiconductor quantum devices. [ABSTRACT FROM AUTHOR]

Dark excitons are fascinating for condensed matter physics, quantum information processing, and optoelectronics due to their long lifetimes. However, direct optical access to dark excitons is still challenging due to the violation of the spin selection rule. Here, a new scheme for the brightening of spin‐forbidden dark exciton in WS2 monolayers by creating artificial out‐of‐plane shear strain that induces an effective in‐plane pseudo‐magnetic field is proposed. To reveal dark excitons, low‐temperature magneto‐photoluminescence experiments on the strained WS2 monolayers are performed. It is found that the dark excitons appear at 59 meV below the bright ones and exhibit an asymmetric magnetic field dependence, which is in agreement with the model taking into account the effect of the out‐of‐plane shear strain on spin‐flip processes of exciton states. The fieldless scheme has great potential in the application of dark excitons for new quantum information processing devices. [ABSTRACT FROM AUTHOR]

Purpose: This study aims to contribute to the numerical modelling of drop impact on a flip-chip component assembled on printed circuit boards using solder micro-bumps. This contribution is based on the introduction of non-linear fracture mechanics in the numerical approach. Design/methodology/approach: The integration of non-linear fracture mechanics into the numerical approach requires the proposal and validation of several simplifying assumptions. Initially, a dynamic 3D model was simplified to a dynamic 2D model. Subsequently, the dynamic 2D model is replaced with an equivalent static 2D model. The equivalent static 2D model was used to perform calculations considering the non-linear fracture mechanics. A crack was modelled in the critical bump. The J-integral was used as a comparative parameter to study the effects of crack length, crack position and chip thickness on the fracture toughness of the solder bump. Findings: The different simplifying assumptions were validated by comparing the results obtained by the various models. Numerical results showed a high risk of failure at the critical solder bump in a zone close to the intermetallic layer. The obtained results were in agreement with the post-test observations using the "Dye and Pry" methods. Originality/value: The originality of this study lies in the introduction of non-linear fracture mechanics to model the mechanical response of solder bumps during drop impact. This study led to some interesting conclusions, highlighting the advantage of introducing non-linear fracture mechanics into the numerical simulations of microelectronic components during a drop impact. [ABSTRACT FROM AUTHOR]

In this paper, we analyze the residual stress of different components of the crystal structures of electronic device materials following exposure to elevated temperatures using a combination of experimental tests and finite element simulations. X-ray diffraction (XRD) and LXRD micro-area residual stress analyzer were employed to determine the residual strain and stress of the CBGA sample encapsulation cover and solder joints. Subsequently, the experimental data were utilized to verify the accuracy of the simulation. The discrepancy between experimental measurements and simulation outcomes of the residual stress following reflow soldering of CBGA-assembled micro-solder joints is below 14%. The analysis also included thermal warping deformation of the CBGA encapsulation cover and how the residual stress was influenced by the diameter, spacing, and height of the solder joints. The study reveals that the residual stress following reflow soldering of BGA solder joints is non-uniformly distributed within the array. Within a single solder joint, residual stress gradually increases in distribution from its middle to the point where it make contact with the PCB and chip, with the highest level of residual stress observed where the solder joint contacts the chip. The variation in material parameters, such as the coefficient of thermal expansion, is the primary cause of thermal warping deformation on the surface of CBGA encapsulation covers. Three primary factors significantly impact the residual stress on BGA solder joints: solder joint diameter, spacing, and height. The maximum value is inversely proportional to the height of the solder joints and the residual stress. Conversely, the diameter and spacing of the joints are positively proportional to the highest value. When the diameter of the solder joint is increased from 0.55 mm to 0.75 mm, the maximum residual stress in the BGA solder joint increases from 37.243 MPa to 36.835 MPa. Conversely, increasing the height of the solder joint from 0.36 mm to 0.44 mm reduces the stress from 39.776 MPa to 36.835 MPa. [ABSTRACT FROM AUTHOR]

Nanomagnetic materials, built from thin, patterned films of ferromagnetic materials, began as analogues to frustrated magnetism. Their low energy of operation and emergent properties make them strong candidates for physics-based devices. A recent model of how nanomagnetic domains flip, the Glauber mean-field model, is used here to understand how systems of nanomagnets evolve when opposed by external field. This reversal can be expressed in an analytical form in the case of one-dimensional chains and trees at zero temperature, where the cascade of spin flips gives rise to harmonic power spectra. The same cascades in two and three dimensions form fractal field reversal clusters whose shape depends on the strength of the field and the tuning of interactions between nanomagnets. [ABSTRACT FROM AUTHOR]

We demonstrate strong coupling of gigahertz-frequency nanomechanical resonators to a frequency-tunable superconducting microwave resonator via a galvanically bonded flip-chip method. By tuning the microwave resonator with an external magnetic field, we observe a series of hybridized microwave-mechanical modes and report coupling strengths of ∼ 15 MHz at cryogenic temperatures. The demonstrated multi-chip approach provides flexible rapid characterization and simplified fabrication and could potentially enable coupling between a variety of quantum systems. Our work represents a step toward a plug-and-play architecture for building more complex hybrid quantum systems. [ABSTRACT FROM AUTHOR]

To bond a semiconductor power chip on a substrate using the formation of bondlines exhibiting long-term mechanical durability at high temperatures such as 300 °C, compression-assisted sinter bonding between Cu finishes was carried out at 300–350 °C in air. Cu flakes of approximately 7 µm were used as the main filler material; their surfaces were modified by pretreatment using a formic acid solution, and the existing oxide layers were transformed into copper formate shells. To increase the amount of the copper formate shells, the shell transformation reaction was controlled by the deliberate addition of 30 nm Cu2O particles and sustained for 50 min. The formate shells formed decomposed at a peak temperature of 250 °C, forming pure Cu, which rapidly induced sintering between the flakes and at the Cu-finish–flake interfaces. Therefore, the paste containing Cu flakes showed a sufficient shear strength of 26.3 MPa even in air after sinter bonding for only 3 min under 5 MPa at 350 °C. Although the bimodal-type paste presented near-full-density bondline structures within 3 min of adding 350 nm pure Cu particles, the strengths with respect to bonding time showed trends of values less than 26.3 MPa, owing to the excessive oxidation of the 350 nm Cu. [ABSTRACT FROM AUTHOR]

Copyright of Journal of South China University of Technology (Natural Science Edition) is the property of South China University of Technology and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

With the rapid advancement of next-generation communication technology, traditional Quad Flat No-leads (QFN) packaging is facing challenges to meet functional requirements. Due to its high integration and excellent thermal performance, the Multi-chips Module combined with Quad Flat No-leads (MCM-QFN) packaging is gaining popularity. However, the structural complexity of MCM-QFN packaging and the thermal coupling effect between multiple dies make it challenging to analyze the steady-state thermal distribution of MCM-QFN packaging, which is necessary for assessing the reliability and optimizing the layout design of the multi-chips module. By analyzing the heat dissipation path from each die to the ambient, this paper proposes an analytical thermal resistance network model for calculating each mean die temperature of MCM-QFN packaging. The thermal coupling effect among the multi-chips, the thermal spreading resistance between critical layers, and the boundary conditions and cooling conditions are all considered. All thermal resistances in the model are expressed analytically, and the mean temperature of each chip can be calculated within 0.1 s using MATLAB programming. To validate the accuracy of the proposed model, finite element method (FEM) simulations are conducted to provide a reference for the mean temperature of each chip under four sets of thermal conditions. The data comparison demonstrates that the analytical model is fast and accurate in calculating each mean die temperature of MCM-QFN packaging, with a maximum error of 3.72%, and the calculation speed increased by about 600× compared to that of FEM simulation. Furthermore, the analytical model is able to offer a direction for optimizing the layout design and material selection of MCM-QFN packaging. [ABSTRACT FROM AUTHOR]

Copyright of Atomic Energy Science & Technology is the property of Editorial Board of Atomic Energy Science & Technology and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

This paper discusses improved design of two-dimensional (2D) arrays, potentially pushing the present state of the art of the high-Tc (and low-Tc) magnetic field detectors to a larger scale, i.e., higher sensitivity. We propose a two-plate geometry for parallel (and two-dimensional) arrays of Josephson junctions (JJs) for application in magnetic field detection. The arrays can be realized either by integration in the same substrate with a multilayer technology or on two different substrates. In the latter case, the substrates can be assembled in a flip-chip or piggyback configuration. A suggestion would be to divide a 2D array in two (equal) parts and to distribute each part on a different layer, one above the other. We model the current distribution in arrays connected in series so that the bias current flowing through the device flows in opposite direction in the layers. We demonstrate that this geometry greatly improves the uniformity of the bias current distribution across the width of the array, thereby restoring the critical current and, in principle, improving the Josephson array response. From the model, we conclude that the alignment of the arrays is not critical and that the realization of the devices requires only conventional techniques. [ABSTRACT FROM AUTHOR]

The substrate material plays an important role in industrialized flip-chip technology of the passive ultra-high frequency radio frequency identification with antenna printed on flexible film. This work presents the flip-chip fabrication and performance evaluation of ultra-high frequency radio frequency identification with screen-printed antenna on common woven fabrics. The antennas were manufactured by screen printing a stretchable silver-based conductor directly on a common woven nylon fabric. The electrical and mechanical connection between the screen-printed antennas and microchips was formed by flip-chip technology, which bridged the antenna with the microchip under a heating contactor with additive anisotropic conductive adhesives, and the effects of heating contactor parameters (contactor pressure, temperature and duration time) on the performance of radio frequency identification tag prototypes were investigated, and the influence mechanism was discussed in terms of the conductivity, the resonance frequency shift and the morphology. The experiment results show that the flip-chip bonding conditions set in the case of screen-printed antenna on nylon fabric is 0.7 N contactor pressure, 120°C heating temperature and 0.6 s heating duration time, different from the case of previous plastic-like thin film substrate, and this is mainly attributed to the compressive and rough surface of the fabric-based antennas. In addition, the flip-chip heating temperature should be consistent with that of screen-printed conductive ink to ensure a stable electrical connection between the antenna and microchip, as well as good performance of fabric-based ultra-high frequency radio frequency identification tags. These conclusions provide a tool for manufacturing large-scale fabric-based ultra-high frequency radio frequency identification tags and characterizing the process quality. [ABSTRACT FROM AUTHOR]

Higher-order topological insulators have drawn great research attention in nanophotonics due to their ability to both support robust edge states and lower dimensional corner states. In this work, we present a theoretical proposal for achieving topologically switchable and valley-selective corner states based on two-dimensional C3-symmetric photonic crystals (PCs), with breaking of inversion symmetry. Through the concatenation of two valley PCs with contrasting topological indices, we demonstrate the emergence of two types of valley-locked chiral topological edge states resulting from the valley–valley interaction. More importantly, we find that the system exhibits two distinct types of corner states, characterized by strong robustness and high localization, when the PCs are spliced at a 60° angle. However, the corner states are absent when the splicing angle is set as 120°. According to the theoretical analysis, the selective activation of topological valley corner states is related to the sign flip of valley Chern number at the corner. Based on this feature, we further propose a topological photonic switching device, in which the corner can be lighted up or off selectively. By combining the benefits of higher-order topology and valley degree of freedom, our work provides an efficient and flexible method for light manipulation. [ABSTRACT FROM AUTHOR]

The article presents a study which proposed a controllable in situ electric field-activated doping method to construct lateral p-n junctions in the short-wave infrared (SWIR) mercury telluride (HgTe) colloidal quantum dot (CQD)-based photodetectors with a simple planar configuration. Topics discussed include planar p-n junction focal play array (FPA) imagers, SWIR imaging using FPA imagers, and device fabrication and characterization.

In this work, rapid failure of a few minutes was observed in real ball grid array solder joints under high current density (8 × 103 and 1 × 104 A cm−2) at room temperature. For each test condition, the failure solder joint was detected at the same position of the daisy chain by computed tomography technology. Furthermore, the open failure for all solder joints was caused by the chip side (anode side) Cu dissolution. Microstructure evolution for a pair of electrically connected solder joints was investigated. In both solder joints, Cu atoms on the chip side were dissolved to the board side with the formation of intermetallic compound particles in solder matrix. Finite element simulation was introduced to calculate the current density, temperature, and heat flux distribution. The temperature gradient along the direction of Cu migration in solder joint was developed due to the accumulation of Joule heating. Thermomigration was confirmed as the dominant mechanism of chip side Cu dissolution. [ABSTRACT FROM AUTHOR]

Scanning acoustic microscopy (SAM) technique has been applied to defect inspection in electronic devices. With the increase of packaging density, detection of the micro-defects in high density devices becomes more and more challenging. The SAM test is suffering from sacrificing the spatial resolution to reach a certain penetration depth of the ultrasonic waves. So it is necessary to enhance the resolution level of the SAM image. In this paper, a wavelet based resolution enhancement technique was investigated to reconstruct a high quality image for SAM test of the flip chip packages. The stationary wavelet transform was adopted to decompose the captured SAM image into four frequency subbands, and the high frequency subbands were enhanced by adding the difference matrix in the intermediate stage, and a super resolution SAM image was derived from combining all the subbands by using the Inverse Discrete Wavelet Transform. Then the solder joints segmented from the SR-SAM image were classified by using the SVM algorithm. The results validated that the proposed technique is effective to improve the detection accuracy of SAM test. • An intelligent system is developed to inspect the solder joints of flip chip. • The SAM image is decomposed into four different frequency components. • High resolution SAM image is reconstructed with the wavelet-based method. • The solder joints are segmented from the SR-SAM image. • The SR-SAM image has high accuracy for defect recognition. [ABSTRACT FROM AUTHOR]

Purpose: Statistical modeling has been successfully applied to integrated circuit (IC) solder joint inspection. However, there are some inherent problems in previous statistical modeling methods. This paper aims to propose an adaptive statistical modeling method to further improve the inspection performance for IC solder joints. Design/methodology/approach: First, different pixels in the IC solder joint image were modeled by different templates, each of which was composed of the hue value of the pixel and a proposed template significance factor. Then, the potential defect image was obtained by adaptive template matching and the potential defect threshold for each pixel. It was noted that the number of templates, matching distance threshold, potential defect threshold and updating rate were adaptively updated during model training. Finally, the trained statistical model was used to inspect the IC solder joints by means of defect degree. Findings: Experimental results indicated that the proposed adaptive schemes greatly contributed to the inspection performance of statistical modeling. Also, the proposed inspection method achieved better performance compared with some state-of-the-art inspection methods. Originality/value: The proposed method offers a promising approach for IC solder joint inspection, which establishes different numbers of templates constructed by pixel values and template significance factors for different pixels. Also, some important parameters were adaptively updated with the updating of the model, which contributed to the inspection performance of the model. [ABSTRACT FROM AUTHOR]

Stand-alone microgrids have become reliable and efficient solutions for remote areas and critical infrastructures. However, the converters within these microgrids experience long-term complex power fluctuations caused by random variations in micro sources and loads. These power fluctuations induce thermal cycling in semiconductor chips, leading to thermal fatigue failure and compromising the safety and reliability of both the converter and microgrid operation. To address this issue, this paper proposes a reactive power injection algorithm aimed at reducing the output power fluctuation of the converter. The algorithm implements reactive power injection at the converter control level, thereby restructuring the output power profile and resulting in reduced junction temperature fluctuations in IGBTs. This approach effectively mitigates thermal stress within the material layers of the module, extending the lifetime of power devices and improving the operational reliability of the microgrid. The algorithm implementation is based on the PQ control strategy, integrating the power triangle with the envelope detection technique. Furthermore, the lifetime prediction process utilizes the electro-thermal coupling model, the rainflow counting algorithm, and the Lesit model. Simulation results demonstrate that, for an active power fluctuation range of 10 kW to 80 kW and an equivalent RC time constant of 22.5 s, the algorithm achieves a significant reduction of 62.64% in the amplitude of output power fluctuation and extends the lifetime of power devices by 74.13%. The obtained data showcase the effectiveness of the algorithm in enhancing the lifetime of power devices and further improving the microgrid operational reliability under specific parameter conditions. [ABSTRACT FROM AUTHOR]

This paper proposes a new type of substrate for manufacturing LEDs based on AlInGaN heterostructures. Instead of depositing SiC layers on the surface of Si using the conventional method, a new method involving the coordinated substitution of atoms (MCSA) to form the SiC layer is proposed. This new approach enables the growth of epitaxial GaN layers with low defect content and facilitates transfer to any surface. The paper details the technology of manufacturing LEDs on SiC/Si substrates obtained by the MCSA and elaborates on the benefits of using these substrates in LED production. Additionally, the advantages of the growth interface between SiC and Si materials are discussed. Moreover, it is found that thinner SiC layers (<200 nm) contribute to the scattering of the LED's own radiation in the heterostructure waveguide, which decreases its absorption by silicon. For flip-chip LEDs with the substrate removed, substrates with thicker SiC layers (~400 nm) and a growth porous layer of several microns at the SiC-Si interface is utilized to simplify Si substrate removal and enhance the manufacturing process's cost-effectiveness. [ABSTRACT FROM AUTHOR]

This paper examines the thermal resistance of the mid-infrared "flip-chip" LEDs based on the p‑InAsSbP/n-InAsSb heterostructure. It was shown that the measurement of thermal resistance via a thermal control unit (forward p–n junction voltage) for LEDs based on narrow-gap semiconductors must be carried out at low temperature when thermal control unit is constant. [ABSTRACT FROM AUTHOR]

Roll-to-roll (R2R) printing methods are well known as additive, cost-effective, and ecologically friendly mass-production methods for processing functional materials and fabricating devices. However, implementing R2R printing to fabricate sophisticated devices is challenging because of the efficiency of material processing, the alignment, and the vulnerability of the polymeric substrate during printing. Therefore, this study proposes the fabrication process of a hybrid device to solve the problems. The device was created so that four layers, composed of polymer insulating layers and conductive circuit layers, are entirely screen-printed layer by layer onto a roll of polyethylene terephthalate (PET) film to produce the circuit. Registration control methods were presented to deal with the PET substrate during printing, and then solid-state components and sensors were assembled and soldered to the printed circuits of the completed devices. In this way, the quality of the devices could be ensured, and the devices could be massively used for specific purposes. Specifically, a hybrid device for personal environmental monitoring was fabricated in this study. The importance of environmental challenges to human welfare and sustainable development is growing. As a result, environmental monitoring is essential to protect public health and serve as a basis for policymaking. In addition to the fabrication of the monitoring devices, a whole monitoring system was also developed to collect and process the data. Here, the monitored data from the fabricated device were personally collected via a mobile phone and uploaded to a cloud server for additional processing. The information could then be utilized for local or global monitoring purposes, moving one step toward creating tools for big data analysis and forecasting. The successful deployment of this system could be a foundation for creating and developing systems for other prospective uses. [ABSTRACT FROM AUTHOR]

The magnetic properties of permalloy-based trilayers of the form Py0.8Cu0.2/Py0.4Cu0.6/Py/IrMn were studied as the spacer layer undergoes a paramagnetic to ferromagnetic phase transition. We find the coupling between the free Py0.8Cu0.2 layer and the exchange bias pinned Py to be strongly temperature-dependent: there is negligible coupling above the Curie temperature of the Py0.4Cu0.6 spacer layer, strong ferromagnetic coupling below that temperature, and a tunable coupling between these extremes. Polarized neutron reflectometry was used to measure the depth profile of the magnetic order in the system, allowing us to correlate the order parameter with the coupling strength. The thickness dependence shows that these are interface effects with an inverse relationship to thickness, and that there is a magnetic proximity effect that enhances the Curie temperature of the spacer layer with characteristic length scale of about 7 nm. As a demonstration of potential functionality of such a system, the structure is shown to spontaneously flip from the antiparallel to parallel magnetic configuration once the spacer layer has developed long-range magnetic order. [ABSTRACT FROM AUTHOR]

Covalent organic frameworks (COFs) have been attracting intense research due to their permanent porosity, designable architecture, and high stability. However, COFs are challenging to crystallize and their synthesis often results in tiny crystal sizes and low crystallinities, which hinders an unambiguous structure determination. Herein, we demonstrate that the structure of low-crystallinity COF Py-1P nanocrystals can be solved by coupling three-dimensional electron diffraction (3DED) with simulated annealing (SA). The resulting model is comparable to that obtained from high-crystallinity samples by dual-space method. Moreover, for low-resolution 3DED data, the model obtained by SA shows a better framework than those provided by classic direct method, dual-space method, and charge flipping. We further simulate data with different resolutions to understand the reliability of SA under different crystal quality conditions. The successful determination of Py-1P structure by SA compared to other methods provides new knowledge for using 3DED to analyze low-crystallinity and nanosized materials. Covalent organic frameworks have demonstrated promise for a wide variety of applications, but their synthesis often results in materials with low crystallinity that are challenging to characterize. Here, coupling three dimensional electron diffraction with simulated annealing is shown to enable the structural determination of a low crystallinity pyrene-containing covalent organic framework. [ABSTRACT FROM AUTHOR]

The development of big data and artificial intelligence technology is increasing the need for electronic devices to become smaller, cheaper, and more energy efficient, while also having enhanced functionalities. However, the miniaturization of silicon chip technology is approaching its Moore's law (i.e., physical) limits. Thus, the application of three-dimensional integrated circuits (3D ICs), in which multiple chips are stacked vertically, provides the most achievable approach for the advancement of post-Moore electronics. In the recent decade, various key techniques have been developed for stacking chips vertically such as through-silicon vias, micro-bumps, low melting point tin–bismuth solders, redistribution layers, and copper-to-copper direct bonding. However, the need for high current densities in these structures results in severe Joule heating, making electromigration (EM) an increasingly challenging problem. This paper reviews studies on EM failures, mechanisms, and potential solutions for the key components of 3D IC packaging. [ABSTRACT FROM AUTHOR]

In this letter, a novel millimeter‐wave chip packaging method based on flip‐suspended‐microstrip technology is proposed. The flip‐suspended‐microstrip contains a waveguide probe, a suspended microstrip line, input and output matching lines, and a terminal pad. The waveguide probe realizes energy coupling from the rectangular waveguide, and the terminal pad above the signal pad of chip achieves power transmission via electronic contact. Thus, the bonding wires which will bring parasitic inductance at high frequencies are avoided. To validate the proposed packaging method, back‐to‐back modules with coplanar waveguide/low noise amplifier were fabricated. The measured insertion loss of the back‐to‐back transition with a 1.75‐mm‐long coplanar waveguide is 2.6–4.2 dB over the entire D‐band, while the packaging loss of the low noise amplifier module with the back‐to‐back transition is less than 2.2 dB at 120–170 GHz, which indicate that the proposed broadband transition is feasible for millimeter‐wave chip packaging. [ABSTRACT FROM AUTHOR]

With the rapid development of microelectronic interconnection technology, the reliability requirements of electronic products are becoming higher and higher. Among them, temperature has the greatest impact on electronic devices. Due to the different coefficients of thermal expansion (CTE) between the many materials of a chip, the inside of a solder joint is subjected to cyclic temperature action. Under the effect of cyclic temperature, the solder joints are subject to internal fracture resulting in the failure of the solder joint. Therefore, it is necessary to find a more reliable material for the solder joint. In this paper, the advantages and disadvantages of pure silver material and low silver material are compared by finite element simulation analysis of nano-silver pure silver material and SAC305 low silver material, and the fatigue life prediction of nano-silveris predicted by a life prediction model. Then, using the Electric Power Research Institute estimation method to estimate the fatigue life of solder joints, the results are compared with those calculated by the finite element method. [ABSTRACT FROM AUTHOR]

The integrity of solder joints of components in an electronic device is critical to the device reliability. The miniaturisation trend in the development of electronic products has continued to challenge the shear strength of the solder joints in these devices and necessitates implementation of optimal reflow profiles to achieve maximum joint strength. This study proposes an optimal parameter combination of reflow profile factors which demonstrate potential for delivering maximum shear strength of solder joints. The Taguchi design of experiment (DoE) is employed to generate eight orthogonal array designs of L24 reflow profiles. The factors/parameters investigated are preheat gradient, time above liquidus (TAL), peak temperature and cooling rate. Three test vehicles of varying solder joint sizes are made from R1206, R0805 and R0603 resistors. Reflow profile number 3 constituting 1.2°C/s preheat, 45 s TAL, 245°C peak temperature and 60% cooling rate is optimal because it yielded joints with the highest strength and ca. 4 µm intermetallic compound thickness. The solder joint shear strength decreased with a decrease in the size of the lead-free joint irrespective of the reflow profile implemented. These results will be useful for electronic packaging and reliability engineers faced with challenges of improving device operational mechanical performance in the continuing trend of product miniaturisation. [ABSTRACT FROM AUTHOR]

We report a new TFT short‐wave infrared (SWIR) sensor based on colloidal quantum dot (CQD) technology. As the name suggests, its function is to detect and image the short‐wave infrared band. This is an industry‐leading TFT colloidal quantum dot SWIR sensor. The active layer is made of colloidal quantum dot material, and the detection band is 0.9~2.5um. The colloidal quantum dots are interconnected with the TFT reading circuit through spin coating, spraying, screen printing or scraping. The new TFT short‐wave infrared sensor of colloidal quantum dots gets rid of the limitation of the indium column flip‐chip bonding process of the traditional indium gallium arsenide CMOS short‐wave infrared focal plane sensor, and the preparation process is simple, the yield is higher, and the cost is low. A new TFT short‐wave infrared sensor based on colloidal quantum dots realizes a short‐wave infrared focal plane array and successfully captures short‐wave infrared images. [ABSTRACT FROM AUTHOR]

Gallium nitride (GaN) power devices have many benefits, including high power density, small footprint, high operating voltage, and excellent power gain capability. However, in contrast to silicon carbide (SiC), its performance and reliability can be negatively impacted by its low thermal conductivity, which can cause overheating. Hence, it is necessary to provide a reliable and workable thermal management model. In this paper, a model of a flip-chip packing (FCP) GaN chip was established, and it was assigned to the Ag sinter paste structure. The different solder bumps and under bump metallurgy (UBM) were considered. The results indicated that the FCP GaN chip with underfill was a promising method because it not only reduced the size of the package model but also reduced thermal stress. When the chip was in operation, the thermal stress was about 79 MPa, only 38.77% of the Ag sinter paste structure, lower than any of the GaN chip packaging methods currently in use. Moreover, the thermal condition of the module often has little to do with the material of the UBM. Additionally, nano-silver was found to be the most suitable bump material for FCP GaN chip. Temperature shock experiments were also conducted with different UBM materials when nano-silver was used as bump. It was found that Al as UBM is a more reliable option. [ABSTRACT FROM AUTHOR]

The main motivation of this work was to demonstrate a hollow telescopic rod structure that could be used for minimally invasive surgery. The telescopic rods were fabricated using 3D printing technology to make mold flips. During fabrication, differences in biocompatibility, light transmission, and ultimate displacement were compared between telescopic rods fabricated via different processes, so as to select the appropriate process. To achieve these goals, flexible telescopic rod structures were designed and 3D-printed molds were fabricated using Fused Deposition Modeling (FDM) and Stereolithography (SLA) techniques. The results showed that the three molding processes had no impact on the doping of the PDMS specimens. However, the FDM molding process had lower surface flatness accuracy compared to SLA. The SLA mold flip fabrication exhibited superior surface accuracy and light transmission compared to the other methods. The sacrificial template method and the use of HTL direct demolding technique had no significant impact on cellular activity and biocompatibility, but the mechanical properties of the PDMS specimens were weakened after swelling recovery. The height and radius of the hollow rod were found to have a significant impact on the mechanical properties of the flexible hollow rod. The hyperelastic model was fitted appropriately with the mechanical test results, and the ultimate elongation increased with an increase in hollow–solid ratios under the uniform force. [ABSTRACT FROM AUTHOR]

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This study focuses on the topological optimization of adhesive overlap joints for structures subjected to longitudinal mechanical loads. The aim is to reduce peak stresses at the joint interface of the elements. Peak stresses in such joints can lead to failure of both the joint and the structure itself. A new approach based on Rational Approximation of Material Properties (RAMP) and the Finite Element Method (FEM) has been proposed to minimize peak stresses in multi-layer composite joints. Using this approach, the Mises peak stresses of the optimal structural joint have been significantly reduced by up to 50% under mechanical loading in the longitudinal direction. The paper includes numerical examples of different types of structural element connections. [ABSTRACT FROM AUTHOR]

A low power consumption is one of the most important issue for all of the electrical products, especially for wearable products. This manuscript proposed a polarized light emitting diode (LED) chip which is used for a direct back light unit for LCD. A wire grid polarizer and a meta-surface textures are set on the top and bottom of the LED chip in order to obtain a high polarization ratio and transparency. After optimizing the potential parameters, the transmittance of TM and the polarization can reach up to 93.71% and 99.3% respectively. It can replace the normal LED in direct back light unit, and obtain an improved efficiency of 20%, when comparing liquid crystal display with a bottom APF polarizer. It can be used for reducing power consumption and supply dependence, as well as the cost of displays. [ABSTRACT FROM AUTHOR]

When the temperature of the package assembly is changed, non‐uniform deformation and local stress may occur owing to the different thermal expansion coefficients of the constituent materials, while concentrated thermal stress may cause significant failure. In this study, we carry out an experiment and analysis of the thermal deformation of a flip chip plastic ball grid array package with respect to temperature change. Interference fringe patterns representing the displacement distribution of each temperature stage are obtained using a Moiré interferometry and the bending deformation behavior and the strain of the solder ball are analyzed thereafter. We compare the deformation behavior of a single‐sided package assembly and a double‐sided package assembly. The effective strain, which significantly affects the failure of the solder ball, is found to be the largest in the solder ball just outside the edge of the chip in the case of the single‐sided package assembly. In the case of the double‐sided package assembly, the maximum effective strain is found in the solder ball just inside the edge of the chip, with a value approximately 50 % larger than in the case of the single‐sided package assembly. [ABSTRACT FROM AUTHOR]

Purpose: The purpose of this research paper is to explore the possibility to enhance the power transfer from piezoelectric energy harvester (PEH) source to the load. As the proposed gyrator-induced voltage flip technique (GIVFT) does not require bulky components such as physical inductors, it is easily realizable in small integrated circuits (IC) package thereby offering performance benefits, reducing area overhead and providing cost benefits for constrained self-powered autonomous Internet-of-Things (IoT) applications. Design/methodology/approach: This paper presents an inductorless interface circuit for PEH. The proposed technique is called GIVFT and is demonstrated using active elements. The authors use gyrator to induce voltage flip at the output side of PEH to enhance the charge extraction from PEH. The proposed technique uses the current-voltage (I-V) relationship of gyrator to get appropriate phasor response necessary to induce the voltage flip at the output of PEH to gain power transfer enhancement at the load. Findings: The experimental results show the efficacy of the GIVFT realization for enhanced power extraction. The authors have compared their proposed design with popular earlier reported interface circuits. Experimentally measured performance improvement is 1.86×higher than the baseline comparison of full-wave bridge rectifier circuit. The authors demonstrated a voltage flip using GIVFT to gain power transfer improvement in piezoelectric energy harvesting. Originality/value: To the best of the authors' knowledge, pertaining to the field of PEH, this is the first reported GIVFT based on the I-V relationship of the gyrator. The proposed approach could be useful for constrained self-powered autonomous IoT applications, and it could be of importance in guiding the design of new interface circuits for PEH. [ABSTRACT FROM AUTHOR]

Second-generation voltage conveyor structures, based on the employment of flipped voltage follower stages, are investigated and proposed in this work. The proposed core has the feature of offering extremely low or electronically adjustable input resistance and programmable outputs, enhancing the achieved design flexibility and versatility of this active cell. Two design examples are presented in this work, including a multi-phase sinusoidal oscillator topology and an electronically adjustable first-order low-pass filter, both supported by simulation and experimental results. [ABSTRACT FROM AUTHOR]

This paper presents the characteristics of signal transmission between a printed circuit board and an integrated circuit, which were obtained using a flip-chip bump process. To minimize signal loss occurring in an interconnection, a Sn-Au alloy soft bump having a diameter of 65 μm was used as the solder bump in the flip-chip process. The measurement result showed a return loss of less than 15 dB from DC to 43.5 GHz, and an insertion loss of 3.82 dB at 28 GHz. The measurements confirmed that it was very small within the measurement error range generated in the measurement environment of the insertion loss generated by the interconnection. This confirms good signal transfer performance across the DC to 43.5 GHz frequency band. Additionally, the study confirmed through meas- urement that all mm-Wave circuits developed in the Ka-band frequency range can be measured easily and accurately using a bound connector without a probe station requiring sophisticated control. [ABSTRACT FROM AUTHOR]

New diamond chip resistors have been used in high-power devices widely due to excellent heat dissipation and high-frequency performance. However, systematic research about their solder joint reliability is rare. In this paper, a related study was conducted by combining methods between numerical analysis and laboratory reliability tests. In detail, the shape simulation and thermal cycling finite element simulation for solder joints with different volumes were carried out. The optimized solder volume was 0.05 mm3, and the maximum thermal cycling stress under the optimized shape was 38.9 MPa. In addition, the thermal cycling tests with current and high temperature storage tests were carried out for the optimized solder joint, which showed good agreement with the simulation results, clarified the growth and evolution law of intermetallic compound at the interconnection interface, and proved the optimized solder joint had great anti-electromigration, temperature cycling and high temperature storage reliability. In this work, an optimized solder joint structure of a diamond chip resistor with high reliability was finally obtained, as well as providing considerable reliability data for the new type of diamond chip resistors, which would boost the development of power devices. [ABSTRACT FROM AUTHOR]

Gold homogeneous bonding is a promising technique for next-generation 3D-IC interconnects, offering low resistivity, favorable parasitic characteristics, and resistance to oxidation. However, the plastic deformation of gold during thermal cycling under service conditions, driven by various material defects, has not been extensively studied. This work investigates the mechanisms of plastic deformation in Au-Au thermosonic flip-chip joints through a comprehensive characterization of defects at the bonding interface, including basal-plane dislocations and their behaviors, stacking faults, and deformation twins (specifically barrier twin T1 and incoming twin T2). Notably, the incoherent twin boundary (ITB) of T1 dissociated into a 9R structure, comprising two distinct 9R phases with varying tilt angles, driven by the glide of Shockley partial dislocations (SPDs). This study provides quantitative analysis, revealing that a higher proportion of the edge component within the mixed dislocation requires increased stress for SPD emission. Finite element analysis indicates that the stress required for the emission of SPDs from the ITB dissociation is achievable during thermal cycling, with a maximum shear stress of approximately 354.25 MPa. This study offers new insights into the role of atomic-scale defects in the plastic deformation of Au-Au joints, contributing to a deeper understanding of deformation mechanisms in homogeneous gold bonding. [ABSTRACT FROM AUTHOR]

• AlGaN-based DUV LEDs adopt the triangular island-shaped p-electrode structure. • The proposed structure has been proven to have more uniform optical emission distribution and current spreading. • After 500 h of aging, the optical power of the triangular island-shaped structure is still maintained at 97.6%. • The L70 predicted lifetime of the new structure is extended by 45% compared to the traditional structure. Current crowding and poor reliability due to uneven current distribution are significant challenges limiting the widespread application of AlGaN-based flip-chip deep-ultraviolet (DUV) LEDs. Herein, a novel triangular island-shaped chip structure designed to mitigate current crowding and enhance device reliability. Although this structure exhibits increased leakage current due to etching damage and the reduced effective light-emitting area compared to the interdigitated structure, it demonstrates lower operating voltage and higher wall-plug efficiency at high currents. Optical emission distribution tests confirm that the triangular island-shaped structure effectively reduces current crowding and achieves uniform light emission. After 500 h of aging, the optical power retention of the triangular island-shaped structure remains at 97.6%, and the L70 lifetime, as predicted by a lifetime model, is extended by 45% compared to the interdigitated structure. These findings highlight the critical role of mitigating current crowding in improving the reliability of AlGaN-based DUV LED chip structures. [ABSTRACT FROM AUTHOR]

Flip-chip bonding technology has been extensively applied in the semiconductor packaging field given the recent increase in demand for electronic products requiring miniaturization and high performance. In this study, a high-temperature long-term reliability evaluation was performed to evaluate the metallurgical reaction and mechanical properties at the Sn-2.3Ag (wt%) flip-chip solder bump joints. Isothermal aging was performed for up to 2000 h at 150 °C. A Ni 3 Sn 4 intermetallic compound (IMC) was formed at the interface of the solder joints, and the thickness of the IMC layer increased as the isothermal aging time increased; however, the thickness of Ni under bump metallization (Ni UBM) layer was decreased during the growth of the IMC. Linear regression analysis showed that the growth thickness of the IMC layer and the consumption thickness of the Ni UBM layer varied linearly as functions of the square root of the isothermal aging time. Based on this analysis, the growth rate constant of the IMC layer and consumption rate constant of the Ni UBM layer were 0.000756 and 0.000303 μm/s1/2, respectively. Thereafter, shear tests were performed to evaluate the mechanical properties of the solder joints. As the isothermal aging time increased, the variation of shear strength was not large. However, the shear strength decreased slightly and then remained constant. As a result of the analysis of the fractured surface, most conditions exhibited ductile fracture behavior inside the solder bump, while in the case of specimens isothermally aged for 500, 1000, 1500, and 2000 h, cratering occurred. By observing the changes in the fracture mode, the ductile fracture behavior became less prominent, and the occurrence of cratering tended to become more prominent as the isothermal aging time increased. [Display omitted] • We assessed the long-term reliability of Sn-2.3wt.%Ag flip-chip solder bump joints. • Isothermal and shear tests evaluated the solder joints' mechanical properties. • The thickness of the IMC (solder-joint interface) increased as aging time increased. • The shear strength decreased and then remained constant as aging time increased. • Aging time led to more/less prominent ductile fracture behavioral/cratering responses. [ABSTRACT FROM AUTHOR]

• An active technology to enhance uniformity and rate of heat transfer in a latent heat thermal energy storage (LHTES) unit is proposed. • The new method concerns flipping LHTES at appropriate stages of the phase change process is investigated. • Analysis is conducted on phase transition fraction, phase interface, temperature interface distribution, velocity interface distribution, and heat storage capacity. • The response surface methodology (RSM) is adopted to analyze and determine the optimal flipping phase transition fraction. • Guidelines to design phase change thermal control devices relevant for spacecraft thermal management are indicated. Latent heat storage technology has made significant contributions to solving the problem of unstable renewable energy supply. Related research indicates that phase change devices are essential for the stability of spacecraft temperature control systems. However, phase change material (PCM) has low thermal conductivity, which reduces device thermal storage and release efficiency. Moreover, the PCM heat transfer performance is further affected by movements such as attitude adjustment during the launch and operation of spacecraft. This paper adopted active heat transfer enhancement technology to enhance uniformity and rate of heat transfer in latent heat thermal energy storage (LHTES) unit. A new method is presented on flipping LHTES unit at appropriate stages of the phase change process, namely flipping enhancement technology. This method effectively uses the benefits of natural convection to enhance heat transfer, reducing the storage and release time of LHTES systems. A physical model was established building upon verification with data in literature, and the effect of flipping under different phase transition fractions on melting and solidification performance within the square cavity was discussed through numerical simulation. Further analysis was conducted on factors including phase transition fraction, phase interface, temperature interface distribution, velocity interface distribution, and heat storage capacity. Finally, the response surface methodology (RSM) was adopted to analyze and determine the optimal flipping phase transition fraction. The research results indicate that flipping improves the heat transfer efficiency of LHTES. Flipping significantly enhances heat transfer 3–5 times during melting compared to solidification process. As the phase transition fraction increases, the complete melting/solidification time demonstrates a trend of decline followed by an increase. Through single factor analysis, the optimal flipping liquid fraction is 51.65 % during the melting process, leading to a substantial decrease in complete melting time by 25.71 %. Based on this, the optimal phase transition fraction combination of melting first and then solidification was explored, which shortened the melting-solidification full cycle time by 12.96 %. This study investigates the melting/solidification performance of LHTES unit under flip conditions, which guides the design of phase change thermal control devices and contributes to the field of spacecraft thermal management. [ABSTRACT FROM AUTHOR]

The rapid development of semiconductor packaging technology has accelerated the applications of flip-chip bonding technology using fine-pitch micro bumps and Cu pillar bumps. These micro-bump systems are composed of metallic Cu and Sn. The properties of the Cu- and Sn-based bonding materials applied in these technologies have a significant effect on the mechanical properties and long-term reliability of micro-joints. This study focuses on the effects of the grain size and orientation of the Cu substrate on the formation and growth of intermetallic compounds (IMCs) at the Sn/Cu interface. The Cu substrate was annealed from 200 to 1000 °C to alter its grain size, which was measured via electron backscatter diffraction analysis. Sn-3.0Ag-0.5Cu (SAC) solder paste was printed onto the Cu substrate, and the Sn/Cu interfacial microstructure was observed by scanning electron microscopy and energy-dispersive X-ray spectroscopy after the reflow soldering process. A thin IMC formed on substrates with small grain sizes, whereas larger grain sizes resulted in the formation of thick and elongated IMCs. In addition, the IMC growth exhibited a specific directional preference in the (2 1 ̅ 1 ̅ 0) direction on substrates annealed at 1000 ℃. The effects of the Cu grain size and orientation on the interfacial reactions and growth of IMCs were compared and analyzed by observing IMCs formed at the SAC/Cu interface. Microstructural analysis revealed that controlling the Cu grain size and orientation significantly impacts the reliability of the solder joints. This study shows that the effect of grain size and orientation can be utilized to micro-solder joints, which can significantly enhance their mechanical strength and reliability. [Display omitted] • EBSD used to analyze annealed Cu substrate from 200–1000 °C to alter grain size. • Printed Sn-3.0Ag-0.5Cu (SAC305) solder paste onto the Cu substrate. • Observed SAC305/Cu interfacial microstructure by SEM and EDS. • IMC growth exhibited a specific directional preference in the (2 1 ̅ 1 ̅ 0) direction. • Compared effects of Cu grain size and orientation on interfacial reactions of IMCs. [ABSTRACT FROM AUTHOR]

• Micro-LED chips were prepared with 1920 × 1080 resolution, 8 μm pixel pitch, and 3175 PPI. • The effects of formic acid reflow temperature and reflow time on indium bump morphology were studied. • Height of mesa/metal layer inversely affects indium bump growth, impacting reflow effectiveness. • Flip-chip bonded micro-LED with CMOS for successful device function. Indium is acknowledged as a preferred material for micro-light-emitting diodes (micro-LEDs) flip-chip bonding within the industry, due to its favorable economic characteristics and low melting point. However, indium bumps fabricated via photolithography and thermal evaporation often exhibit irregular shapes and varying heights, and they readily oxidize in air to form a tightly adhered oxide layer (In 2 O 3), leading to flip-chip bonding failures and blind pixels. The reflow process can not only remove the oxide layer but also enhance bump uniformity. Nevertheless, literature on indium reflow predominantly focuses on planar substrates, with limited studies on high-resolution micro-LED chips for flip-chip bonding. This paper details the preparation of micro-LED chips with a pixel density (pixel per inch, PPI) of 3175. An indium bump array with a diameter of approximately 5 μm was prepared on the micro-LED chips using thermal evaporation technology. The influence of reflow time and temperature on indium bumps was thoroughly investigated by the formic acid reflow process, revealing that under the conditions of 270 °C and 180 s, the indium bumps with a narrower size distribution could be reflowed into spherical shapes on the micro-LED structure. Furthermore, an inversely proportional relationship was discovered between mesa/metal layer height and indium bump growth, which influenced the reflow effect. Ultimately, micro-LED chips were integrated with si complementary metal–oxide–semiconductor (CMOS) driver chips through flip-chip bonding technology, resulting in the successful functioning of the devices. [ABSTRACT FROM AUTHOR]

In this study, we report the effect of temperature on the microstructural evolution of flip chip solder joints under a temperature gradient of 2580 °C/cm at ambient temperatures of 100 °C, 125 °C, 150 °C, 160 °C, and 175 °C. The experimental results show that no microstructural evolution of un-stressed solders was found for samples tested at ambient temperatures of 100 °C and 125 °C, whereas thermomigration induced phase separation was observed for the samples tested at 150 °C, 160 °C, and 170 °C, suggesting that the thermomigration only occurred when the ambient temperature was higher than 150 °C. The theoretical derivation indicates that the threshold temperature difference needed to trigger thermomigration is found to be decreased with an increase in the ambient temperature. In addition, at a temperature gradient of 2580 °C/cm, the theoretical calculation indicated that a threshold temperature to trigger thermomigration is about 150 °C [ABSTRACT FROM AUTHOR]