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In this paper, a novel lumped electrical model for magneto-impedance sensors based on square-root of the frequency $f~( \sqrt {f} )$ is introduced. The model is mathematically derived using an alternative approximation of $\sqrt {f} $ that leads to an approximate transfer function with a finite number of products of poles and zeros. This approach can be easily implemented in circuit simulators, such as SPICE ( Simulation Program with Integrated Circuit Emphasis ) by means of current conveyors circuits and linear passive elements, such as resistors, capacitors, and inductors. These elements are interconnected using impedance converters based on Senani’s model to implement the poles and zeros of the transfer function. The scope and validity of the model were demonstrated through circuit simulations using spice, and compared with experimental results. The model can be used in the electronic signal conditioning stage for optimizing and/or for researching new cheap low-power practical electronics circuits.

The analysis and design trade-offs of a simple and economical technique to implement wideband low-voltage CMOS instrumentation amplifiers (IAs) based on indirect current feedback (ICF), are described. The input and an output transconductors consist of two super-source-followers and a resistor. As a result, the overall performance of the IA is enhanced. A thorough analysis of the proposed technique provided valuable insight on its operation. Two different realizations in 0.35-μm CMOS technology of an IA operating with a supply voltage of 3 V, are presented. In particular, a wide bandwidth single-stage IA with fixed voltage gain equal to 50 V/V and a low-power two-stage IA with externally programmable voltage gain, have been designed and characterized by extensive simulations. The simulated results of both circuits showed an improved response in terms of bandwidth, noise and power consumption, while their overall performance is comparable to other proposed approaches in terms of common-mode rejection ratio (CMRR) and linearity (THD). This work has been supported by the Spanish Ministerio de Ciencia, Innovación Universidades, under Grant RTI2018-095994-B-I00, and by the Junta de Extremadura R&D Plan and the European Fund for Regional Development (EFRD), under Grant IB18079 .

A novel current-mode CMOS RMS-to-DC converter using translinear techniques is introduced. It is based on a squarer/divider cell that is implemented using an electronically simulated loop with a novel biasing scheme that allows its operation in two quadrants. The cell is designed using a differential input current and a small signal first order filter to implement the voltage averaging, leading to a compact solution that can be used with low voltage supplies. The converter has been fabricated in a standard 130-nm CMOS process, and measurement results are provided to demonstrate the feasibility of the system. This work was supported in part by Agencia Estatal de Investigación/Fondo Europeo de Desarrollo Regional under Grant TEC2016-80396-C2-1-R, and in part by the Obra Social La Caixa - Fundación Caja Navarra (Convocatoria 2018 de Captación de Talento).

A complete current-mode Automatic Gain Control (AGC) system is introduced in this paper. It is based on novel Piece-Wise Linear (PWL) exponential and logarithmic pre-distortion circuits to obtain constant time responses for input abrupt changes. The system has been fabricated in 0.13μm CMOS technology and measurement results are provided to demonstrate the viability of the system. The settling time of the designed AGC circuit is 6.09μs for a 6dB input step with a compression factor equal to 3.55, a power consumption of 12mW, and a chip area of 0.04mm2.

SUMMARY Nowadays, the design of magneto-impedance (MI) sensors requires the development of lumped circuit models that can be simulated through equivalent impedance circuits relied on Bessel functions. A new impedance model based on Senani's equivalent using the zeros of Bessel functions is developed in this paper. The model allows to describe the impedance as a transfer function that can be easily synthesized by means of current conveyor circuits and passive elements. The mathematical representation was verified under simulation of transfer functions involving different number of poles and zeros. Moreover, the model has been verified using SPICE simulations and measurement results from a fabricated prototype demonstrating its scope and validity. Finally, a study of finite tracking errors of CCIIs used in the implementation of magneto-impedance sensor has been realized. Copyright © 2014 John Wiley & Sons, Ltd.

A compact transconductor based on transistors operating in the triode region is presented. A novel V---I conversion stage made up of current dividers is proposed. The circuit allows tunability by adjusting a dc current and the transconductance is independent of transconductance parameter of the triode transistors. Besides, the circuit is simple because feedback structures to fix source-drain voltages of triode transistors are not needed, saving area and featuring low power consumption. Measurement and simulation results are presented and analyzed for validating the proposed technique.

A novel fully differential current-mode multiplier based on a translinear (TL) loop is presented. The transistors that form the TL loop are working in the triode region, and a novel biasing scheme is used, allowing operation in two quadrants. The biasing circuitry is designed using simple current conveyors and a common-mode control circuit. Measurement results for a chip fabricated in a 0.5-μm CMOS technology are shown to demonstrate the feasibility of the technique. Furthermore, an analysis of second-order effects is also reported.

A CMOS current-mode analog multiplier/divider circuit is presented. It is suited to standard CMOS fabrication and can be successfully employed in a wide range of analog signal processing applications. Measurement results for a 0.5 μm CMOS test chip prototype verify the approach employed. The circuit consumes 120 μW using a single supply voltage of 1.5 V and requires a silicon area of 150 × 140 μm.

In this paper a lumped circuit model of magneto-impedance (MI) sensors that can be easily implemented in Spice-like simulators is proposed. The model is based on the equivalent circuit of a Pade's approximation derived from the impedance relied on Bessel functions. Thus, the model can simulate the transient and frequency responses from DC to several megahertz for a fix external magnetic field. Besides, the model can predict the impedance changes of the sensors as a nonlinear function of an external magnetic field via behavioral sources. This allows simulating MI sensors using magnetic feedback for controlling their response to improve linearity and dynamic range. The model has been verified using Spice simulations together with measurement results from a discrete prototype for generating the pulse voltage source, a simple modulation-type configuration, and a feedback structure. Copyright © 2010 John Wiley & Sons, Ltd.

Different design procedures to operate MOS translinear loops at low supply voltage are presented. They utilize innovative biasing strategies based on flipped voltage followers and floating batteries. An alternate topology based on coupled negative feedback loops is also introduced. Simulation and measurement results for various test chip prototypes validate the proposed techniques and allow comparison among them.

A 4th order Butterworth Gm-C filter based on a low-power design technique employing Floating-Gate MOS (FGMOS) transistors is presented. It consists in a topological rearrangement of conventional fully-differential Gm-C structures decreasing the number of active blocks of the filter and relaxing the transconductor requirements at transistor level. Moreover, high linearity is obtained at low and medium frequencies of the pass band. Measurement results from a test chip prototype in a 0.5 μm standard CMOS n-well process are provided and compared with other published circuits, corroborating the advantages of the proposed topology. A static power consumption of 0.76 mW for a 3.3 V supply voltage has been obtained, with a BW tunable from 300 kHz to 850 kHz.

An integrator employing the log-domain principle and fabricated in a 0.8-/spl mu/m CMOS process is presented. It uses floating-gate MOS transistors biased in weak inversion to achieve low-voltage operation and low power consumption. The circuit does not suffer from initial charge trapped in the floating gates, thus not requiring postfabrication charge removal. It can be frequency tuned over more than three decades, from 25 Hz to 35 kHz, and uses a 1.2-V single supply to achieve a dynamic range at 1% THD of 75 dB thanks to its balanced class-AB operation. For cutoff frequencies in the range of 100 Hz, the supply voltage can be reduced down to 1 V. The circuit occupies an active area of 0.1 mm/sup 2/ and dissipates 4.7 /spl mu/W. The technique employed can be readily extended to high-order filters.

A novel first-order CMOS log-domain filter is presented. The internal voltage swing compression due to its instantaneous voltage companding nature, together with the use of Floating-Gate MOS transistors and its class AB differential topology, allows operation with a single 1 V supply while maintaining at the same time a large input range. Moreover, operation in weak inversion leads to very low power consumption. The filter can be tuned in more than one decade through its bias currents. Simulation and measurement results of an experimental prototype fabricated in a 0.8 μm CMOS technology demonstrate on silicon the feasibility of the proposed technique, which can be readily extended to higher-order filters.

Two novel nonlinear CMOS transconductors that can be employed for building CMOS current-mode filters are presented and their performances compared to formerly proposed topologies aimed at the same goal. The first one is based on a previous topology proposed by the authors, where a new biasing procedure leads to an improved performance for low supply voltages. The second one follows a novel approach, based on cascading a transresistor and a transconductor. The analysis is complemented with a more general approach based on the identification of translinear loops present in the circuit. Both nonlinear transconductors can operate at supply voltages as low as one V GS plus two V DS of a saturated MOSFET. CMOS current-mode filters based on these blocks are built following companding techniques, and their correct operation is validated by simulation and experimental results.

A compact, wide dynamic range, four-quadrant analog CMOS current multiplier is presented. The use of floating DC level shifters (floating batteries) made by resistors and current sources allows low supply voltages while maintaining at the same time a large input range and low harmonic distortion. Measurement results for an experimental prototype in a 0.8 μm CMOS technology demonstrate on silicon the proposed technique.

A new family of two stage op-amps with broadband open loop response is introduced. These have a significant reduction of the DC open loop gain and maintain a high gain at frequencies as low as 1 Hz. This provides them with low DC offset. The proposed circuits are based on the Quasi-Floating Gate (QFG) technique, using a novel implementation for active loads that provides a very low effective resistance at DC and very-low frequencies without penalizing the high resistance at the pass band gain significantly. Moreover, a wide-band AC coupling structure also based on QFG transistors has been combined with the proposed technique, rejecting both the differential input DC voltage and the offset introduced by the circuit. These features make the proposed op-amps suitable for biological signal processing, where small amplitude signals are commonly affected by large DC offsets. Cadence simulation results employing a 0.5 micrometers technology are provided for validating the proposed circuits.

This chapter is devoted to review the static and dynamic translinear paradigm in the last years (2000–2011). Many papers have been written since then extending the application fields, proposing novel and new analog circuits and systems based on this principle, where MOS transistors are working in new regions of operation. These ongoing researches on translinear circuits arised of the requirements of low-power and low-voltage, which are forcing the technology at its maximum performance, and this paradigm can be an excellent solution. The chapter is presented as a summary of the advances in this field from different perspectives such as applications, circuits, and regions of operation of transistors, emphasizing the advantages and drawbacks. Also, some unsolved general trends are mentioned and research lines are described with the aim of identifying the main frame for this paradigm.

In this paper a novel CMOS latch is designed using a class-AB transconductor as a core. The static latch behavior is studied using a homotopy method which allows highlighting sufficient conditions for the transconductor to become a latch. These last conditions are general and can be used for the design of new latches and comparators. The proposed latch features high speed together with high power efficiency inherited of class-AB transconductor. Besides, the latch with low-impedance loads can be used for low-swing mixed-signal applications and current-mode differential logic circuits. Simulation results using a 0.18u CMOS technology are presented in order to support the proposed study and circuits.

In this paper a Spice model of magneto-impedance sensors is proposed. The model is based on the equivalent circuits of a Pade's approximation derived from the impedance relied on Bessel functions. The resulting model is fast and acceptably accurate since only lumped electrical passive elements are required. Besides, it can predict the nonlinear frequency response from DC to several megahertz taking into account the transverse permeability changes due to an external magnetic field. The model is verified using Spice simulations together with measurements results from a discrete prototype for generating the pulse voltage source and a simple modulation type configuration.

Fabricated Ag/TiO2/ITO devices, that show memristive properties, have been measured and their electrical variables were characterized. A piecewise nonlinear methodology is used to recast the model of the device in a range-dependent polynomial. The resulting model is coded in a high-level hardware description language with the aim of incorporating the device into a simulation framework.