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Presence of defects in high-k dielectric materials will affect device’s electrical properties, thus, defect/material characterization is of great importance. We present a simulation-based methodology relying on an accurate description of charge trapping and transport that is useful to extract relevant information on material and defect characteristics. This methodology was applied to cerium oxide and lanthanum oxide high-k dielectric materials and as a result, material properties alongside defect characteristics were extracted. Consequently, main charge conduction mechanism was identified to be trap-assisted tunneling (TAT).

A multiscale simulation platform predicts the effect of atomic level defects in thin films on the electrical characteristics of nanoscale devices and identifies ways to engineer these defects to achieve optimum performance and reliability in logic and memory circuits.

Memristor-based neuromorphic systems have been proposed as a promising alternative to von Neumann computing architectures, which are currently challenged by the ever-increasing computational power required by modern artificial intelligence (AI) algorithms. The design and optimization of memristive devices for specific AI applications is thus of paramount importance, but still extremely complex, as many different physical mechanisms and their interactions have to be accounted for, which are, in many cases, not fully understood. The high complexity of the physical mechanisms involved and their partial comprehension are currently hampering the development of memristive devices and preventing their optimization. In this work, we tackle the application-oriented optimization of Resistive Random-Access Memory (RRAM) devices using a multiscale modeling platform. The considered platform includes all the involved physical mechanisms (i.e., charge transport and trapping, and ion generation, diffusion, and recombination) and accounts for the 3D electric and temperature field in the device. Thanks to its multiscale nature, the modeling platform allows RRAM devices to be simulated and the microscopic physical mechanisms involved to be investigated, the device performance to be connected to the material&rsquo, s microscopic properties and geometries, the device electrical characteristics to be predicted, the effect of the forming conditions (i.e., temperature, compliance current, and voltage stress) on the device&rsquo, s performance and variability to be evaluated, the analog resistance switching to be optimized, and the device&rsquo, s reliability and failure causes to be investigated. The discussion of the presented simulation results provides useful insights for supporting the application-oriented optimization of RRAM technology according to specific AI applications, for the implementation of either non-volatile memories, deep neural networks, or spiking neural networks.

In this paper we present a comprehensive examination of the characteristics of complex Random Telegraph Noise (RTN) signals in Resistive Random Access Memory (RRAM) devices with TiN/Ti/HfO2/TiN structure. Initially, the anomalous RTN (aRTN) is investigated through careful systematic experiment, dedicated characterization procedures, and physics-based simulations to gain insights into the physics of this phenomenon. The experimentally observed RTN parameters (amplitude of the current fluctuations, capture and emission times) are analyzed in different operating conditions. Anomalous behaviors are characterized and their statistical characteristics are evaluated. Physics-based simulations considering both the Coulomb interactions among different defects in the device and the possible existence of defects with metastable states are exploited to suggest a possible physical origin of aRTN. The same simulation framework is also shown to be able to predict other temporary phenomena related to RTN, such as the temporary change in RTN stochastic properties or the sudden and iterative random appearing and vanishing of RTN fluctuations always exhibiting the same statistical characteristics. Results highlight the central role of the electrostatic interactions among individual defects and the trapped charge in describing RTN and related phenomena.

We present in this paper a multiscale modeling platform that is used to study the effect of atomic level defects on the electrical characteristics of nanoscale devices. This allows identifying ways to engineer material (and defects) and device properties to achieve optimum performance and reliability in logic and memory circuits. Atom scale defects in multilayer thin film material stacks have a profound effect on the electrical performance and reliability of nanoscale electronic devices. These defects include both point defects such as vacancies and interstitial ions as well as extended defects such as grain boundaries, dislocations. We developed a multiscale modeling platform connecting the atomic material properties to the electrical device performance, which allows understanding the optimum material characteristics for different types of logic devices and memory cells. These include logic devices, conventional memories (e.g. DRAM, 3D-NAND) as well as emerging devices (e.g. RRAM, PCM). The simulations allow learning how to scale these technologies through material and process improvement and how to co-optimize materials and devices. I. MULTISCALE MODELING Figure 1 shows the flowchart of the multiscale multiphysics simulation platform along with its main blocks [1]. The ab-initio material properties relevant for the electrical device performances (e.g. bandgap, permittivity, defects energies, defect diffusion barrier ...) are computed using DFT calculations (gray portion). These material properties are then used for the device level simulations (green portion), and the output device electrical characteristics allows calibrating the circuit simulations (yellow portion). The device simulator couples classical and quantum charge transport mechanisms with stress induced material changes (e.g. atomic breakage, creation and diffusion of ions/vacancies), whose occurrence probability is calculated by accounting for the temperature increase and power dissipation associated with the current. The charge transport mechanisms include drift/diffusion in conduction band (CB) or valence band (VB), which is the primary carrier transport mode in semiconductors, and Trap Assisted Tunneling (TAT), which is the dominant mechanism in dielectrics and amorphous semiconductors. Defects with energy levels in the bandgap play a crucial role in the conduction, assisting electron transfer. The charge transport is coupled to the kinetics of atomic level material modifications caused by electrical and thermal stresses encompassing distortion and breakage of bonds, diffusion of vacancies and interstitial ions leading to changes in local fields, stoichiometry and phase changes including ferroelectricity. This allows modeling the reliability of devices to be calculated in addition to static electrical characteristics as well as the device variability. In this presentation, we will show how this multiscale simulation platform can be used to extract defect properties for advanced logic stack as well as to understand the physics of operation of RRAM devices. II. UNDERSTANDING DEFECT IMPACT ON LOGIC STACKS The multiscale approach presented in Section II can be used to characterize and understand the role of the dielectric defects on device electrical characteristics and reliability. Oxide defects are at the bases of the most relevant reliability phenomena in both logic and memory devices, e.g. Random Telegraph Noise (RTN), Bias Temperature Instabilities (BTI), Stress Induced Leakage Currents (SILC) and breakdown (BD). Identifying their nature and their spatial/energy distributions in the dielectric stack is crucial for process optimization and device operation/reliability improvement. The developed simulation framework implements a fast defect spectroscopy (DS) technique based on the modeling and simulation of the charge transport within the dielectric. This technique is applied to identify the defects responsible for I-V, CV. GV in a variety of different stack configurations. III. UNDERSTANDING RRAM OPERATIONS We used this modeling platform proposed to investigate the kinetics of the operation processes of HfO2-based RRAM devices. Forming, set and reset operations are consistently described within the modeling framework described in Section II, accounting for species (i.e. O ions and vacancies) generation, recombination and diffusion. Simulations can reproduce the evolution of the current simulated for a full cycle comprised by forming, reset and set operations. The simulated current exhibits the expected features: an abrupt jump at forming, a gradual reduction in reset, and a lower set voltage compared to forming. The evolution of potential, temperature and generated oxygen vacancies and ions during simulations can be monitored to gain insights on the mechanisms controlling device operations, including the structural changes such as the creation and disruption of the conductive filament, as well as the high temperature reached during forming. IV. REFERENCES [1] GINESTRATM , http://www.mdlsoft.com Fig 1: Schematic flow chart describing the main blocks of multiscale simulation platform. Figure 1

The impact of device-to-device statistical variation on Program/Erase (P/E) transients of planar TANOS devices is investigated using a multi-scale simulation approach. Atomic-level material and defect properties are first extracted from experimental results and then employed to study variability of the flat-band voltage shift. Erase characteristics are observed to be more affected by statistical variation. Interestingly, by adjusting temperature, gate voltage and/or blocking layer thickness, an optimized operating condition can be reached such that variability in 3D TANOS arrays is minimized.

In this chapter, we focus on the necessary interplay between “modeling for characterization” and “characterization for modeling” approaches for a detailed yet manageable physics-based description of resistive random access memory (RRAM) device operations. Particularly, the “modeling for characterization” is based on a multiscale modeling platform that accounts for all the relevant physical mechanisms involved in charge transport and structural changes at the basis of resistive switching. The “characterization for modeling” instead provides a set of specific characterization methodologies to support the simulation engine and to confirm its results. The excellent agreement between the multiscale model predictions and the experimental results obtained on different material systems and device structures confirms the accuracy of the proposed solution. This makes the proposed platform a tool for the analysis of RRAM technologies and TCAD-assisted material/device codesign, potentially accelerating the introduction of RRAM-based solutions for several different applications.

We perform experiments and device simulations to investigate the origin of current-voltage (I-V) linearity of TaOX-based resistive switching memory (RRAM) devices for their possible application as electronic synapses. By using electrical characterization and simulations, we link the electrical characteristics (linear or nonlinear I-V) to the microscopic properties of the conductive filament (CF). Our findings indicate that the shape and the thermal properties of the CF region are crucial to achieve linear I-V characteristics. These results allow optimizing the I-V curve linearity of TaOX-based RRAM devices, explaining the wide range of linear I-V characteristics experimentally observed on RRAM device obtained. When weight sum operation using SPICE simulations is performed, the read current is improved under the condition of linear I-V characteristics due to current loss minimization.

Top-gated, few-layer MoS2 transistors with HfO2 (6 nm)/Al2O3 (3 nm) gate dielectric stacks are fabricated and electrically characterized by capacitance–voltage (C–V) measurements to study electrically active traps (Dit) in the vicinity of the Al2O3/MoS2 interface. Devices with low Dit and high Dit are both observed in C–V characterization, and the impact of H2/N2 forming gas annealing at 300 and 400 °C on the Dit density and distribution is studied. A 300 °C anneal is able to reduce the Dit significantly, while the 400 °C anneal increases defects in the gate stack. Simulation with modeled defects suggests a sizable decrease in Dit, half the amount of positive fixed charge in the dielectric, and slightly increased unintentional doping in MoS2 after a 300 °C anneal. In the as-fabricated devices displaying high Dit levels, the energy distribution of the Dit located at the Al2O3/MoS2 interface is continuous from the conduction band edge of MoS2 down to 0.13–0.35 eV below the conduction band edge. A plausible Dit origin in our experiments could come from the unexpected oxygen atoms that fill the sulfur vacancies during the UV–O3 functionalization treatment. The border trap concentration in Al2O3 is the same, both before and after the anneal, suggesting a different origin of the border traps, possibly due to the low-temperature atomic-layer-deposited process.

Ultra-thin dielectric breakdown (BD) has been studied in-depth for SiO 2 and HfO 2 in CMOS devices in the past. In general, the degradation physics and model governing BD in these materials are assumed to hold true for MgO. This study provides evidences that this assumption may not be true by investigating in detail the statistical nature of BD in MgO dielectrics for wide range of operating conditions, relevant to its application as spin transfer torque magnetic random access memory (STT-MRAM). Our analysis shows that - MgO BD is polarity dependent; lifetime is lower for bipolar (AC) stress; defect generation is clustered in space and time; self-heating dominates for low frequencies; temperature within the percolation path exhibits fast transients (thermal runaway); Weibull model does not apply to BD statistics and defect generation (F+) is charge fluence driven (and field assisted) with power law model being most suited for lifetime extrapolation.

Discovery of ferroelectric (FE) behavior in HfO 2 removed the compatibility roadblocks between the state-of-the-art CMOS and FE memories. Even though FE FETs (FeFETs) are scaled into 22 nm nodes and beyond, the limits of the technology as well as the physical mechanisms and reliability are still under research. In this paper we successfully developed a multiscale modeling platform to understand the interplay between the FE switching and charge trapping. Starting from the nucleation theory and rigorous charge transport modeling we present for the first time a self-consistent modeling framework we used for investigation of reliability and variability in FeFETs.

We investigated possible mechanisms for correlated defect production in amorphous (a) SiO 2 and HfO 2 films under applied stress bias using ab initio simulations. During bias application, electron injection into these films may lead to the localization of up to two electrons at intrinsic trapping sites which are present due to the natural structural disorder in amorphous structures. Trapping two electrons weakens Si-O and Hf-O bonds to such an extent that the thermally activated creation of Frenkel defects, O vacancies and O2- interstitial ions, becomes efficient even at room temperature. Bias application affects defect creation barriers and O2- interstitial diffusion. The density of trapping sites is different in a-SiO 2 and a-HfO 2 . This leads to qualitatively different degradation kinetics, which results from different correlation in defect creation in the two materials. These effects affect TDDB statistics and its dependence on the film thickness.

After more than a decade working with graphene there is still a preoccupying lack of commercial devices based on this wonder material. Here we report the use of high-quality solution-processed graphene sheets to fabricate ultra-sharp probes with superior performance. Nanoprobes are versatile tools used in many fields of science, but they can wear fast after some experiments, reducing the quality and increasing the cost of the research. As the market of nanoprobes is huge, providing a solution for this problem should be a priority for the nanotechnology industry. Our graphene-coated nanoprobes not only show enhanced lifetime, but also additional unique properties of graphene, such as hydrophobicity. Moreover, we have functionalized the surface of graphene to provide piezoelectric capability, and have fabricated a nano relay. The simplicity and low cost of this method, which can be used to coat any kind of sharp tip, make it suitable for the industry, allowing production on demand.

In this paper, we investigate the random telegraph noise (RTN) in hafnium-oxide resistive random access memories in high resistive state (HRS). The current fluctuations are analyzed by decomposing the multilevel RTN signal into two-level RTN traces using a factorial hidden Markov model approach, which allows extracting the properties of the traps originating the RTN. The current fluctuations, statistically analyzed on devices with a different stack reset at different voltages, are attributed to the activation and deactivation of defects in the oxidized tip of the conductive filament, assisting the trap-assisted tunneling transport in HRS. The physical mechanisms responsible for the defect activation are discussed. We find that RTN current fluctuations can be due to either the coulomb interaction between oxygen vacancies (normally assisting the charge transport) and the electron charge trapped at interstitial oxygen defects, or the metastable defect configuration of oxygen vacancies assisting the electron transport in HRS. A consistent microscopic description of the phenomenon is proposed, linking the material properties to the device performance.

We propose a model describing the operations of hafnium oxide-based resistive random access memory (RRAM) devices at the microscopic level. Charge carrier and ion transport are self-consistently described starting from the leakage current in pristine HfO2. Material structural modifications occurring during the RRAM operations, such as conductive filament (CF) creation and disruption, are accounted for. The model describes the complex processes leading to a formation of the CF and its dependence on both electrical conditions (e.g., current compliance, voltage stress, and temperature) and device characteristics (e.g., electrodes material and dielectric thickness).

We present in this paper a novel defect spectroscopy technique for extracting defect and material properties of gate oxides and dielectrics used for memory devices (e.g. DRAM, RRAM). The method is based on the correlate simulation of electrical characteristics (IV, CV, GV, BTI), to allow the determination of the energy distribution and depth profile of atomic defects within the material bandgap. This novel defect spectroscopy technique is applied to MOSFET gate stacks with Si and InGaAs, and to DRAM capacitors.

In modern electronic devices, a variety of novel materials have been introduced such as transition metal oxides, chalcogenides, ferroelectric, and magnetic materials. The electrical response of such materials, used also as active layers, is strongly affected by atomic defects, which affect device performances, variability, and reliability. Extracting the defect properties (i.e., density, energy, and atomic nature) is, thus, crucial to both engineer the performances of electron devices and correctly project their scaling potential and reliability. In this paper, we propose a simple method to extract the atomic properties of defects from the thermal activation energy of the leakage current using a charge trapping relaxation model.

The Collaborative Innovation Center of Suzhou Nano Science & Technology, the Jiangsu Key Laboratory for Carbon-Based Functional Materials & Devices, and the Priority Academic Program Development of Jiangsu Higher Education Institutions are also acknowledged. Stanford co-authors acknowledge support from the Non-volatile Memory Technology Research Initiative (NMTRI). An Chen from IBM is acknowledged for revision of section 5. Alok Ranjan from Singapore University of Technology and Design is acknowledged for useful discussion on section 3.5., Resistive switching (RS) is an interesting property shown by some materials systems that, especially during the last decade, has gained a lot of interest for the fabrication of electronic devices, being electronic non-volatile memories those that have received most attention. The presence and quality of the RS phenomenon in a materials system can be studied using different prototype cells, performing different experiments, displaying different figures of merit, and developing different computational analyses. Therefore, the real usefulness and impact of the findings presented in each study for the RS technology will be also different. In this manuscript we describe the most recommendable methodologies for the fabrication, characterization and simulation of RS devices, as well as the proper methods to display the data obtained. The idea is to help the scientific community to evaluate the real usefulness and impact of an RS study for the development of RS technology., This work has been supported by the Young 1000 Global Talent Recruitment Program of the Ministry of Education of China, the National Natural Science Foundation of China (grants no. 61502326, 41550110223, 11661131002), the Jiangsu Government (grant no. BK20150343), and the Ministry of Finance of China (grant no. SX21400213).

In this paper, a multiscale modeling platform for neuromorphic computing devices connecting the atomic material properties to the electrical device performances is presented. The main ingredients of the modeling platform are discussed in view of the different technologies (e.g. RRAM, PCM, FTJ) proposed for 3D integrated neuromorphic computing.

We present a multiscale modeling platform that exploits ab-initio calculation results and a material-related description of the most relevant defect-related phenomena in dieledtrics (charge trapping and transport, degradation and atomic species motion) to interpret and understand the electrical characteristics of OxRAM memory devices for non-volatile memories and neuromorphic applications. Simulation results provide a deep and quantitative understanding of the factors controlling device operation. The proposed multiscale modeling platform represents a powerful tool for investigating material properties and optimizing device performances and reliability.

9th IEEE International Memory Workshop (IMW), Monterey, CA, MAY 14-17, 2017; International audience; This work analyzes the self-rectifying behavior and the response under identical pulses of tri-layer RRAMs in crossbar arrays to implement the synapse function. Our finding shows that tri-layer RRAMs allow to achieve a stable Low Resistance State (LRS) without complete oxide breakdown. The first RRAM layer works as tunneling barrier allowing to achieve on-state half-bias nonlinearity. Thanks to LRS nonlinearity the power consumption during synaptic programming is reduces of one order of magnitude. Analog switching under identical pulses allows to emulate synaptic plasticity. The multilevel states of conductance have been explained by the enlargement of the conductive filament (CF) in the broken oxide by means of physical based simulations.

In this paper we report about the scaling perspective of ultra-scaled HfO 2 Resistive Random Access Memory devices. Due to filamentary conduction, the scalability of these devices is considered to be ultimately limited by the size of the conductive filament. However, even though the precise size and shape of the filament is not fully elucidated, it is widely accepted that its size is mainly controlled by the current compliance. In turn, the latter sets the operating current level of the cell. The reduction of the current level is nevertheless accompanied by performance instabilities, which are the main reliability threat for low-current operations. The resulting tradeoff raises concerns about the scalability potential of RRAM devices. In this work, we combine device-level measurements, Conductive Atomic-Force Microscopy (C-AFM), and physics-based simulations of HfO 2 RRAM devices to elucidate the reason for these instabilities. Results clarify the scaling perspectives of ultra-low cell size (< 10×10 nm2) RRAMs and their reliability.

RRAM technology represents an attractive option for the embedded non-volatile memory systems. Optimizing the RRAM performance requires understanding the physical processes governing the electrical characteristics and identifying the major performance-driving forces from the standpoint of device structural properties and device operation conditions. We use a simulation model, which explicitly considers HfOx-specific nature of RRAM characteristics to understand at microscopic level the RRAM device operations [1-3]. This model is based on the description of the physical processes leading to the formation of the conductive filament and the subsequent resistive switching. The impact of the material properties are included at different levels (i.e. charge transport, ion diffusion, atomic bond breakage) by adopting a multi-scale approach. A full 3D description combined with a Monte-Carlo method is considered to account for the stochastic nature of microscopic RRAM mechanisms. The conductive filament formation is modeled as a metal-oxygen bond breakage and a subsequent out-diffusion of the released oxygen ions. The rates of the oxygen vacancy and ion generation are calculated using a thermochemical model [4]. The 3D temperature map is calculated from the power dissipation by solving the Fourier heat equation, while the power dissipated at isolated and extended defects is directly calculated from the charge transport model, Fig.1. The charge transport is described by a trap-assisted tunneling (TAT) model including carrier-phonon coupling and lattice relaxation [4], accounting for the role of grain boundaries as a preferential conductive spots [5]. The reduction of the relaxation energy with increasing the O vacancy density and the electron drift through the defect sub-band at very high O vacancy density are also included. The model successfully reproduces the current evolution during forming, Fig. 2, and the whole dynamics of the forming process including both charge transport (with the associated temperature increase) and ion diffusion, Fig. 1, as well as the characteristic dependencies on temperature and voltage ramp [1-3]. The concurrent description of charge transport and O ion diffusion allows understanding the effect of forming conditions on the stability of the conductive filament, which is found to be strongly controlled by ramp-rate of the forming pulse, which strongly affects the final ion position [1]. The simulations of the reset operation (bringing the device into high resistance state, HRS) shows that this process is controlled by re-oxidation of the filament tip caused by field-induced back-diffusion of oxygen ions. The charge transport in HRS is governed by TAT through O vacancies in the re-oxidized CF portion, Fig. 3. Simulations successfully reproduce the measured HRS current [2]. The activation and deactivation of O vacancies is found to be responsible of noise observed on HRS current, which is successfully simulated in both time and frequency domains, Fig. 3. Fig. 1. Current evolution during forming and the 3D maps of power dissipation, temperature and oxygen vacancy (blue) and ion (red) distributions, simulated on a TiN/TiOy/5nm-HfO2/TiN RRAM device biased at constant voltage of 1.7Va t the end of forming. Fig. 2. Current evolution measured and simulated during forming on a TiN/Ti/7nm-HfO2/TiN RRAM device. Fig. 3. a) Schematic illustration of the CF in HRS conditions. Simulations of RTN current fluctuations in time b) and frequency (power spectral density) domain. d) Measured and Experimental and simulated distribution of HRS current amplitude. References [1] L. Larcher, A. Padovani, O. Pirotta, L. Vandelli, G. Bersuker, Tech. Dig. IEDM, pp. 20.1.1-20.1.4, 2012. [2] G. Bersuker et al., J. Appl. Phys., Vol. 110, Issue 12, December, 2011. [3] L. Vandelli et al, Tech. Dig. IEDM, pp. 17.5.1-17.5.4, 2011. [4] L. Vandelli et al., Trans. Elect. Dev., Vol. 58, Issue 9, 2011. [5] O.Pirrotta et al., J. Appl. Phys. 114, 134503, 2013.

This paper presents a physics-based compact model for the program window in HfOx resistive random access memory devices, defined as the ratio of the resistances in high resistance state (HRS) and low resistance state (LRS). This model allows extracting the characteristics of the conductive filament (CF) in HRS. For a given forming current compliance limit, the program window is shown to be correlated to the thickness of the reoxidized portion of the CF in HRS, which can be modulated by the reset voltage amplitude. On the other hand, the statistical distribution of the memory window depends exponentially on the barrier thickness variations that points to the critical role of reset conditions for the performance optimization of RRAM devices.

We propose a physical model for the fast component ( \( s) of the positive bias temperature instability (PBTI) process in SiO x /HfO2 gate-stacks. The model is based on the electron-phonon interaction governing the trapping/emission of injected electrons at the preexisting defects in the dielectric stack. The model successfully reproduces the experimental time dependences of the \(V_{\mathrm {{TH}}}\) shift on both stress voltage and temperature. Simulations allow the extraction of the physical characteristics of the defects contributing to PBTI, which are found to match those assisting the leakage current in these stacks (i.e., oxygen vacancies).

In this paper we present a comprehensive physical model that describes charge transport and degradation phenomena in high-k stacks. The physical mechanisms are modeled using a novel material-related approach that includes in a self-consistent fashion the charge transport (dominated by defect-assisted contribution), power dissipation and temperature increase, defect generation, and ion and vacancy diffusion and recombination. The physical properties of defects, which play a crucial role in determining the electrical behavior of the high-k stacks, depend on their atomistic configurations, as calculated using ab-initio methods. This simulation framework represents a powerful tool to interpret electrical characterization measurements. In addition, it can be used to optimize logic and memory device stacks thanks to its predictive statistical capabilities that allow reproducing gate current, threshold voltage increase and time to breakdown (TDDB) statistics. Simulation results performed using this simulation package are shown to reproduce accurately leakage current, Stress-Induced Leakage Current (SILC), threshold voltage shift observed during Positive Bias Temperature Instability (PBTI) stress, TDDB in various dielectric stacks.

In this paper we analyze Random Telegraph Signal (RTS) noise and Power Spectral Density (PSD) in hafnium-based RRAMs. RTS measured in HRS exhibits fast and slow multilevel switching events. RTS characteristics are examined through novel color-coded time-lag plots and Hidden Markov Model (HMM) time-series analyses. Results are validated by comparing simulated and experimental PSD. Noise is examined at different reset conditions to provide an insight into the conduction mechanisms in HRS. Higher reset voltages are found to result in greater RTS complexity due to a larger number of active traps as confirmed by PSD.

We present a multiscale modeling platform that exploits ab-initio calculation results and a material-related description of the most relevant defect-related phenomena in dielectrics (charge trapping and transport, degradation and atomic species motion) to interpret the reliability and electrical characteristics of logic and memory devices. The model is used to identify and characterize the dielectric defects responsible for the charge transport and degradation in SiO x /high-k (HK) bi-layer logic devices and to investigate the kinetics of forming and switching operations of Hf-based RRAM memories. Simulation results provide a deep and quantitative understanding of the factors controlling device operation and reliability. The proposed multiscale modeling platform represents a powerful tool for investigating material properties and optimizing device performances and reliability.

We perform a comparative study of HfO2 and Ta2O5 resistive switching memory (RRAM) devices for their possible application as electronic synapses. By means of electrical characterization and simulations, we link their electrical behavior (digital or analog switching) to the properties and evolution of the conductive filament (CF). More specifically, we identify that bias-polarity-dependent digital switching in HfO2 RRAM is primarily related to the creation and rupture of an oxide barrier. Conversely, the modulation of the CF size in Ta2O5 RRAM allows bias-polarity-independent analog switching with multiple states. Therefore, when the Ta2O5 RRAM is used to implement a synapse in multilayer perceptron neural networks operated by back-propagation algorithms, patterns in handwritten digits can be recognized with high accuracy.

In this paper, we delve into one of the most relevant defects-related phenomena causing failures in the operation of modern nanoscale electron devices, namely Random Telegraph Noise (RTN). Due to its detrimental impact on devices and circuits performances, RTN mechanism must be thoroughly understood, which requires establishing a self-consistent framework encompassing automated measurement techniques, data analysis algorithms, and physics-based modeling. This platform is not only required to understand the physics of RTN-related failures, but also to enable RTN analysis as a tool to investigate device reliability. Starting from the analysis of RTN signal statistical properties, we propose a set of guidelines to perform correct RTN measurements and data analysis, in order to get reliable results that are needed for an unbiased physical interpretation. This is achieved by combining automated experiments with sophisticated data analysis, consistency check, and comprehensive physics-based simulations. RTN analysis is then applied to two different devices for logic and memory applications, respectively: FinFETs and RRAMs. Particularly, the analysis of the statistical properties of RTN simultaneously measured on the drain and on the gate current of FinFETs allows understanding the details of the defects generation during stress. The analysis of RTN measured during the read operation in RRAM devices allows understanding the physical origin of RTN in these devices and identifying the defects species involved in this phenomenon.

HfO2-based ferroelectrics reveal full scalability and CMOS integratability compared to perovskite-based ferroelectrics that are currently used in non-volatile ferroelectric random access memories (FeRAMs). Up to now, the mechanisms responsible for the decrease of the memory window have not been revealed. Thus, the main scope of this study is an identification of the root causes for the endurance degradation. Utilizing trap density spectroscopy for examining defect evolution with cycling of the device studied together with modeling of the degradation resulted in an understanding of the main mechanisms responsible for degradation of the ferroelectric behavior.