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This paper presents reconfigurable RF integrated circuits (ICs) for a compact implementation of an intelligent RF front-end for multiband and multistandard applications. Reconfigurability has been addressed at each level starting from the basic elements to the RF blocks and the overall front-end architecture. An active resistor tunable from 400 to 1600 /spl Omega/ up to 10 GHz has been designed and an equivalent model has been extracted. A fully tunable active inductor using a tunable feedback resistor has been proposed that provides inductances between 0.1-15 nH with Q>50 in the C-band. To demonstrate reconfigurability at the block level, voltage-controlled oscillators with very wide tuning ranges have been implemented in the C-band using the proposed active inductor, as well as using a switched-spiral resonator with capacitive tuning. The ICs have been implemented using 0.18-/spl mu/m Si-CMOS and 0.18-/spl mu/m SiGe-BiCMOS technologies.

A comprehensive investigation of the high-temperature characteristics of advanced SiGe heterojunction bipolar transistors (HBTs) is presented, and demonstrates that, contrary to popular opinion, SiGe HBTs are potentially well-suited for many electronics applications operating at temperatures as high as 300/spl deg/C.

The low-frequency noise in high-speed transistors generally increases (degrades) as device technologies down-scale for higher performance. Interestingly, the latest generation of deep-submicron SiGe HBTs breaks this trend, and we find record-low noise corner frequencies of 220 Hz in SiGe HBTs with a peak f T of 210 GHz. An explanation for this behavior based on a reduction of the number of dominant noisy traps is offered, and microscopic 2-D simulations of noise are used to support this claim and explore the origins and scaling limits of low-frequency noise in advanced SiGe HBTs.

This paper discusses and illustrates the key device design issues for SiGe BiCMOS HBTs suitable for wireless power amplifier (PA) applications. Experimental results addressing ruggedness, ac performance, and safe operating area for high-breakdown SiGe HBTs built in several generations of BiCMOS technology are presented. Implications of recent high-performance SiGe HBT scaling achievements for BiCMOS technologies targeting wireless PA applications are considered. Circuit results for GSM, PCS, GPRS, and EDGE front-end modules have been obtained. A one-chip solution is demonstrated, including control circuitry and switching functionality, that supports all GPRS, PCS, and EDGE modes featuring output power at 33.8 dBm and overall power added efficiency of 37% withstanding voltage standing wave ratio conditions of 15:1.

This work investigates the impact of collector-base (CB) junction traps on low-frequency noise in high breakdown voltage (HBV) SiGe HBTs. By comparing the base current and 1/f noise at the same internal emitter-base (EB) voltage of the standard breakdown voltage (SBV) and HBV devices, we show that the CB junction traps not only increase base current, but also contribute base current 1/f noise when high injection occurs. The individual 1/f noise contributions from the emitter-base junction traps and from the collector-base junction traps are separated. The dependence of the 1/f noise component on the corresponding base current component is determined, and shown to be different for the EB and CB junction traps. The dependence of the total 1/f noise on the total base current, however, remains the same before and after high injection occurs in the HBV device, which is approximately the same as that for the SBV device. The I/sub B/ contribution from the CB junction recombination current needs to be modeled for accurate I-V and 1/f noise modeling.

SiGe is having a major impact in device electronics. The most mature application is the SiGe BiCMOS technology which is in production throughout the world. The areas of most rapid growth are in CMOS where SiGe is being considered for a wide variety of elements including raised S/D, poly-SiGe Gates, in buffer layers to create a tensile strained Si layer, and as the conducting channel in MODFETs.

We show that silicon-germanium (SiGe) heterojunction bipolar transistors (HBTs) are naturally suited for space applications requiring operation of electronics at cryogenic temperatures, and present the first comprehensive investigation of the effects of gamma irradiation on the characteristics of SiGe HBTs operating at liquid nitrogen temperature (77 K). We find that exposure to 1 Mrad total dose at 77 K produces significantly less base current degradation than exposure at 300 K, and hence the total dose tolerance of SiGe HBTs, which is already excellent at room temperature without intentional hardening, improves with cooling. We compare 77 and 300 K radiation results in order to better understand the damage mechanisms.

The paper presents the results of an investigation of the proton tolerance of the multiple-threshold voltage and multiple-breakdown voltage device design points contained in a 0.18 /spl mu/m system-on-a-chip CMOS technology. The radiation response of the CMOS devices having three different device design configurations are characterized and compared for equivalent gamma doses up to 300 krad(Si), using the threshold voltage, off-state leakage, and effective mobility to assess the dc performance. All three CMOS device configurations show a very slight degradation of threshold voltage and effective mobility with increasing dose. We also present for the first time the frequency response and S-parameters of these RF CMOS devices under proton radiation. The S-parameters and cut-off frequency show little degradation up to 300 krad(Si) total dose. These results suggest that the CMOS devices in this 0.18 /spl mu/m SoC CMOS technology are well-suited for RF circuit applications in an ionizing radiation environment without intentional total-dose hardening.

We use proton irradiation to probe the origins of the geometry-dependent variation of low-frequency noise in 120 GHz SiGe heterojunction bipolar transistors (HBTs). Before irradiation, small-sized transistors show a strong variation in noise magnitude across many samples, whereas the noise in larger devices is more statistically reproducible. Although the noise magnitude shows little degradation after 2/spl times/10/sup 13/ p/cm/sup 2/ irradiation, the observed noise variation decreases. Its dependence on both geometry and bias is quantified. This fundamental geometrical scaling effect is investigated using theoretical calculations based on the superposition of generation/recombination (G/R) noise sources.

This paper presents the first 3-D simulation of heavy-ion induced charge collection in a SiGe HBT, together with microbeam testing data. The charge collected by the terminals is a strong function of the ion striking position. The sensitive area of charge collection for each terminal is identified based on analysis of the device structure and simulation results. For a normal strike between the deep trench edges, most of the electrons and holes are collected by the collector and substrate terminals, respectively. For an ion strike between the shallow trench edges surrounding the emitter, the base collects appreciable amount of charge. Emitter collects negligible amount of charge. Good agreement is achieved between the experimental and simulated data. Problems encountered with mesh generation and charge collection simulation are also discussed.

The effects of operating bias conditions on the proton tolerance of Silicon–Germanium (SiGe) heterojunction bipolar transistors (HBTs) are investigated for the first time. While this SiGe HBT technology is relatively insensitive to different bias conditions during radiation exposure, the cases with all terminals grounded and with the emitter–base junction reverse-biased show slightly enhanced degradation at proton fluences above 2 × 1013 p/cm2 compared to the other bias configurations, consistent with 2D simulations, and can thus be viewed as worst case conditions.

In this paper, we highlight the effectiveness and flexibility of SiGe BiCMOS as a technology platform over a wide range of performance and applications. The bandgap-engineered SiGe heterojunction bipolar transistors (HBTs) continue to be the workhorse of the technology, while the CMOS offering is fully foundry compatible for maximizing IP sharing. Process customization is done to provide high-quality passives, which greatly enables fully integrated single-chip solutions. Product examples include 40-Gb/s (OC768) components using high-speed SiGe HBTs, power amplifiers compatible for cellular applications, integrated voltage-controlled oscillators, and very high-level mixed-signal integration. It is argued that such key enablements along with the lower cost and higher yields attainable by SiGe BiCMOS technologies will provide competitive solutions for the communication marketplace.

As device scaling for higher performance bipolar transistors continues, the operation current density increases as well. To investigate the reliability impact of the increased operation current density on Si-based bipolar transistors, an accelerated-current wafer-level stress was conducted on 120-GHz SiGe heterojunction bipolar transistors (HBTs), with stress current density up to as high as J/sub C/=34 mA//spl mu/m/sup 2/. With a novel projection technique based on accelerated-current stress, a current gain shift of less than /spl sim/15% after 10/sup 6/ h of operation is predicted at T=140/spl deg/C. Degradation mechanisms for the observed dc parameter shifts are discussed for various V/sub BE/ regions, and the separation of the current stress effect from the self-heating effect is made based on thermal resistance of the devices. Module-level stress results are shown to be consistent with wafer-level stress results. The results obtained in this work indicate that the high-speed SiGe HBTs employed for the stress are highly reliable for long-term operation at high operation current density.

The influence of geometrical scaling on low-frequency noise in SiGe HBTs is presented. Small-size transistors show a strong variation in noise across many samples, whereas the noise in larger devices is more statistically reproducible. This size-dependent variation in noise can produce challenges for accurate compact modeling. This effect is investigated using reverse-bias emitter-base stress and calculations based on the superposition of generation/recombination noise.

The influence of proton exposure on the low-frequency noise of 0.20 μm UHV/CVD SiGe HBTs is presented. The noise degradation after irradiation shows a strong dependence on transistor geometry. Our previously developed noise theory is used to understand this behavior, and a comparison is made between these new results on third generation SiGe technology and our prior results on the first generation SiGe technology.

Over the past few years, CMOS Silicon-oninsulator (SOI) has emerged as the dominant technology for RF switches in RF front end modules for cell phones and WiFi. RF SOI technologies were created from silicon processes originally used for high speed logic applications, but the technology was modified to meet the performance needs of RF switches. The RF SOI technologies have been improved to follow the evolving system requirements for insertion loss, isolation, voltage tolerance, linearity, integration and cost. In this paper, the performance results of the latest generations of RF SOI switch technologies from IBM are reviewed and technology elements that contribute to improved performance are discussed. Future improvements are also discussed.

This paper presents the first investigation of the physical origins of the observed variable proton tolerance in multiple SiGe HBT BiCMOS technology generations. We use the combination of an extensive set of newly measured proton data on distinct SiGe HBT BiCMOS technology generations, detailed calibrated 2-D MEDICI simulations for both the SiGe HBT and Si CMOS devices, as well as reverse-bias emitter-base and forward-bias electrical stress data to aid the analysis. We find that the scaling-induced increase in the emitter-base electric field under the spacer oxide in the SiGe HBT is primarily responsible for the degraded radiation tolerance with technology scaling, while the decrease in shallow-trench thickness is largely responsible for the improved nFET radiation tolerance with technology scaling.

A new mixed-mode base current degradation mechanism is identified in bipolar transistors for the first time, which, at room temperature, induces a large I/sub B/ leakage current only after simultaneous application of both high J/sub C/ and high V/sub CB/. This new mechanism differs fundamentally from well-known I/sub B/ degradation mechanisms such as the reverse EB voltage stress, high forward current stress and damage due to ionizing radiation. Extensive measurements and two-dimensional (2-D) simulations have been used to help understand the device physics associated with this new degradation mechanism.

We present the first systematic experimental and modeling results of noise corner frequency (f/sub C/) and noise corner frequency to cutoff frequency ratio (f/sub C//f/sub T/) for SiGe heterojunction bipolar transistors (HBTs) in a commercial SiGe RF technology. The f/sub C/ and f/sub C//f/sub T/ ratio are investigated as a function of operating collector current density, SiGe profile, breakdown voltage, and transistor geometry. We demonstrate that both the f/sub C/ and f/sub C//f/sub T/ ratio can be significantly reduced by careful SiGe profile optimization. A comparison of the f/sub C/ and f/sub C//f/sub T/ ratio for high breakdown and standard breakdown voltage devices is made. Geometrical scaling data show that the SiGe HBT with A/sub E/=0.5/spl times/2.5 /spl mu/m/sup 2/ has the lowest f/sub C/ and f/sub C//f/sub T/ ratio compared to other device geometries. An f/sub C/ reduction of nearly 50% can be achieved by choosing this device as the unit cell in RF integrated-circuit design.

This work examines the trade-off between noise figure and gain in SiGe HBT RF technology. Based on the linear noisy two-port theory, analytical expressions for the minimum noise figure, the optimum source admittance, and the associated gain are derived. For many current RF applications of SiGe HBTs operating at frequencies comparable to or smaller than f/sub T///spl radic//spl beta/, /spl beta/ must be increased through SiGe profile optimization to further reduce noise. This noise improvement, however, also results in a degradation of associated gain, as experimentally observed. The implications of the noise-gain trade-off for RF integrated circuit design are discussed.

Product designs for 40-Gb/s applications fabricated from SiGe BiCMOS technologies are now becoming available. In this paper we first briefly discuss heterojunction bipolar transistor (HBT) device operation at high speed, demonstrating that perceived concerns regarding lower BV/sub CEO/ and higher current densities required to operate silicon HBTs at such high speeds do not in actuality limit design or performance. The high-speed portions of the 40-Gb/s system are then addressed individually. We demonstrate the digital capability through a 4: 1 multiplexer and a 1 : 4 demultiplexer running over 50 Gb/s error free at a -3.3-V power supply. We also demonstrate a range of analog elements, including a lumped limiting amplifier which operates with a 35-GHz bandwidth, a transimpedance amplifier with 220-/spl Omega/ gain and 49.1-GHz bandwidth, a 21.5-GHz voltage-controlled oscillator with over -100-dBc/Hz phase noise at 1-MHz offset, and a modulator driver which runs a voltage swing twice the BV/sub CEO/ of the high-speed SiGe HBT. These parts demonstrate substantial results toward product offerings, on each of the critical high-speed elements of the 40-Gb/s system.

A comprehensive investigation of electric field effects associated with the backside Ge profile in SiGe heterojunction bipolar transistors (HBTs) is conducted using calibrated simulations. We show for the first time that the backside Ge retrograde can alter the local electric field distribution in the base–collector space-charge region near the SiGe to Si heterojunction, thereby affecting the impact ionization and the apparent neutral base recombination (NBR) ( I B ( V CB )/ I B ( V CB =0)) of SiGe HBTs. The changes in the electric field induced by the Ge-induced band offsets contributes to a decrease of the observed impact ionization between comparably doped SiGe HBTs and Si bipolar junction transistors (BJTs), as well as an improved V CB dependence of I B (apparent decrease in NBR). Experimental data on SiGe HBTs with various Ge profiles and a Si BJT control are used to support our claims.

We examine the geometrical scaling issues in SiGe HBT technology. Width Scaling, length scaling, and stripe-number scaling are quantified from a radio frequency (RF) design perspective at 2 GHz. We conclude that a SiGe HBT with emitter area A/sub E/=0.5/spl times/20/spl times/6 /spl mu/m/sup 2/ is optimum for low noise applications at J/sub c/=0.1 mA//spl mu/m/sup 2/ and f=2 GHz using the design methodology, which guarantees optimal noise and input impedance matching with the simplest matching network. Finally, the optimal device sizes at f=4 and 6 GHz for low noise applications are also obtained using the same method.

Silicon–germanium (SiGe) heterojunction bipolar transistor (HBT) BICMOS technology is a stable, ultra-high performance, semiconductor technology capable of supporting mixed-signal, very large-scale integration (VLSI) circuit designs for a variety of emerging communication applications. This technology is supported by a computer-aided design (CAD) system that supports a variety of high-performance circuit designs, mixed-signal circuit block reuse, and the ability to accurately predict circuit performance at the highest frequencies. This paper summarizes the progress this technology has made in recent years in moving from the research laboratory to a production environment. We also specifically address performance, operating voltage, reliability and integration considerations for using 100–200 GHz SiGe HBTs in high-speed (10–40 Gb/s) network ICs, an application space previously only addressed by InP technology. All indications are that SiGe will be very successful at addressing this new application space, and all facets of the networking IC market.

Presents the first experimental results of the effects of 63 MeV proton irradiation on SiGe heterojunction bipolar transistor (HBT) analog and radio-frequency (RF) circuits and passive elements. A SiGe HBT bandgap, reference circuit, commonly used to generate stable on-chip voltages in analog ICs, a SiGe HBT voltage-controlled oscillator, a key building block for RF transceivers, and an LC bandpass filter routinely used in RF circuit design were each irradiated to proton fluences as high as 5/spl times/10/sup 13/ p/cm/sup 2/. The degradation associated with these extreme proton fluences was found to be minimal, suggesting that SiGe HBT technology is robust for these types of circuit applications.

The silicon germanium (SiGe) heterojunction bipolar transistor (HBT) marketplace covers a wide range of products and product requirements, particularly when combined with CMOS in a BiCMOS technology. A new base integration approach is presented which decouples the structural and thermal features of the HBT from the CMOS. The trend is to use this approach for future SiGe technologies for easier migration to advanced CMOS technology generations. Lateral and vertical scaling are used to achieve smaller and faster SiGe HBT devices with greatly increased current densities. Improving both the f/sub T/ and f/sub MAX/ will be a significant challenge as the collector and base dopant concentrations are increased. The increasing current densities of the SiGe HBT will put more emphasis on interconnects as a key factor in limiting transistor layout. Capacitors and inductors are two very important passives that must improve with each generation. The trend toward increasing capacitance in polysilicon-insulator-silicon (MOSCAP), polysilicon-insulator-polysilicon (Poly-Poly), and metal-insulator-metal (MIM) capacitors is discussed. The trend in VLSI interconnections toward thinner interlevel dielectrics and metallization layers is counter to the requirements of high Q inductors, potentially requiring a custom last metallization layer.

We present the first experimental results of the effects of 63 MeV proton irradiation on both the lateral and vertical scaling properties of SiGe HBT BiCMOS technology. Three distinct generations of (unhardened) SiGe technology are examined. The first generation SiGe HBTs experience very minor degradation in current gain at proton fluence as high as 2/spl times/10/sup 13/ p/cm/sup 2/. The second and third generations SiGe HBTs, however, show 60-70% degradation in current gain under similar conditions, suggesting that emitter-base spacer optimization may be required as the technology is scaled. Si nFETs from the first generation SiGe BiCMOS technology are only hard to about 40 krad equivalent gamma dose, and are limited by drain-to-source leakage along the shallow trench edge. The second generation Si nFETs, however, improve with scaling since the shallow trench is thinned, and can withstand up to 150 krad of equivalent dose.

This paper investigates SiGe profile design tradeoffs for low-noise RF applications at a given technology generation (i.e., fixed minimum feature size and thermal cycle). An intuitive model relating structural parameters and biases to noise parameters is used to identify the noise limiting factors in a given technology. The noise performance can be improved by pushing more Ge into the base and creating a larger Ge gradient in the base. To maintain the SiGe film stability, the retrograding of the Ge into the collector has to be reduced, leading to a stronger f/sub T/-I/sub C/ roll-off at high injection. Two low-noise profiles were designed and fabricated explicitly for improving minimum noise figure (NF/sub min/) without sacrificing gain, linearity, frequency response, or the stability of the SiGe strained layer. A 0.2 dB NF/sub min/ was achieved at 2.0 GHz with an associated gain (G/sub assoc/) of 13 dB.

A comprehensive investigation of the impact of Ge profile shape as well as the scaling of collector and base doping profiles on high-injection heterojunction barrier effects in SiGe HBTs has been conducted over the -73-85/spl deg/C temperature range. The onset of Kirk effect at high current densities is shown to expose the Si/SiGe heterojunction in the collector-base space charge region, thereby inducing a conduction band barrier which negatively impacts the collector and base currents as well as the dynamic response, leading to a premature roll-off in both /spl beta/ and f/sub T/. In light of this, careful profile optimization is critical for emerging SiGe HBT circuit applications, since they typically operate at high current densities to realize maximum performance. We first explore the experimental consequences and electrical signature of these barrier effects over the 200-358 K temperature range for a variety of Ge profiles from an advanced UHV/CVD SiGe HBT technology. We then use extensive simulations which were calibrated to measured results to explore the sensitivity of these barrier effects to both the Ge profile shape and collector profile design, and hence investigate the optimum profile design points as a function of vertical scaling.

The linear superposition approach to the modeling of small-signal parameters in the presence of substantial base recombination, which involves a virtual transistor without base recombination, is identified to cause incorrect emitter current modeling. All of the terminal current changes can be correctly modeled by using the measured forced-V/sub BE/ Early voltage in a new equivalent circuit, which properly accounts for NBR and Early effect in a physically consistent manner. As a result, practical situations of small collector-base resistance (/spl tau//sub /spl mu//) can be properly handled, /spl tau//sub /spl mu// is related to the ac current-drive and ac voltage-drive Early voltages, which facilitates parameter extraction and circuit modeling. Measurements on state-of-the-art UHV/CVD SiGe HBT's show that the conventional assumption that /spl tau//sub /spl mu// is far larger than the forced-V/sub BE/ output resistance /spl tau//sub 0/ does not apply to devices with significant NBR. In practice, /spl tau//sub /spl mu// can be comparable to (and smaller than) /spl tau//sub 0/ depending on the device processing, profiles and operating temperature. Temperature dependent data are presented, and circuit implications are discussed based on the new equivalent circuit.

This work quantifies neutral base recombination in UHV/CVD SiGe heterojunction bipolar transistors (HBTs) using calibrated two-dimensional (2-D) simulation. The simulated collector-base conductance through neutral base recombination (NBR) modulation is far below the experimentally observed values, and hence does not explain the measured output resistance degradation under forced-I/sub B/ operation. In spite of the output resistance degradation, these UHV/CVD SiGe HBTs have approximately the same base current as the silicon control, and hence higher current gain. Based on the observation of the majority carrier concentration limited recombination in the CB junction depletion layer, as opposed to the minority carrier concentration limited recombination in the neutral base, local presence of traps in the CB junction depletion layer is suggested. This explains the measured CB conductance modulation and the related output resistance degradation without compromising the current gain. Numerical simulations using traps locally introduced into the CB junctions successfully reproduced the measured collector-base conductance from simulation without appreciable degradation in current gain.

The SiGe heterostructure device simulation tool SCORPIO is used to investigate profile optimization in SiGe HBT's for high-performance analog circuit applications. After calibrating SCORPIO to measured data, the effects of germanium profile shape on current gain, cut-off frequency, Early voltage and maximum oscillation frequency are compared over the temperature range of 200-360 K. The impact of aggressive base profile scaling on device performance is also investigated as a function of SiGe film stability.

We present the first comprehensive investigation of neutral base recombination (NBR) in ultra-high vacuum/chemical vapor deposited (UHV/CVD) SiGe heterojunction bipolar transistors (HBT's), and its influence on the temperature characteristics of Early voltage (V/sub A/) and current gain-Early voltage product (/spl beta/V/sub A/). We show that a direct consequence of NBR in SiGe HBT's is the degradation of V/sub A/ when transistors are operated with constant-current input (forced-I/sub B/) as opposed to a constant-voltage input (forced-V/sub BE/). In addition, experimental and theoretical evidence indicates that with cooling, V/sub A/ in SiGe HBT's degrades faster than in Si bipolar junction transistors (BJT's) for forced-I/sub B/ mode of operation. Under the forced-V/sub BE/ mode of operation, however, SiGe HBT's exhibit a thermally-activated behavior for both V/sub A/ and /spl beta/V/sub A/, in agreement with the first-order theory. The differences in V/sub A/ as a function of the input bias and temperature for SiGe HBT's are accurately modeled using a modified version of SPICE. The performance of various practical SiGe HBT circuits as a function of temperature, in the presence of NBR, is analyzed using this calibrated SPICE model.

An inductorless Ka-band silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) ring oscillator is presented. The Ka-band operation is achieved with the addition of a cross-coupled pair to the simple differential inverting amplifier of a single-stage ring oscillator. Implemented with 120-GHz SiGe HBTs, the circuit occupies an extremely compact active area of only 0.0108mm/sup 2/ due to lack of inductors. The frequency is tunable from 28.36 to 31.96GHz, and the single-sideband phase noise is -85.33 dBc/Hz at 1-MHz offset from 31.96GHz. Operating on a -3-V supply, the total power consumption is 87 mW. The resulting oscillator figure-of-merit is -156 dBc/Hz. To our knowledge, this oscillator achieves the best figure-of-merit while occupying the least active area, when compared with other state-of-the-art inductorless ring oscillators operating over a similar frequency range.

A monolithic active isolator combining common-base and common-collector configurations of SiGe heterojunction bipolar transistors (HBT) is used to improve reverse isolation in wireless system applications. This simple active isolator results in an insertion loss of 2 dB and input IP3 of +0.7 dBm over 5-6 GHz with a 1.8-mA current flow for the core circuit of a 3-V supply.

Silicon technologies have continued to usurp other exotic technologies, such as GaAs and Silicon-on-Sapphire (SOS), from the RF wireless communication system to provide a more cost-effective integration path. The integration of RF front-end (RFFE) electronics is a good example of this trend. RFFE components such as, transmit-receive switch, antenna tuners, low-noise amplifiers, and power amplifiers, are being integrated wherever possible. In this paper we discuss the high-resistivity silicon-on-insulator (HR-SOI) technology as a cost effective solution for the RFFE integration in a wireless mobile communication system.

SPMT-ESD interaction and co-design analysis are critical to designing SPMT with high ESD protection. New co-design approach helps to deliver a high linearity SP10T with 8500V ESD protection in SOI CMOS, compared favorable to the state-of-the-art with 0-700V ESD protections [1-3].

This paper reports the first 8kV+ ESD-protected SP10T transmit/receive (T/R) antenna switch for quad-band (0.85/0.9/1.8/1.9-GHz) GSM and multiple W-CDMA smartphones fabricated in an 180-nm SOI CMOS. A novel physics-based switch-ESD co-design methodology is applied to ensure full-chip optimization for a SP10T test chip and its ESD protection circuit simultaneously.

We present for the first time a novel high resistivity bulk SiGe BiCMOS technology that has been optimized for a WiFi RF front-end-IC (FEIC) integration. A nominally 1000 Ohm-cm p-type silicon substrate is utilized to integrate several SiGe HBTs for power amplifiers (PAs), a SiGe HBT low-noise amplifier (LNA), and isolated nFET RF switch device. Process elements include trench isolation for low-loss passives and reduced parasitic coupling, and a lower-resistivity region for the FETs to minimize changes to the circuit library.

In this study, we define and investigate the maximum power handling capability (Pmax) in an SOI RF shunt branch switch. One of the critical factor in the Pmax is the non-uniform voltage division across an OFF shunt branch. In this study we provide a simple analytical method to determine the stack voltage imbalance. The Pmax is characterized as a function of various parameters, such as, switch stack height, channel length, Gate and Body bias, and process parameters. Overall, we find that the Pmax can be improved by reducing stack imbalance as well as device leakage currents, namely, GIDL.

We present a new device design for 20V application in thin body SOI technology. High breakdown voltage is achieved by forming RX-bound field plates which deplete the drift region of an LDMOS structure using only lateral electric field coupling. A baseline 180nm CMOS SOI process is utilized and RX field plate shapes are designed to result in an essentially uniform longitudinal drift region electric field satisfying the RESURF principal. We studied device scaling and the effect of varying the width and length of the angular RX field plates and their relation to impact ionization rate in both floating body and body-contacted n-channel LDMOS deices. 3D TCAD simulations were used to investigate the effect design parameters on electric field and impact ionization. Unitary 20V rated-LDMOS devices are experimentally demonstrated, verifying a LDMOS option to stacked CMOS for high voltage applications in SOI technology.

We analyze the effects that the Ge profile shape has upon the bias and temperature characteristics of SiGe HBT's. The widely used bandgap reference (BGR) design equation and a more general analytical expression we developed incorporating Ge grading are used to compare silicon devices to their SiGe counterparts. Measurement and simulation show that although the Ge-ramp effect is negligible in the -55 to 85 °C range, it can become important as the temperature drops, perhaps affecting the operation of SiGe circuits in the 77 K regime.

A new substrate current-based technique for measuring the avalanche multiplication factor (M - 1) in high-speed SiGe heterojunction bipolar transistors (HBTs) is proposed. The technique enables M - 1 measurement at high operating current densities required for high-speed operation, where conventional techniques fail because of self-heating. Using the proposed technique, M - 1 was measured up to 10 mA//spl mu/m/sup 2/ on SiGe HBTs featuring 120 GHz peak f/sub T/ which occurs at J/sub C/ about 7 mA//spl mu/m/sup 2/. Implications for circuit applications are also discussed.

The 4th generation wireless standard is ushering an era of ubiquitous connectivity. The convergence of data and voice to a portable media device is producing an explosive demand for high data rate communication. Such convergence requirements along with the need for improved battery life, smaller form factor, and reduced cost will demand new ways of system integration. The RF front-end-modules (FEM) that incorporates Power Amplifiers (PAs), Switches, power controller, and passives is one of the segment that is seeing major advancements. Silicon solutions are starting to penetrate into this GaAs stronghold. We discuss the potential for silicon-based technology in providing capability for FEM integration.

This chapter focuses on some of the radiofrequency (RF) and millimetre-wave (MMW) applications that a through-silicon via (TSV) technology can enable. We will first discuss a grounded TSV application for a RF wireless communication power amplifier that is in mass production. A grounded TSV is essentially a metal connection that takes the active device interconnect to a package ground without needing to go through wire bond. A tungsten-filled grounded TSV delivers over 75% reduction in inductance compared to a traditional wire bond, thus enabling higher frequency applications in silicon technology. Such a grounded TSV is seamlessly integrated into a 350-nm SiGe BiCMOS. Next we show feasibility on insulated TSV that is utilised in a digital technology for high speed I/O functions, such as, in an advanced microprocessor. The insulated TSV sits in a 3D-IC carrier silicon chip that is made compatible with standard 90-nm high performance CMOS processing. The TSV arrays are designed to provide minimal resistance and inductance with excellent yield and breakdown voltage characteristics. A commercial application of this concept is for the emerging 100-Gb Ethernet that requires almost 1 Tbps data transmission between ICs. This concept of insulated via in a 3D-IC environment is then extended to a 130-nm MMW SiGe BiCMOS technology. We introduce the concept of a Wilkinson power divider that can be utilised in a 60-GHz phased array radar system.

This paper describes 0.18um CMOS silicon-on-insulator (SOI) technology and design techniques for SOI RF switch designs for wireless applications. The measured results of SP4T (single pole four throw) and SP8T (single pole eight throw) switch reference designs are presented. It has been demonstrated that SOI RF switch performance, in terms of power handling, linearity, insertion loss and isolation, is very competitive with those utilizing GaAs pHEMT and silicon-on-sapphire (SOS) technologies, while maintaining a cost and manufacturing advantage.

The utilization of inverse-mode operation of the SiGe HBT in a single-pole, single-throw RF switch designed for high-linearity and high-power handling applications is investigated for the first time. By swapping the base-emitter junction with base-collector junction for switching, record linearity performance is obtained for SiGe BiCMOS switches at X-band frequencies, while maintaining comparable insertion loss. An IIP3 of 35 dBm and P1dB of 20 dBm is obtained while consuming 29.7 mW of dc power in the ON state. The inverse-mode switch did not show any degradation up to an RF power level of 30 dBm. The reliability mechanisms in SiGe BiCMOS RF switches is understood to be junction damage in the series-diode switching element.

On behalf of the Executive Committee, we would like to welcome you to the 2010 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM). The BCTM 2010 will be held 4th∓6th October, 2010 at the Radisson Hotel & Suites Austin-Town Lake. It includes a one day short course and two days of the conference.

On-chip Wilkinson power dividers are used in MMW circuit designs such as phased array antenna systems. This paper presents a novel on-chip MMW Through-Silicon-Via (TSV) Wilkinson power divider. HFSS simulations of the TSV Wilkinson power divider in a 130 nm BiCMOS technology revealed insertion loss per λ/4 “arm” of 0.9 dB at 60 GHz with both return loss and isolation better than 18 dB at 60 GHz and good matching in both signal phase and amplitude at the two outputs.