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In this paper, a maximum power point tracking (MPPT) system for indoors photovoltaic transducers is presented. The proposed system is used in conjunction with a switching DC-DC boost converter that generates a 1.2 V output for the circuits of the ultra-low-power application. The MPPT tracks different illumination intensities through changing the input impedance of the boost converter. The open circuit voltage of the photovoltaic transducer is compared with a reference voltage and the switching frequency of the boost converter is changed accordingly. The stability of the MPPT feedback system is analyzed for a wide range of illumination intensities. The proposed system has been implemented in a low-cost CMOS 130nm technology. It consumes a quiescent current less than 2.5μA and achieves an average tracking efficiency (TE) of 99%.

A highly linear fully differential CMOS transconductor architecture based on flipped voltage follower (FVF) is proposed. The linearity of the proposed architecture is improved by mobility reduction compensation technique. The simulated total harmonic distortion (THD) of the proposed transconductor with 0.4V"p"p differential input is improved from -42dB to -55dB while operating from 1.0V supply. As an example of the applications of the proposed transconductor, a 4th-order 5MHz Butterworth Gm-C filter is presented. The filter has been designed and simulated in UMC 130nm CMOS process. It achieves THD of -53dB for 0.4V"p"p differential input. It consumes 345@mw from 1.0V single supply. Theoretical and simulated results are in good agreement.

This brief proposes a scalable multichannel clock and data recovery architecture that exploits the synchrony of multiple point-to-point serial links and uses a single voltage-controlled oscillator (VCO) to drive multiple phase detection loops. The proposed architecture can be naturally reduced by design to an ensemble of weakly interacting delay-locked loops. As a result, the jitter peaking problem is asymptotically eliminated, which makes this architecture well suited for use in long-haul repeater chains. Moreover, it allows controlling VCO jitter transfer to the recovered clock without affecting data jitter transfer. The architecture is demonstrated both by a Verilog-A behavioral model along with a rigorous system and statistical analysis.

This paper presents an ultra-low-power boost converter for indoors photovoltaic energy harvesting applications. The boost converter, working in the discontinuous conduction mode (DCM), utilizes an active diode (AD) technique to avoid negative current flowing in the inductor and a control technique that allows supplying dual output voltage levels with sufficient power. The AD is implemented using a level-sensitive clocked comparator that is driven by the system clock while consuming 350nA only. The system clock is chosen as a compromise between required speed of the comparator, switching losses, and size of external inductor. Post-layout simulation results show an overall efficiency of 76.9% for an input power of 160µW while providing two outputs at 1.2V and 3V in 130nm CMOS technology.

This paper presents the design of a 60-GHz millimeter wave (mm-wave) receiver RF front-end (LNA and mixer) and the local oscillator in CMOS65nm and 1.2-V supply. The system-level design and specifications of all blocks are discussed. Two-stage LNA is used to provide a total gain of 11dB with 6-dB NF. The power consumption for the LNA is 10mW and occupies an area of 0.08mm2. Fully differential Gilbert mixer is used with current bleeding technique to increase the gain. The conversion gain is more than 4dB at 10-MHz intermediate frequency. The area of the mixer is 0.0054mm2 and the power dissipation is 5mW. A differential Clapp oscillator is used for the push-push oscillator topology, which is suitable for mm-wave generation. The oscillator is single-ended and an on-chip balun is used to convert the output to differential. The receiver achieves 16-dB conversion gain and consumes 24mW.

This paper presents a muli-input multi-output battery-less energy harvesting system for microscale wireless sensor nodes that combines piezoelectric and photovoltaic energy sources. The system undergoes four states of operation to achieve two voltage levels at the output of 1.2V and 3V. It is a dual path system that uses a single inductor for both boost and buck converter. A maximum power point tracking technique is introduced to lock to the maximum power voltage of the photovoltaic transducer. The system was implemented in UMC CMOS 130nm technology. It achieves an efficiency up to 74% at 10mW of harvested power.

In this work, the design of a 94GHz rotary traveling wave oscillator (RTWO) is presented. The oscillator targets mm-Wave transceivers for biomedical imaging applications. A design procedure to minimize the total power consumption is presented. Using this proposed procedure, a 4 section RTWO is designed in a 65nm CMOS technology. The oscillator consumes 80mA (including buffers) from a 1V supply, and has a phase noise of −106.4dBc/Hz at 10MHz offset with a total core area of 0.36mm2.

In this paper, an approach to map the Bluetooth and 802.11b standards specifications into an architecture and specifications for the building blocks of a dual-mode direct conversion receiver is proposed. The design procedure focuses on optimizing the performance in each operating mode while attaining an efficient dual-standard solution. The impact of the expected receiver nonidealities and the characteristics of each building block are evaluated through bit-error-rate simulations. The proposed receiver design is verified through a fully integrated implementation from low-noise amplifier to analog-to-digital converter using IBM 0.25-/spl mu/m BiCMOS technology. Experimental results from the integrated prototype meet the specifications from both standards and are in good agreement with the target sensitivity.

A single chip quad-band multi-mode (GSM900/ DCS1800/PCS1900/CDMA2K) direct-conversion RF receiver with integrated baseband ADCs is presented. The fully integrated RF receiver is implemented in a 90-nm single poly, six level metal, standard digital CMOS process with no additional analog and RF components. The highly digital multi-mode receiver uses minimum analog filtering and AGC stages, digitizing useful signal, dynamic DC offsets and blockers at the mixer output. The direct-conversion GSM front-end utilizes resistive loaded LNAs with only two coupled inductors per LNA. The GSM front-end achieves a 31.5 dB gain and a 2.1 dB integrated noise figure with a 5 dB noise figure under blocking conditions. The CDMA2K front-end utilizes a self-biased common-gate input amplifier followed by passive mixers, achieving wideband input matching from 900 MHz up to 2.1 GHz with an IIP3 of +8 dBm. The GSM receiver consumes 38 mA from a power supply of 1.5 V and CDMA2K receiver consumes 16 mA in the low band and 21 mA in the high band. The multi-mode receiver, including LO buffers and frequency dividers, ADCs, and reference buffers, occupies 2.5 mm/sup 2/.

A general description of nonlinearities in pseudo differential operational transconductance amplifiers (OTA) with common-mode feedback (CMFB) is introduced. The effects of CMFB nonlinearities on the differential signals are evaluated and design tradeoffs including nonidealities are determined. A practical pseudo differential fully balanced fully symmetric OTA architecture with common-mode feedforward (CMFF) is used as a case study to probe the theory. The OTA has an inherent common-mode detector; hence, the CMFB circuit is efficiently implemented. The OTA is used to implement a 100-MHz fourth-order linear-phase OTA-C filter.

A low-voltage fourth-order RF bandpass filter structure based on emulation of two magnetically coupled resonators is presented. A unique feature of the proposed architecture is using electric coupling to emulate the effect of the coupled inductors, thus providing bandwidth tuning with small passband ripple. Each resonator is built using on-chip spiral inductors and accumulation-mode pMOS capacitors to provide center frequency tuning. The filter has been implemented in HP 0.5-/spl mu/m CMOS process and occupies an area of 0.15 mm/sup 2/. It consumes 16 mA from a single 2.7-V supply at a center frequency of 1.84 GHz and a bandwidth of 80 MHz while providing a passband gain of 9 dB and more than 30 dB of image attenuation for an IF frequency of 100 MHz. The measured output 1-dB compression point and output noise power spectral densities are -16 dBm and -137 dBm/Hz, respectively. This results in a 1-dB compression dynamic range of 42 dB. The filter minimum power supply voltage for proper operation is 2 V. The chip experimental results are in good agreement with theoretical results.

A pseudo-differential fully balanced fully symmetric CMOS operational transconductance amplifier (OTA) architecture with inherent common-mode detection is proposed. Through judicious arrangement, the common-mode feedback circuit can be economically implemented. The OTA achieves a third harmonic distortion of -43 dB for 900 mV/sub pp/ at 30 MHz. The OTA, fabricated in 0.5-/spl mu/m CMOS process, is used to design a 100-MHz fourth-order linear phase filter. The measured filter's group delay ripple is 3% for frequencies up to 100 MHz, and the measured dynamic range is 45 dB for a total harmonic distortion of -46 dB. The filter consumes 42.9 mW per complex pole pair while operating from a /spl plusmn/1.65-V power supply.

This paper presents the design of a novel integrated continuous current sensor (CCS) circuit for class-D audio amplifier and current mode controlled DC-DC converter. The proposed current sensor has the capability of sensing either positive or negative current of off-chip inductor continuously. Additionally, fast transient response with low quiescent current has been achieved. Furthermore, a calibration technique has been developed and attached to current sensor circuit to eliminate performance deterioration due to process, supply, and temperature (PVT) variation. The proposed CCS has been implemented using TSMC 65 nm technology. Simulation results show that the proposed CCS is able to operate with switching frequency up to 1 MHz at only 75 μA quiescent current. The overall accuracy of proposed CCS is greater than 95% over all process corners and temperature variation from -40°C to 125°C, and supply variation from 2.5 V to 2.9 V.

Threshold voltage cancellation (V t cancellation) scheme is applied to cancel the threshold drop associated with the diode-connected device and improve charge pump performance. Applying this scheme depends on generating control signals from the next stage so it cannot be applied on the output stage. In this paper V t cancellation is applied for the output stage of modified Pelliconi pump. This is done by adding an extra circuit that establishes the controlling signals necessary for the auxiliary circuit of the output stage. This modification in the output stage leads to increasing the whole pump power efficiency and voltage gain. Also the pump output equivalent resistance is improved. The proposed charge pump is more suitable for energy harvesting applications due to its ability to give more gain at low voltage levels.

In this paper, an efficient ultra-low-voltage PMU working for TEG input voltages as low as 200mV is proposed. The PMU core, charging an energy buffer, employs a main DC/DC converter. It consists of a cascade of two Dickson-based charge pumps with a variable conversion factor and switching frequency. Feedback is provided from the load buffer by means of a current sensor to a control unit that maximizes the overall power transfer efficiency at low input voltages. System simulation results demonstrate a peak efficiency greater than 70% with a controller current consumption less than 2µA. The PMU core was simulated in Cadence environment using a UMC CMOS 180nm process and the layout of the basic core building blocks is presented. The fully-integreable design consumes an area of approximately 30mm2.

In this paper, the N-phase current driven passive mixer clocked by 1/N duty-cycle clocks is analyzed. The analysis shows that the N-phase passive mixer holds the property of impedance transformation, where it can frequency-translate baseband lowpass impedances into RF frequency to synthesize high-Q bandpass filters. This property can be used to replace the off-chip SAW filter in wireless receivers. For the proof of concept, the system is implemented in 65nm CMOS technology. The simulation results are in a close agreement with the theoretical results.

In this paper, an ultra-low-voltage charge pump is presented. Two techniques are used to reduce required number of stages and improve power efficiency, namely clock boosting and V t cancellation. Clock boosting is employed to increase the output voltage per stage resulting in lower number of stages, and hence smaller output resistance. V t cancellation is achieved by using an auxiliary circuit that enables the charge pump to operate at input voltages as low as 300mV. Compared to conventional charge pump techniques, the proposed technique is shown to offer higher power efficiency and voltage gain. The charge pump is designed using TSMC 0.25µm CMOS technology.

For energy harvesting applications, a power management unit (PMU) architecture operating at low input voltages is required. The most critical sub-blocks of such a PMU are the voltage multiplier and the low-voltage clock generator. An ultra-low-voltage exponential gain charge pump (ECP) that serves as a voltage multiplier for such PMUs is analyzed. A low-cost fully-integrated CMOS implementation for the ECP is proposed. Circuit simulations demonstrate a 0.85-0.90V output for input voltages as low as 150mV and static loads up to 1.5µA. The ECP was simulated in Cadence environment using a TSMC CMOS 65nm process and a total of 5nF MIM capacitors.

This paper presents a CMOS low-voltage bandgap reference circuit with improved power supply rejection (PSR). The analysis of the reference circuit shows the required condition to achieve high PSR. The proposed circuit incorporates a feedback loop to insure that the condition for high PSR is achieved across process variations and temperature drifts. The design has been implemented in 130nm CMOS process. It consumes 70µA from a single 1.2V supply. Simulation results show an improvement of more than 15dB in low frequency PSR due to the additional feedback loop. The theoretical and simulation results are in close agreement.

In this paper an integrated SAW-less narrowband RF front-end for direct conversion wireless receivers is presented. The analysis of the feedback system shows a shift of the center frequency f RX for the overall RF bandpass filter from its nominal value f LO . The proposed architecture incorporates a notch filter at 2f LO to insure that there is no shift in f RX . The design has been implemented in 65nm CMOS process. It consumes 44mA from a single 1.2V supply. Simulation results show a rejection of more than 15dB in a bandwidth of +/−500MHz around 2GHz due to the additional feedback loop. The theoretical and simulation results are in close agreement.

A low-voltage 5th-order continuous-time ΣΔ modulator for a universal mobile TV receiver is presented. A unique feature of the proposed modulator is the blocker filtering provided using a 3rd order notch filter employing frequency dependent negative resistance (FDNR). The noise added by the FDNR is shaped. The modulator employs 3-level switched-capacitor DAC in the feedback. It has been implemented in 6 5nm CMOS process and occupies an area of 0.26mm2. It consumes 6mA from a single 1.2V supply at a sampling frequency of 146MS/s while providing 70dB of dynamic range in 3.85MHz bandwidth.

An integrated digitally-controlled crystal oscillator (DCXO) is presented that generates both 38.4MHz and also a 32.768kHz real time clock (RTC) from a single 38.4MHz crystal. The DCXO can startup independently and transition seamlessly in and out of software control. The tuning range is 280ppm with 2ppb/step and guaranteed monotonicity. The phase noise is −135dBc/Hz at 1kHz offset and −146dBc/Hz at 10kHz offset. The current consumption is 5mA from a 1.4V supply in full power mode and 234µA in low power mode, including the LDO and all clock buffers. The DCXO is implemented in standard 65nm digital CMOS with a die area of 0.09mm2.

The implementation of a complete low-power microphone uplink system is presented. The system comprises a low-dropout regulator (LDO), an input operational transconductance amplifier (OTA), and a 3rd order continuous-time sigma-delta (ΣΔ) modulator. The LDO provides biasing to the microphone and OTA input. The OTA presents high input impedance to the microphone and act as a pre-amplifier. The OTA consumes 100µA from 3.3V supply and ΣΔ modulator consumes 480µA from 1.2V supply at a sampling frequency of 3MHz and achieves dynamic range of 81.5dB. A decimation filter is added after the ΣΔ modulator with decimation factor 64. The design has been implemented in 65nm CMOS process and occupies 0.25mm2.

A quad-band GSM/GPRS/EDGE receiver front-end including I and Q ADCs designed in 90nm digital CMOS technology is presented. The low band receiver designed for GSM850/GSM900 achieves 33dB gain, 1.9dB noise figure, 7.5dB of noise figure under blocking condition and -20dBm of in-band IIP3 with a power of 68mW, while the high band DCS/PCS receiver achieves 32dB gain, 2.2dB noise figure, 9.3dB of noise figure under blocking condition and -20dBm of in-band IIP3 with a power of 72mW. Total active area occupies 3mm/sup 2/.

The design of a dual-mode low-pass channel selection filter for a dual-standard 802.11b/Bluetooth direct conversion receiver is presented. The filter is an OTA-C, 5/sup th/ order, Butterworth low pass structure. The OTA is implemented as a source-degenerated bipolar differential pair. Dual-mode operation, 600 kHz cut-off frequency for Bluetooth mode and 6 MHz for Wi-Fi mode, is achieved by switching the source-degeneration resistors and the capacitors. The filter operates from a single 2.5 V supply while consuming 2.7 mA and 0.9 mA for 802.11b and Bluetooth, respectively. It achieves 10 dBm in-band IIP3, 40 dBm out-of-band IIIP3 for both modes. The measured input referred noise density is -148.92 dBV/Hz and -140.48 dBV/Hz for 802.11b and Bluetooth, respectively.

A fully integrated direct conversion receiver, supporting both Bluetooth and 802.11b standards, is implemented using IBM 0.25 /spl mu/m BiCMOS technology. The RF front-end is shared between both standards while the baseband blocks are programmable for each receiving mode. All the components of the receiver from the LNA to the ADC are integrated using 19 mm/sup 2/ of silicon area. The current consumption of the chip is 41.3 mA/45.6 mA in Bluetooth/802.11b standard and the measured sensitivity is -91 dBm/-86 dBm, respectively.

A dual-mode direct-conversion 802.11b/Bluetooth receiver is integrated from LNA to ADC in a 0.25/spl mu/m BiCMOS process. The baseband circuits are programmable to accommodate both standards while the RF front-end is shared. Die area is 21 mm/sup 2/, and the IC consumes 45.6/41.3mA (802.11b/Bluetooth). Sensitivity is -86/-91dBm and IIP3 is -13/-13dBm.

This paper presents different design considerations of active Q-enhanced LC bandpass filters. An architecture for implementing high order filters is proposed. It uses electric coupling to emulate the effect of the transformer, thus providing bandwidth tuning with small passband ripple.

This paper presents the implementation of an incremental A/D converter for a power supply voltage of /spl plusmn/1 V. The design relies on using floating gate technique in order to reduce the effect of nonlinear settling due to possible saturation of the input stage and to achieve good performance under low voltage operation. The converter has been implemented in 0.5 /spl mu/m CMOS technology with V/sub TN/=0.65 V and V/sub TP/=-0.90 V. The chip prototype occupies an area of 0.2 mm/sup 2/. The converter has been designed for 15 bits of accuracy. Due to the limited accuracy of the measurement equipment, we were able to measure 11 bits of resolution. The converter operates at a clock frequency of 500 kHz and consumes less than 1 mW.

This paper presents a comparative study of three single-stage high frequency linearized OTAs for the design of high-performance continuous-time filters. The advantages and disadvantages of each structure are discussed. The two pseudo-differential OTAs are suitable for very low-voltage applications. One OTA is suitable for very high frequency applications and the other one has a very large linear signal swing and a large transconductance tuning range. The third OTA is based on complementary differential pairs and has very low power consumption. Design examples and experimental results are presented to demonstrate the performance characteristics of each structure.

The implementation of a 3/sup rd/-order 50MS/s CT /spl Delta//spl Sigma/ modulator with 5 levels of quantization, for a CDMA2k receiver, is presented. Its 9nVrms//spl radic/Hz input referred noise produces 80dB of DR in a 600kHz BW for signals as low as 70mVrms. It draws 4mA from a single 1.5V supply, uses a 90nm CMOS process and occupies 0.25mm/sup 2/.

A low-power quadrature direct digital frequency synthesizer (DDFS) is presented. Piecewise linear approximation is used to avoid using a ROM look-up table to store the sine values as in a conventional DDFS. Significant saving in power consumption, due to the elimination of the ROM, renders the design more suitable for portable wireless communication applications. To demonstrate the proposed technique, a quadrature DDFS has been implemented using 0.5-/spl mu/m CMOS process and occupies an active area of 1.4 mm/sup 2/. It consumes 8 mW at 100 MHz and operates from a single 2.7-V supply. The spurious-free dynamic range is better than 59 dBc at low synthesized frequencies and the frequency resolution is 1.5 kHz.