A 2-V 11-bit incremental A/D converter using floating gate technique

This paper presents the implementation of an incremental A/D converter for a power supply voltage of /spl plusmn/1 V. The design relies on using floating gate technique in order to reduce the effect of nonlinear settling due to possible saturation of the input stage and to achieve good performance under low voltage operation. The converter has been implemented in 0.5 /spl mu/m CMOS technology with V/sub TN/=0.65 V and V/sub TP/=-0.90 V. The chip prototype occupies an area of 0.2 mm/sup 2/. The converter has been designed for 15 bits of accuracy. Due to the limited accuracy of the measurement equipment, we were able to measure 11 bits of resolution. The converter operates at a clock frequency of 500 kHz and consumes less than 1 mW.