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Despite their growing adoption in a variety of applications, SiC MOSFETs are generally not available at high current rating. Therefore, there is a high demand for power modules exploiting configurations based on parallel devices. However, these products still need optimization in order to ensure long-term reliability. This paper presents a methodology relying on fast electrothermal simulations aimed at aiding this optimization procedure. The proposed approach is applied to a power module in which the parallel MOSFETs are realistically subject to mismatched parameters.

This paper investigates the effect of negative gate bias voltage (V gs ) on the avalanche breakdown robustness of commercial state-of-the-art silicon carbide (SiC) power MOSFETs. The device's ability to withstand energy dissipation during avalanche regime is a connoting figure of merit for all applications requiring load dumping and/or benefiting from snubber-less converter design. The superior material properties of SiC material means that SiC MOSFETs even at 1200V exhibit significant intrinsic avalanche robustness.

This paper presents an in-depth investigation into the avalanche breakdown robustness of commercial state-of-the-art silicon carbide (SiC) power MOSFETs comprising of functional as well as structural characterization and the corresponding underlying physical mechanisms responsible for device failure. One aspect of robustness for power MOSFETs is determined by its ability to withstand energy during avalanche breakdown. Avalanche energy (EAV) is an important figure of merit for all applications requiring load dumping and/or to benefit from snubber-less converter design. 2D TCAD electro-thermal simulations were performed to get important insight into the failure mechanism of SiC power MOSFETs during avalanche breakdown.

Beyond their main function of high-frequency switches in modulated power converters, solid-state power devices are required in many application domains to also ensure robustness against a number of overload operational conditions. This paper considers the specific case of 1200 V SiC power MOSFETs and analyses their performance under three main transient regimes at the edge of and out of their Safe Operating Area: unclamped inductive switching led avalanche breakdown; short-circuit; operation as current limiting and regulating devices. The results presented highlight both inherent major strengths of SiC over Si and areas for improvement by tailored device design. The paper aims to contribute useful indications for technology development in future device generations to better match widespread and varied application requirements.

The behavior of Silicon Carbide Power MOSFETs under stressful short circuit conditions is investigated in this paper. Illustration of two different short-circuit failure phenomena for Silicon Carbide Power MOSFETs are thoroughly reported. Experimental evidences and TCAD electro-thermal simulations are exploited to describe and discriminate the failure sources. Physical causes are finally investigated and explained by means of properly calibrated numerical investigations, and are reported along with their effects on devices short-circuit capability.

Relatively recently, SiC power MOSFETs have transitioned from being a research exercise to becoming an industrial reality. The potential benefits that can be drawn from this technology in the electrical energy conversion domain have been amply discussed and partly demonstrated. Before their widespread use in the field, the transistors need to be thoroughly investigated and later validated for robustness and longer term stability and reliability. This paper proposes a review of commercial SiC power MOSFETs state-of-the-art characteristics and discusses trends and needs for further technology improvements, as well as device design and engineering advancements to meet the increasing demands of power electronics. 2016 Elsevier Ltd. All rights reserved.

This work aims to present an investigation on short-circuit (SC) failure behaviour of SiC Power MOSFETs due to the onset of thermal runaway. As inferable from experimental outcomes, it is related to the formation of hotspot, whose exact location is mainly unpredictable and dictated by device structure and design parameters non-uniformities. TCAD simulations were performed to examine the impact of some parameters mismatch on hotspot formation and failure occurrence.

Failure mechanisms during short-circuit conditions of Silicon Carbide Power MOSFETs are analysed in this work, and a possible theoretical explanation is provided. Insight into the physics involved in such processes was inferred through experimental and numerical analyses. The TCAD structure used for electro-thermal simulations was calibrated to fit the I D -V GS characteristics of a commercial device. Adequate physical effects were considered, such as the presence of charges and traps at the oxide-SiC interface and their effect on threshold voltage and carrier mobility. Experimental evidences were explained by analyzing the numerical results. The high temperature reached during these operating conditions was addressed as the main cause of the device failure. The effect on the leakage current and the activation of a parasitic bipolar transistor are also shown.

This paper presents an extensive electro-thermal characterisation of latest generation silicon carbide (SiC) Power MOSFETs under unclamped inductive switching (UIS) conditions. Tests are carried out to thoroughly understand the single pulse avalanche ruggedness limits of commercial SiC MOSFETs and assess their aging under repetitive stress conditions. Both a functional and a structural characterisation of the transistors is presented, with the aim of informing future device technology development for robust and reliable power system development.