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This letter presents a two-stage mm-wave power amplifier (PA) in 22nm fully depleted silicon-on-insulator (FD-SOI) technology. High output power is obtained through transistor stacking. Transistor segmentation and back-gate bias control techniques are used in this adaptive PA which can work in high gain mode (HGM) and high linearity mode (HLM). The proposed PA achieves 17.9 dBm saturated output power ($P_{s}at$), 27.6 dB power gain, 11.6 dBm output 1-dB compression point (OP1dB), and 11.0% peak power-added efficiency (PAE) at 74 GHz in the HGM. In the HLM, 17.1 dBm $P_{s}at$ , 21.2 dB power gain, 14.6 dBm OP1dB, and 12.9% peak PAE are obtained at 74 GHz. [ABSTRACT FROM AUTHOR]

This article presents a 55–63-GHz fundamental multicore voltage-controlled oscillator (VCO) in a 28-nm bulk CMOS process. The single-core VCO utilizes stacking and magnetic coupling of two NMOS-based resonators, which increases the tank energy for phase noise reduction while maintaining low voltage swings for reliability. In the multi-core configuration, the oscillators are coupled in a way that also simplifies LO distribution toward the transmitter and receiver. The potential parasitic modes that occur both in single-core and multi-core configurations are suppressed by design. The implicit common-mode (CM) impedance control is utilized to reduce phase noise without any large extra tail inductor as used in a conventional complementary oscillator. The distributed nature of energy restoring elements in the proposed stacked oscillator also offers robust parasitic mode suppression compared to alternative implementation based on a conventional complementary oscillator. The working range of the prototype is between 55 and 63 GHz corresponding to a tuning range of 13.4% with power consumption varying from 15.3 to 12 mW across the tuning range. The prototype achieves the best phase noise of −95 and −121.7 dBc/Hz at 1- and 10-MHz offsets from the carrier at 55GHz. The corresponding peak figure of merits (FOMs) achieved are 178 and 185 dBc/Hz at 1- and 10-MHz offsets from the carrier. [ABSTRACT FROM AUTHOR]

This article presents a 135–155-GHz low-power and high-efficiency frequency multiply-by-9 (x9) frequency-modulated continuous-wave (FMCW) radar transmitter (TX). Starting from a 16-GHz frequency-chirping input signal, cascaded frequency triplers at $V$ -band (40–75 GHz) and $D$ -band (110–170 GHz) bring the signal to the $D$ -band, subsequently amplified and radiated via a power amplifier (PA) and an on-chip antenna at $D$ -band. The $D$ -band PA with a reduced gain of transistors at $f_{\max }$ /2 proposes a broadband gain-boosting technique, achieving a maximum achievable gain ($G_{\max }$) for broad frequency range with high-order embedding passives. The x9 chain proposes phase-controlled frequency triplers that align the phase of each harmonic contribution and boost the third harmonic output power, conversion gain, and dc-to-RF efficiency. Implemented in a 28-nm CMOS process, the TX achieves a measured effective isotropic radiated power (EIRP) of 9.4 dBm, a dc-EIRP efficiency of 16.6% while exhibiting an antenna gain de-embedded output power of 7.1 dBm, and a dc-to-RF efficiency of 9.7% with less than 77-mW dc power consumption. [ABSTRACT FROM AUTHOR]

This article presents novel methodologies and practical design considerations for a $D$ -band transmit/receive (T/R) front-end module (FEM) in 22-nm fully depleted silicon-on-insulator (FD-SOI/FDX) CMOS technology for beyond-5G wireless communication. An ABCD-matrix-based synthesis methodology is proposed to co-design the T/R switch (SW) topology, including the power amplifier (PA) output and the low noise amplifier (LNA) input matching networks, to minimize the losses in both Tx and Rx modes. Based on this synthesis, an asymmetric T/R SW topology is realized with intrinsic electrostatic discharge (ESD) protection. Both the stacked-field-effect transistor (FET) PA and LNA adopt differential topologies with transformer-based matching networks to eliminate unwanted effects from common-mode parasitics. Passive gain-boosting techniques are used for both PA and LNA to enhance different TRx specifications. A reusable unit-cell layout strategy is applied for transistor arrays to accelerate the multiple-stage PA implementation and maintain uniform performance and minimal parasitics. At 140 GHz, the Tx achieves a power gain $G_{p}$ of 33.6/35.7 dB, a saturated output power $P_{\mathrm{ sat}}$ of 12.5/14.7 dBm, a peak power-added efficiency (PAE) of 10.8/11.3%, and an output 1-dB compression point (OP1dB) of 9.4/11.2 dBm with nominal/boosted supplies. An average output power (${P_{out}}_{avg}$)/PAE of 4.9 dBm/2% is obtained for a 4-GHz bandwidth 64-QAM single-carrier signal at an error-vector magnitude (EVM) of −24.8 dB. Moreover, its Tx-mode reliability has been assessed. At 140 GHz, the Rx achieves a 20-dB $G_{p}$ , a −24-dBm input 1-dB compression point (IP1dB), and a 9.2-dB noise figure (NF) with only 20-mW power consumption from a 0.8-V supply. This compact FEM has a PA/LNA core area of 0.024/0.032 mm2, respectively. [ABSTRACT FROM AUTHOR]

Achieving high linearity and bandwidth with good power efficiency makes the design of ADCs in deep nanoscale CMOS processes very challenging, as the constraints of low-voltage operation and limited intrinsic gain often dictate the use of power-consuming analog circuits and intensive digital calibration. This paper addresses these problems by introducing a pipelined ADC that exploits the low but very constant open-loop gain versus output voltage characteristic of the ring amplifier (ringamp) to achieve both high speed and linearity in low-voltage nanoscale CMOS designs. A tunable ringamp biasing scheme using an anti-parallel arrangement of CMOS transistors and an active ringamp-based common-mode feedback are also introduced. A single-channel prototype ADC is implemented in a standard 28-nm CMOS process, achieving 58.7-dB SNDR and 72.4-dB SFDR at 600 MS/s while consuming 14.5 mW from a single 0.9-V supply, resulting in Walden and Schreier figure-of-merit (FoM) values of 34.4 fJ/conv.-step and 161.9 dB, respectively. [ABSTRACT FROM AUTHOR]

This paper proposes the use of a high-power stacked output stage for a current-based in-phase/quadrature (I/Q) direct digital to RF modulator (DDRM) in bulk CMOS. The main nonlinearities associated with implementing the stacked transistor on top of the I/Q DDRM are easily compensated by a simple 2-D digital predistortion. A prototype implemented in 28-nm bulk CMOS achieves a saturated output power (PSAT) of 25 dBm and a peak output power (Pout) of 21 dBm at 1-GHz carrier frequency ( fc). Their corresponding efficiencies are 45% power added efficiency and 33% system efficiency (ηsys), respectively. In addition, it achieves 11.5% ηsys with a -30.5-dB error vector magnitude when transmitting a 40-MHz 64 quadrature amplitude modulation wireless local area network (WLAN) signal. The WLAN signal is transmitted at 12-dBm average Pout, and at 1-GHz fc with 8.73-dB peak to average power ratio (peak Pout of 20.73 dBm). [ABSTRACT FROM AUTHOR]

In this paper, we present an intensive study of 6T-SRAM designs for vertical gate-all-around (GAA) transistors (VFETs) and lateral GAA transistors (LFETs) using 5-nm node design rules. Optimizations of the nanowire (NW) diameter and the gate length are also conducted to enhance the SRAM performance. Device VT retargeting has been proposed for improving the minimum operating voltage ( V\min ) of SRAMs. The isoperformance and isoyield have been performed to assess and determine the benefits provided by LFET and VFET architectures, respectively. Our results show that the VFET bitcells are denser than the LFET bitcells by 20%–30%. The SRAM read stability (read static noise margin) is significantly improved using the NW channel. For a $6\sigma $ yield target and an isoarea of SRAM bitcells, V\min of the VFET bitcell is 80 mV lower than LFET designs. Applying the proposed VT retargeting technique can allow the VFET 122 bitcell to operate at 0.57 V without using assist circuits. A standby leakage below 10 pA/cell can be achieved for both architectures. At isoperformance, the standby leakage of VFET bitcells is $2.6\times $ lower than LFET bitcells. [ABSTRACT FROM AUTHOR]

Substrate noise is a major obstacle for mixed-signal integration. Ground bounce is a major contributor to substrate noise generation due to the resonance caused by the inductance and the Vdd — Vss admittance that consists of the on-chip digital circuit capacitance of the MOS transistors, the decoupling, and the parasitics arising from the interconnect. In this paper, we address: 1) the dependence of the Vdd — Vss admittance on the different states of the circuit, the supply voltage, and the interconnect, and 2) the computation of the total supply current with ground bounce. By using a fast and accurate macromodeling approach, the Vdd — Vss admittances of several test circuits are computed with 2%-3% error relative to the values simulated from the complete SPICE level netlist, but several orders of magnitude faster in CPU time and with 10% maximum error relative to the measurements on a test ASIC fabricated in a 0.18-µm CMOS process on a high-ohmic substrate with 18 &Omega · cm resistivity. The measurements also show that this admittance mainly depends only on the connectivity of the gates to the supply rail rather than their connectivity among each other. [ABSTRACT FROM AUTHOR]

It has been known that using selective epitaxial growth (SEG) silicon, to elevate source/drain regions, is beneficial to digital CMOS by reducing the junction leakage. In addition, this architecture also reduces the gate resistance by enabling a T-shape gate and allowing thicker silicides, which is beneficial for RF-CMOS regarding increased maximum oscillation frequency (f[sub max]) and lowering of the noise figure (NF). In this paper, we report the impact of the SEG-deep source/drain implant (DSDI) process sequence and Co silicide thickness on dc C and RF performance of NMOS transistors. Up to a 28%-45% improvement in f[sub max] is achievable due to a T-shaped gate and thicker Co, made possible by an elevated source/drain ([sup E]S/D) architecture. The maximum transconductance (g[sub m]) of the [sup E]S/D device reaches a value of 1100 mS/mm, which in turn gives a very high f[sub T] of 150 GHz. The low gate sheet resistance obtained with this architecture is also very beneficial for suppressing noise figure in the low-noise amplifier (LNA) circuit demonstrated in this paper. Furthermore, it is shown by simulation that the noise performance of an RF LNA improves due to the SEG and the Co thickness in the T-shaped gate of the NMOS transistor. [ABSTRACT FROM AUTHOR]

This paper presents an in-situ storage topology for ultra-high-speed burst mode imagers, enabling low noise operation while keeping a high frame depth. The proposed pixel architecture contains a 4T pinned photodiode, a correlated double sampling (CDS) amplification stage, and an in-situ memory bank. Focusing on the sampling noise, the system level trade-off of the proposed pixel architecture is discussed, showing its advantages on the noise, power, and scaling capability. Integrated with an AC coupling CDS stage, the amplification is obtained by exploiting the strong capacitance to the voltage relation of a single NMOS transistor. A comprehensive noise model is developed for optimizing the trade-off between the area and noise. As a proof-of-concept, a prototype imager with a 30 µm pixel pitch was fabricated in a CMOS 130 nm technology. A 108-cell memory bank is implemented allowing dense layout and parallel readout. Two types of CDS amplification stages were investigated. Despite the limited memory capacitance of 10 fF/cell, the photon transfer curves of both pixel types were measured over different operation speeds up to 20 Mfps showing a noise performance of 8.4 e−. [ABSTRACT FROM AUTHOR]