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Fully-depleted (FD) tri-gate CMOS transistors with 60 nm physical gate lengths on SOI substrates have been fabricated. These devices consist of a top and two side gates on an insulating layer. The transistors show near-ideal subthreshold gradient and excellent DIBL behavior, and have drive current characteristics greater than any non-planar devices reported so far, for correctly-targeted threshold voltages. The tri-gate devices also demonstrate full depletion at silicon body dimensions approximately 1.5 - 2 times greater than either single gate SOI or non-planar double-gate SOI for similar gate lengths, indicating that these devices are easier to fabricate using the conventional fabrication tools. Comparing tri-gate transistors to conventional bulk CMOS device at the same technology node, these non-planar devices are found to be competitive with similarly-sized bulk CMOS transistors. Furthermore, three-dimensional (3-D) simulations of tri-gate transistors with transistor gate lengths down to 30 nm show that the 30 nm tri-gate device remains fully depleted, with near-ideal subthreshold swing and excellent short channel characteristics, suggesting that the tri-gate transistor could pose a viable alternative to bulk transistors in the near future.

We have combined the benefits of the fully depleted tri-gate transistor architecture with high-k gate dielectrics, metal gate electrodes and strain engineering. High performance NMOS and PMOS trigate transistors are demonstrated with IDSAT=1.4 mA/mum and 1.1 mA/mum respectively (IOFF=100nA/mum, VCC =1.1V and LG=40nm) with excellent short channel effects (SCE)-DIBL and subthreshold swing, DeltaS. The contributions of strain, the lang100rang vs. lang110rang substrate orientations, high-k gate dielectrics, and low channel doping are investigated for a variety of channel dimensions and FIN profiles. We observe no evidence of early parasitic corner transistor turn-on in the current devices which can potentially degrade ION-IOFF and DeltaS

Several key emerging nanoelectronic devices, such as Si nanowire field-effect transistors (FETs), carbon nanotube FETs, and III-V compound semiconductor quantum-well FETs, are assessed for their potential in future high-performance, low-power computation applications. Furthermore, these devices are benchmarked against state-of-the-art Si CMOS technologies. The two fundamental transistor benchmarking metrics utilized in this study are: (i) CVII versus L/sub G/; and ii) CVII versus I/sub ON//I/sub OFF/. While intrinsic device speed is emphasized in the first metric, the tradeoff between device speed and off-state leakage is assessed in the latter. For high-performance and low-power logic applications, low CVII and high I/sub ON//I/sub OFF/ values are both required. Based on the results obtained, the opportunities and challenges for these emerging novel devices in future logic applications are highlighted and discussed.

Sustaining Moore's Law requires continual transistor miniaturization. Through silicon innovations and breakthroughs, CMOS transistor scaling and Moore's Law will continue at least through early next decade. By combining silicon innovations with other nanotechnologies on the same Si platform, it is expected that Moore's Law will extend well into the next decade. This paper describes the most recent advances made in silicon CMOS transistor technology and discusses the challenges and opportunities presented by the recent emerging nanoelectronic devices such as carbon nanotubefield-effect transistors (FET), Si-nanowire FETs and III-V FETs for high-performance, low-power logic applications.

Sustaining Moore's Law of scaling Si CMOS transistors requires not only shrinking the transistor dimensions, but also the introduction of new materials and structures. In the future, advanced high performance CMOS transistors are likely to incorporate highly strained Si and SiGe channels for enhanced carrier transport and high-k/metal-gate stacks for low gate leakage. This work describes the recent advances made in integrating strained Si and SiGe channel transistors with high-k/metal-gate stacks for future high performance, low power logic applications.

In this paper, the performance and energy delay trends for research devices down to 10 nm and also discusses the 10 nm barrier and potential ways to break it were explored.

Tri-Gate fully-depleted CMOS transistors have been fabricated with various body dimensions. These experimental results and 3-D simulations are used to explore the design space for full depletion, as well as layout issues for the Tri-Gate architecture, down to 30 nm gate lengths. It is found not only that the Tri-Gate body dimensions are flexible and relaxed compared to single-gate or double-gate devices, but that the corner plays a fundamental role in determining the device I-V characteristics. The corner device not only turns on at lower voltages due to the proximity of two adjacent gates, but the DIBL of this part of the device is much smaller than the rest of the transistor. The shape of the subthreshold I-V characteristics and the degree of DIBL control, as well as the early device turn-on are also greatly affected by the degree of body corner rounding. Examination of layout issues shows that the fin-doubling approach from using a spacer printing technique results in an increase in drive current of 1.2 times that of a planar device for a given width, though the shape of the allowed Tri-Gate fins has certain restrictions.

This paper reports, for the first time, the high-frequency response of NMOS and PMOS transistors in an integrated CMOS technology with 100 nm physical gate length and alternative gate dielectrics such as ZrO/sub 2/ and HfO/sub 2/ with TiN/PolySi gate electrode. It is shown that the dielectric constants of ZrO/sub 2/, HfO/sub 2/ and SiO/sub 2/ are invariant with respect to operating frequency at least up to 20 GHz. In addition, the cutoff frequency f/sub t/ of the 100 nm CMOS transistor test structures with ZrO/sub 2/ gate dielectric was measured to be equal to 46 GHz for NMOS and 47 GHz for PMOS. The corresponding f/sub t/ values for HfO/sub 2/ were 45 GHz for NMOS and 35 GHz for PMOS. High-K film transistors with 80 nm physical gate lengths, 7 /spl mu/m gate width and layout optimized for high frequency testing were also fabricated. The NMOS devices achieved an f/sub t/ of 83 GHz and an f/sub max/ of 35 GHz, while the PMOS yielded 41 GHz and 25 GHz respectively. These results are very similar to those of CMOS transistors with SiO/sub 2/ gate dielectric at similar physical gate lengths and widths. These results are very encouraging and suggest that high-K gate dielectrics can be used for high-frequency logic applications.

We demonstrate for the first time 85nm gate length enhancement and depletion mode InSb quantum well transistors with unity gain cutoff frequency, fT, of 305 GHz and 256 GHz, respectively, at 0.5V VDS, suitable for high speed, very low power logic applications. The InSb transistors demonstrate 50% higher unity gain cutoff frequency, fT, than silicon NMOS transistors while consuming 10 times less active power