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In this paper, we report a single grain boundary (GB) junctionless thin film transistor (JLFET) on recrystallized polycrystalline silicon (poly-Si JLFET). Using 2-D simulations, the electrical performance of the poly-Si JLFET is evaluated for different single GB locations in the channel. Without the need for creating the source and the drain regions by implantation, we demonstrate the prospect of achieving thin-film poly-Si JLFETs whose performance is reasonable for silicon film thicknesses less than 10 nm.

In this brief, a negative bias stress (NBS) induced degradation in n-type multigate polycrystalline silicon (poly-Si) thin-film transistor (TFT) is investigated. It is observed that after NBS the transfer characteristic curves shift to the negative gate bias direction and multigate TFTs degrade more than the single-gate TFTs with the same effective channel length. The observed degradation phenomenon is explained with short channel effect that is resulted from the diffusion and distribution of hole carriers in the channel, which are generated in the source/drain depletion region and swept into the channel when the junctions are reversely biased during NBS. Pronounced NBS degradation caused by increased hole carriers in the channel is also verified in NBS experiment with light illumination. [ABSTRACT FROM PUBLISHER]

We have succeeded in developing a hybrid-type temperature sensor using poly-Si thin-film transistors (TFTs) that outputs rectangle waveforms. An advantage of the conventional hybrid-type sensor is that large temperature dependences of off-leakage currents can be utilized, and it simultaneously works in a digital operation tolerant of noises. Additionally, in this paper, by connecting two conventional ones, the sensor becomes able to output rectangle waveforms, which can be easily counted. We confirm the waveform and that the sensor can detect the correct temperature. We think that it is promising to integrate this temperature sensor in some applications using TFTs. [ABSTRACT FROM PUBLISHER]

Two-stage degradation of p-type polycrystalline silicon thin-film transistors under dynamic positive bias temperature (PBT) stress is reported for the first time. ON-state current ( \(I_\mathrm{{\scriptstyle ON}}\) ) gradually increases in the first degradation stage while dramatically drops in the second degradation stage, which are, respectively, due to the channel length shortening effect, caused by electrons trapping into the gate oxide, and grain boundary potential barrier buildup, caused by dynamic hot-carrier-induced traps generation. The transition from the first to the second degradation stage is clarified, in which the pulse peak duration plays a key role. Longer pulse peak duration is preferred to suppress the dynamic PBT stress-induced degradation. [ABSTRACT FROM AUTHOR]

A method for fabrication of tri-gate polycrystalline silicon (poly-Si) transistors with short channel length and width is proposed and demonstrated without employing costly lithographic tools. Specifically, the method employs a spacer formation technique to extend source and drain regions so as to scale down the channel length below sub-lithographic dimension. Concurrently, the channel width is scaled down below sub-lithographic dimension by using a photoresist (PR) trimming technique. Our results show that the reduction in the planar channel width is essential for suppressing the short-channel effects. Finally, devices with channel length of 120 nm and planar channel width of 110 nm are demonstrated with superior electrical characteristics in terms of small subthreshold swing (146 mV/dec) and low drain-induced-barrierlowing value (100 mV/V) [ABSTRACT FROM AUTHOR]

We propose a thermal sensor using poly-Si thin-film transistors (TFTs) with self-aligned and offset gate structures. First, the temperature dependences of the transistor characteristic are compared between the self-aligned and offset TFTs. It is found that both the TFTs have the temperature dependence of the off-leakage current, whereas the off-leakage current of the self-aligned TFT is larger than that of the offset TFT. Next, the self-aligned and offset TFTs are included in a cell circuit to detect the temperature utilizing the off-leakage current, which is composed of a pair of 1-transistor and 1-capacitor. It is found that low and high temperatures can be detected using the self-aligned and offset TFTs, respectively. We think that it is promising to integrate this thermal sensor in certain applications using TFTs. [ABSTRACT FROM PUBLISHER]

N-type junctionless (JL) planar poly-Si thin-film transistors (TFTs), which contain an in situ heavily phosphorous-doped channel with thickness ranging from 8 to 12 nm, were fabricated and characterized. The devices exhibit superior current drive and good control over performance variability. From C– V characterization, the ionized dopant concentration in the channel is determined to be around \2 \times \10^19 \ \cm^-3 and the fixed charge density to be around -6 \times \10^12 \ \cm^-2. The negative fixed charge density is probably related to the segregation of phosphorous species at the oxide/channel interface. We also observed a reverse short-channel effect from the relationship between the threshold voltage and the channel length. One mechanism considering enhanced phosphorous segregation is proposed to explain this finding. [ABSTRACT FROM AUTHOR]

Abstract: We propose a thermal sensor employing a ring oscillator composed of poly-Si thin-film transistors (TFTs). First, temperature dependences of transistor characteristics are compared between n-type TFTs with self-aligned and offset gate structures. It is confirmed that the temperature dependence of the offset TFT is larger. Next, a ring oscillator is composed using the n-type offset TFTs. It is clarified that the temperature can be detected by measuring the oscillation frequency. We think that this kind of thermal sensor is available as a digital device. [Copyright &y& Elsevier]

Abstract: We have compared transistor characteristics between excimer-laser crystallized (ELC) and solid-phase crystallized (SPC) poly-Si thin-film transistors (TFTs). First, off characteristic and characteristic parameters, such as the subthreshold swing and field-effect mobility, of the ELC TFT are superior to those of the SPC TFT, which indicates that the trap states in the ELC TFT are fewer than those in the SPC TFT. Next, the activation energy (Ea) for the on characteristic of the ELC TFT is larger than that of the SPC TFT, which originates from the difference of the grain structures. Moreover, Ea for the off characteristic of the ELC TFT is much larger than that of the SPC TFT, which is caused by the difference of the trap distribution. [Copyright &y& Elsevier]

We have analyzed the device behavior of a poly-Si thin-film transistor (TFT) with a lightly doped drain (LDD) structure using 2-D device simulation. It is found that the reason that the on current does not fall very much is that the electron channel oozes from the channel region to the LDD region and the electric current paths spread to the entire LDD region. On the other hand, the reason that the off current is effectively reduced is undoubtedly that the electric field at the interface between the channel and LDD regions is weakened. However, it should be noted that the depletion region is formed at the drain edge owing to the “pseudo” space-charge region in the channel region, where the carrier density is much lower than in the other channel region, although the net space-charge does not exist. [ABSTRACT FROM AUTHOR]

The characteristic degradation of p-type poly-Si thin-film transistors is analyzed using a device simulation. An experiment indicates that the drain current increases under the hot-carrier stress as the stress drain bias increases. The device simulation clarifies that this degradation phenomenon can be reproduced by the electron traps at the insulator interface at least in 1 \mu\m from the drain edge, but the electric field is high only in several hundred nanometers in the conventional trap model. This contradiction is dispelled by considering that the pseudo drain edge advances toward the channel region owing to the electron traps, allowing for a high electric field even far from the drain edge in the pseudo drain edge advance model. [ABSTRACT FROM PUBLISHER]

Abstract: Trap densities (D t) in entire bandgaps of poly-Si thin-film transistors (TFTs) fabricated by solid-phase crystallization (SPC) have been extracted by measuring low-frequency capacitance–voltage characteristics and using an extraction algorithm. The extraction algorithm is explained in detail. D t in the upper and lower halves of the bandgap is extracted from n- and p-type TFTs, respectively. It is found that D t is very roughly 1018 cm−3 eV−1 near the midgap and becomes tail states near the conduction and valence bands. As a result, D t is distributed like U shape in the bandgap, but humps appear around the midgap. Moreover, the dependence of D t on process conditions of post annealing has been evaluated. It is found that the hump can be reduced by increasing annealing temperature and time because crystal defects generated during the SPC are extinguished during the post annealing. [Copyright &y& Elsevier]

Abstract: We propose degradation evaluation of poly-Si TFTs by comparing normal and reverse characteristics. Since symmetrical normal and reverse characteristics indicate Joule-heating degradation whereas asymmetrical characteristics indicate hot-carrier degradation, they can be clearly and easily classified. Moreover, degradation occurrence is contrasted between standard and fine TFTs. Finally, behavior of the hot-carrier degradation is analyzed. [ABSTRACT FROM AUTHOR]

In this paper, we characterize and compare the characteristics of a poly-Si nanowire (NW) device with independent double-gated configuration under different operation modes. In the device, the tiny NW channels are surrounded by an inverted-T-shaped gate and a top gate. It is found that the device under double-gate (DG) mode exhibits significantly better performance with respect to the two single-gate (SG) modes, as indicated by a higher current drive than the combined sum of the two SG modes and a smaller subthreshold swing of less than 100 mV/dec. Origins of such improvement have been identified to be due to the elimination of the back-gate effect as well as an enhancement in the effective mobility with the DG operation. [ABSTRACT FROM AUTHOR]

Positive bias temperature instability in p-channel polycrystalline silicon thin-film transistors is investigated. The stress-induced hump in the subthreshold region is observed and is attributed to the edge transistor along the channel width direction. The electric field at the corner is higher than that at the channel due to thinner gate insulator and larger electric flux density at the corner. The current of edge transistor is independent of the channel width. The electron trapping in the gate insulator via the Fowler-Nordheim tunneling yields the positive voltage shift. As compared to the channel transistor, more trapped electrons at the edge lead to more positive voltage shift and create the hump. The hump is less significant at high temperature due to the thermal excitation of trapped elections via the Frenkel-Poole emission. [ABSTRACT FROM AUTHOR]

The performance of thin-film transistors with a novel poly-Si nanowire channel prepared by solid-phase crystallization is investigated in this paper. As compared with conventional planar devices having self-aligned source/drain, the new devices show an improved ON-current per unit width and better control over the short channel effects. The major conduction mechanism of the OFF-state leakage is identified as the gate-induced drain leakage, and it is closely related to the source/drain implant condition and the unique device structure. [ABSTRACT FROM AUTHOR]

We fabricated poly-Si thin-film transistors at 150 °C using inductively coupled plasma (ICP) chemical vapor deposition (CVD) and excimer laser annealing (ELA). An Si film deposited by ICP-CVD was recrystallized using ELA, and a poly-Si film with large grains exceeding 5000 Å in diameter was fabricated. An SiO2 film with a high breakdown field was deposited by ICP-CVD. A high mobility exceeding 100 cm²/Vs and a low subthreshold swing of 0.76 V/dec were successfully achieved. [ABSTRACT FROM AUTHOR]

Highlights: [•] We propose employing a p/i/n-type poly-Si TFT for quasi-static C–V measurement. [•] The electric current smoothly flows through either the n-type or p-type region. [•] Relatively high f can be used to get a quasi-static C–V characteristic for any voltage conditions. [•] This improves the S/N ratio. [•] The C–V characteristics are available for various analyses such as extraction of trap densities. [Copyright &y& Elsevier]

We have evaluated the effects of thermal annealing before formation of gate insulator films (preannealing) and thermal annealing after formation of gate insulator films (postannealing) by extracting trap densities for solid-phase crystallized poly-Si thin-film transistors. It is suggested that the preannealing densifies the poly-Si films and induces additional internal stress after the thermal oxidation of the gate insulator films. On the other hand, the postannealing also relieves the internal stress. These conflicting effects indicate that the order of the thermal annealing is very important to improve device performance. [ABSTRACT FROM AUTHOR]

In this letter, for the first time, we experimentally investigate the radio-frequency (RF) characteristics and low-frequency noise (LFN) of n-type planar junctionless (JL) poly-Si thin-film transistors (TFTs). The fabricated JL devices show remarkable dc performance with good current drive and a high on-current/off-current ratio of \8 \times \10^7. Furthermore, with the implementation of an in situ phosphorus-doped channel architecture and a salicide process, the JL device with a channel length of 0.4 \mu\m exhibits a cutoff frequency (ft) of 3.36 GHz and a maximum oscillation frequency (f\max) around 7.37 GHz at a drain bias of 2 V. As far as LFN is concerned, the JL device shows approximately four orders of magnitude lower drain-current noise power spectral density (Sid) over conventional inversion-mode counterparts. These results demonstrate that the JL poly-Si TFT technique is promising for RF modules implemented in system-on-panel applications. [ABSTRACT FROM PUBLISHER]

A novel complementary metal-oxide-semiconductor inverter with poly-Si nanowire channels is proposed and demonstrated in this letter. The scheme employs a clever tilted-angle implant process in the fabrication; therefore, the formation of the source and drain of both p-channel and n-channel devices requires only one lithographic step. The fabricated n-channel and p-channel field-effect transistors in the inverters show a high ON/OFF current ratio, an acceptable subthreshold swing, and a symmetric driving current, thus enabling the realization of excellent characteristics of the inverters. [ABSTRACT FROM PUBLISHER]

We have compared the temperature dependences of the current–voltage characteristics between single drain (SD) and lightly doped drain (LDD) poly-Si thin-film transistors (TFTs). It is found that the temperature dependence of the off-leakage current for the LDD TFT is larger because the electric field at the drain junction is weaker. Moreover, the change of the temperature dependence from low drain voltage (V \rm ds) to high Vds for the LDD TFT is smaller because the main mechanism of the off-leakage current is always phonon-assisted tunneling (PAT), whereas that for the SD TFT shifts from PAT to band-to-band tunneling. [ABSTRACT FROM PUBLISHER]

Abstract: We have reproduced columnar grains formed after laser crystallization from amorphous-Si to poly-Si in actual experiments using a crystallization simulator. The crystallization simulator possesses random nucleation, crystal growth velocity, latent heat emission, and partial crystallization models. The columnar grains appear by assuming partial melting condition where thin amorphous-Si remains underneath and that the nucleation rate at the interface between the amorphous-Si and liquid-Si is larger than 5×1018 cm−2 s−1. The nucleation rate corresponds to that the nucleation probability at the interface is more than five times as large as that inside the liquid-Si. [Copyright &y& Elsevier]

In this letter, we study the characteristics of n-type junctionless (JL) poly-Si thin-film transistors (TFTs) with an ultrathin and heavily phosphorous doped channel. The fabricated devices show excellent performance with a subthreshold swing of 240 mV/dec and an on/off current ratio of > \10^7. Moreover, the JL device shows 23 times increase in the on-state current at a gate overdrive of 4 V as compared with the conventional control device with an undoped channel. The significant improvement in the current drive is ascribed to the inherently high carrier concentration contained in the channel of the JL device. These results evidence the great potential of the JL poly-Si TFTs for the manufacturing of future 3-D and flat-panel electronic products. [ABSTRACT FROM PUBLISHER]

We have analyzed the mechanism of off-leakage current in an lightly doped drain (LDD) poly-Si thin-film transistor by investigating the activation energy Ea. It is found that Ea decreases as the gate and drain voltages increase. We have also discussed the mechanism using a device simulator. It is found that a hole channel is lightly formed in the LDD region, and a pseudo p-n junction appears at the junction between the LDD and drain regions. The aforementioned experimental behavior of Ea is because the electric field increases there. These results suggest that the off-leakage current is caused by the phonon-assisted tunneling with Poole–Frenkel effect at the junction between the LDD and drain regions. [ABSTRACT FROM AUTHOR]

We propose a thermal sensor using a poly-Si thin-film transistor (TFT) with widened detectable temperature range. The cell circuit is composed of one transistor and one capacitor. The cell capacitor is charged during initializing periods and discharged during holding periods, and the dropped voltages are measured during detecting periods. The temperature is detected because the discharge current is subject to the temperature dependence of the transistor characteristic. The detectable temperature is expanded to -\10\ ^\circ\C–\140\ ^\circ\C by adding multiple holding periods. We think that it is promising to integrate this thermal sensor in some applications using TFTs. [ABSTRACT FROM PUBLISHER]

We have conducted chronoamperometry using an integrated potentiostat consisting of poly-Si thin-film transistors. An electrochemical measurement of enzymatic redox reaction using glucose oxidase and ferrocene mediator is attempted as a practical example. It is found that the chronoamperogram depends on the glucose concentration, and a glucose concentration as low as 2 mM can be detected by comparing the chronoamperogram without glucose. The glucose sensitivity of the chronoamperometry is similar to that of the cyclic voltammetry and sufficient for diabetic diagnosis. [ABSTRACT FROM AUTHOR]

In this letter, a magnetic-field area sensor using poly-Si micro Hall devices is reported. A matrix array of Hall devices is formed on a glass substrate using fabrication processes compatible with poly-Si thin-film transistors. Here, 3 \times 3 Hall devices are arrayed every 1 \times 1 mm, and the dimension of the principal part is less than \50 \times \50\ \mu\m. A compensation technique of the characteristic variation is used, and it is confirmed that the area sensing is correctly conducted. This sensor presents a novel application using thin-film technologies for giant-micro flexible electronics. [ABSTRACT FROM PUBLISHER]

A capacitorless single-transistor (1T) memory cell with a long data-retention time is demonstrated on polycrystalline silicon thin-film transistors (TFTs). A new operation mode using channel traps is employed to modulate the drain current in the accumulation region. The different drain current can be read by modulating the barrier height at the grain boundary. The extrapolated retention time at the half of the current window is \sim\!\!\10^7\ \s. There is no degradation after 2000 write/erase cycles by trap-assisted tunneling programming. The low-temperature process of the TFT cells is attractive for the 3-D integration. [ABSTRACT FROM PUBLISHER]

This letter studies the electrical degradation of laterally grown polycrystalline silicon thin-film transistors (poly-Si TFTs) under dynamic voltage stress. The experimental results show the serious electrical degradation of poly-Si TFTs with a protruding grain boundary. The concentration of the electric field in the protrusion region was verified by capacitance-voltage measurements and simulation of the device characteristics. These results reveal that more electrons are induced at the grain boundary of the poly-Si channel because of the relatively high electric field in the protrusion region. Based on these data, this letter proposes a model to explain the enhanced electrical degradation of poly-Si TFTs with a protruding grain boundary, generated by laser-crystallized lateral growth technique. [ABSTRACT FROM AUTHOR]

A novel thin-film transistor test structure is proposed for monitoring the device hot-carrier (HC) degradations. The new test structure consists of several source/drain electrode pairs arranged in the direction perpendicular to the normal (i.e., lateral) channel of the test transistor. This unique feature allows, for the first time, the study of spatial resolution of HC degradations along the channel of the test transistor after stressing. The extent of degradation as well as the major degradation mechanisms along the channel of the test transistor can be clearly identified. [ABSTRACT FROM AUTHOR]