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In this study, a novel structural design of the p‐type low‐temperature polycrystalline silicon thin‐film transistors (p‐type LTPS TFTs) applied to the pixel structure of displays is proposed. Compared to the conventional pixel structure of displays, the proposed architecture can achieve the aperture ratio improvement by stacking the switch thin‐film transistor and the storage capacitor in a pixel region to enlarge the active space. Therefore, the demands of high‐resolution characteristics, such as a high aperture ratio, and high pixel densities for high‐end displays or novel technologies, can be satisfied by the adoption of the proposed design concept. Furthermore, the discussion of experimental and simulated results in terms of device physics of the transistor indicates that proposed TFTs possess higher performance and reliability properties. By modulating the geometry of the drain‐connected bottom metal in stacked TFTs, output characteristics and hot carrier phenomenon in devices can be further improved. Time‐dependent transfer characteristics, extracted electrical parameters, and numerical simulation results are performed to support our design. [ABSTRACT FROM AUTHOR]

In this study, the negative bias temperature instability (NBTI) under mechanical strain conditions of low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs) with a stress-release structure was investigated. With both electrical and mechanical stresses simultaneously applied, more significant degradation behaviors will be observed in standard TFT devices because mechanical stress makes it easier to generate strain in Si–H bonds, thus benefiting the process of electrochemical reaction. By employing a stress-release shape in the poly channel, mechanical stress, which mainly accumulates at the width edge of the poly-Si/SiO2 interface, is moved away from the main channel; thus, fewer strained Si–H bonds can participate in the electrochemical reaction compared to the standard structure. Therefore, the degradation of devices under strained NBTI is effectively mitigated, such that the reliability of the devices is enhanced. These observations were obtained using electrical characteristics and extraction of the trap state distribution. [ABSTRACT FROM AUTHOR]

In this work, the impact of positive bias stress (PBS) on an all copper(Cu)-electrode a-InGaZnO TFT is discussed. Commonly, Cu diffusion from the source/drain electrode after negative bias stress (NBS) leads to degradations in the on-state current and subthreshold swing. However, this study finds that diffusion in the gate insulator layer from the gate electrode suffers from more serious degradation. Eventually, this phenomenon causes a serious breakdown of the gate insulator such that it loses the transistor function. Results indicate that after 2000s of PBS, accumulation of Cu ions forms a filament which dominates the leakage path. During the stress duration, the gate leakage current is monitored and current fittings are adopted to confirm the phenomena. Furthermore, temperature dependencies have verified the results of hopping and Ohmic conduction at different stages of deterioration. Compared to previous literature that focus on the impacts of source/drain electrodes, this work suggests that gate engineering for thin film transistors is more urgent for high-quality display applications. [ABSTRACT FROM AUTHOR]

In this letter, a study of physical mechanisms is introduced to describe an abnormal phenomenon in transfer characteristics while p-type low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs) were subjected to a negative bias temperature stress (NBTS) in an illuminated environment. In general, under NBTS, the transfer characteristics exhibits a negative shift of threshold voltage and a degradation of subthreshold swing. Here, however, experimental results reveal that the degree of degradation is different after NBTS is applied to poly-silicon TFTs in a darkened and in an ultraviolet condition. This variation is mainly a result of the light-generated electrons recombining with the inversed holes, and leading to a lower degree of degradation. Moreover, we found that the influence of the UV light is an edge effect at different channel lengths. This letter investigates the illumination effect in LTPS TFTs during NBTS, and the phenomenon is clarified by electrical measurements and by trap state extraction. [ABSTRACT FROM AUTHOR]

This work studies the effect of the location of the light shielding (LS) layer on negative bias illumination stress (NBIS) instability in self-aligned top-gate amorphous indium-gallium-zinc oxide thin-film transistors (SA-TG a-InGaZnO TFTs). Although the NBIS instability can be mitigated by introducing a fully covered LS layer, it causes an unwanted parasitic capacitance, as evidenced by capacitance–voltage (C – V) measurements. An alternative solution, in which the device that is partially covered by the LS layer at the source side, is proposed to optimize the tradeoff. This study suggests that an LS layer could be adopted in the SA-TG configuration, as it is versatile in different structural designs, depending on the requirement of targeted applications. [ABSTRACT FROM AUTHOR]

This study demonstrated that the edge effect induced by positive gate bias stress (PBS) was effectively eliminated by applying channel width extensions over source/drain regions in low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs). After PBS, a stress-induced hump current in subthreshold region is observed and is caused by the charge trapping into parasitic transistors along the channel width edges. This phenomenon is attributed to carrier injection occurring along the width edges since a high electric field is located at that region, where lots of defects are generated due to the definition of the active area during the etching process. In this study, we show that the degradation in electrical characteristics during the gate bias operation resulted from the edge effect can be eliminated when the TFT devices utilize the channel width extension in the active layer. Electrical measurements, numeral calculations, and a TCAD electrical simulation confirm that this geometry, which includes a channel extension along the width direction, can dramatically reduce the carrier injection at the edges even though high electric field is mainly located at the width edges during gate bias operation. [ABSTRACT FROM AUTHOR]

Optoelectronic memory whose digital signals depend on electrical as well as optical sources have attracted tremendous attention recently due to their potential in applications, including optical communication systems, neural networks, and image correlation systems. In this work, metal‐oxide semiconductors for use as optical memory devices are accomplished through a heterojunction channel layer which acts as a quantum confinement architecture confining electrons to the front channel. Compared to conventional memories, which rely on electron injections that cause hot electron degradation, the proposed device is based on a floating body effect. After irradiation, photo‐excited carriers are separated under a lateral electrical field, and generated holes are left in the back channel, which facilitates data storage behavior. Beneficial characteristics include a memory window (≈4.6 V), a high on/off ratio (≈106), and low operating voltage (<20 V). Furthermore, photo‐excited carriers are only generated when irradiated by ultraviolet light, leading to a visible‐blind optical memory. A retention of more than 10 years and endurance cycle of more than 1000 cycles demonstrate its nonvolatile behaviors. This work provides a novel heterojunction channel layer architecture in disordered oxide semiconductors and provides a novel idea for a wide range of unipolar materials in future optoelectronic memory devices. [ABSTRACT FROM AUTHOR]

In this article, an n-type double-gate low-temperature polysilicon (LTPS) TFT is investigated. Previous work has confirmed that the hot-carrier effect will cause impact ionization. Here we observed that, after hot-carrier stress (HCS), the transfer curve in the saturation region has a negative $\text{V}_{\mathrm {th}}$ shift, and a hump is also observed. The reverse output characteristic shows that gate induced drain leakage (GIDL) of the transistor gradually increases and the subthreshold swing (S.S.) has a tendency to collapse. In structures with longer lightly doped drain (LDD) lengths, the electric field at both source/drain side can be effectively dispersed. Thereby, an extended LDD can reduce the overall degradation, and a physical model of explanation is proposed. By using the energy band diagram, we clarify how the additional electron hole pairs affect the output property. Next, Silvaco TCAD simulation is utilized to illustrate the electric field distribution and validate the physical model. [ABSTRACT FROM AUTHOR]

The effects of radiation on tungsten doped indium oxide (IWO) thin-film transistors (TFTs) have been well investigated in this Letter. In order to achieve high stability and excellent electrical performance simultaneously even in high ionizing radiation damage ambient, different concentrations of tungsten dopant have been introduced for the TFT device fabrication. It is interesting that the high energy ionizing radiation may significantly increase the conductivity and influence the total concentration of oxygen vacancy in the transparent amorphous oxide semiconductor material, which may be completely different from the traditional radiation damage effect for silicon based CMOS devices. However, that abnormal phenomenon will be effectively suppressed by the powerful carrier suppressor, tungsten, which may have a high oxygen bond dissociation energy. Therefore, IWO devices with a 4% tungsten oxide dopant might be the optimized result even after high dosage ionizing radiation exposure. Hence, it may provide a promising radiation hardness approach to improve both the electrical characteristics and reliability for next generation displays, which can be used in the control system of nuclear power generation or space technology. [ABSTRACT FROM AUTHOR]

In this study, a novel structural device, named as a wing-shaped TFT, is proposed and is demonstrated to prevent fast deterioration under mechanical bending in foldable devices. After long-term mechanical bending, standard low-temperature polysilicon TFTs exhibit instability behaviors such as sub-channel formation, serious threshold voltage shifts, an on-current (ION) increase, and an off-current (IOFF) decrease. These phenomena are believed to be due to additional oxide traps along the channel-width edges of the gate insulator after bending. In order to suppress this degradation, a wing-shaped structure is proposed. By extending the active layer, degradation regions are shifted away from the main channel. Therefore, the reliability of the devices is enhanced. The transfer characteristics show enhanced electrical behavior after being held for 48 hours in a static bent condition, with an 88% drop in threshold voltage shift as well as a 55% decrease in subthreshold swing degradation, proving better durability of the foldable TFT to bending stress for devices with these wings. Time-dependent transfer characteristics, a COMSOL simulation, and device geometry are discussed to support our findings. [ABSTRACT FROM AUTHOR]

In this study, the role of nitrogen in the dc-sputtered amorphous indium gallium zinc oxide (a-IGZO):N are explored extensively with a series of nitrogen gas flow rates during IGZO film deposition. The amorphous film structure and the evolution of chemical bondings were confirmed by X-ray diffractometer and X-ray photoelectron spectroscopy spectra analysis. Also, electrical performance and reliability of a-IGZO:N thin-film transistors (TFTs) formed with different nitrogen gas flow rates were analyzed to study the effects of nitrogen on TFT devices. The device performance of a-IGZO:N TFTs can be enhanced with a proper nitrogen doping concentration. However, with excess nitrogen incorporation in the a-IGZO:N channel layer, both electric characteristic and reliability are degraded due to the extra creation of oxygen deficiencies in a-IGZO:N film and easy formation of unstable interface between gate insulator and channel layer, which were confirmed by low-frequency noise measurement. This potential issue of a-IGZO:N TFT characteristics can be effectively released by introducing a post-treatment on the surface of gate dielectric layer. The optimized electrical characteristics of a-IGZO:N TFT can exhibit a carrier mobility of 19.21 cm2/V⋅s, subthreshold swing of 0. 26 V/decade and threshold voltage $({{V_{{\rm th}}}})$ of −0.74 V in this study. [ABSTRACT FROM PUBLISHER]

In this study, indium-gallium-zinc-oxide thin film transistors can be operated either as transistors or resistance random access memory devices. Before the forming process, current-voltage curve transfer characteristics are observed, and resistance switching characteristics are measured after a forming process. These resistance switching characteristics exhibit two behaviors, and are dominated by different mechanisms. The mode 1 resistance switching behavior is due to oxygen vacancies, while mode 2 is dominated by the formation of an oxygen-rich layer. Furthermore, an easy approach is proposed to reduce power consumption when using these resistance random access memory devices with the amorphous indium-gallium-zinc-oxide thin film transistor. [ABSTRACT FROM AUTHOR]

Abstract: We examined the characteristics of passivation-free amorphous In–Ga–Zn–O thin film transistor (a-IGZO TFT) devices under different thermal annealing atmospheres. With annealing at higher temperature, the device performed better at the above-threshold operation region, which indicated the film quality was improved with the decrease of defects in the a-IGZO active region. The mobility, threshold voltage and subthreshold swing of a-IGZO TFT annealed at 450°C was 7.53cm2/Vs, 0.71V and 0.18V/decade, respectively. It was also observed that the a-IGZO was conductive after thermal annealing in the vacuum, due to the ease of oxygen out-diffusion from the a-IGZO back channel. The oxygen deficiency resultantly appeared, and provided leaky paths causing electrical unreliability when TFT was turned off. In contrast, the annealing atmosphere full of O2 or N2 would suppress the oxygen diffusion out of the a-IGZO back channel. The worst Vth degradation of a-IGZO TFT after positive gate bias stress and negative gate bias stress (NGBS) was about 2V and −2V, respectively. However, the Vth shift in the NGBS testing could be suppressed to −0.5V in vacuum chamber. Material analysis methods including X-ray photoelectron spectroscopy and scanning electron microscopy were used to investigate the change of a-IGZO film after different thermal annealing treatments. The variation of O 1s spectra with different annealing atmospheres showed the consistence with our proposed models. [Copyright &y& Elsevier]

This letter studies the correlation of postannealing treatment on the electrical performance of amorphous In-Zn-Sn-O thin-film transistor (a-IZTO TFT). The 400 °C annealed a-IZTO TFT exhibits a superior performance with field-effect mobility of 39.6 cm \(^{{\mathbf {2}}}\) /Vs, threshold voltage (V \(_{\rm th}\) ) of −2.8 V, and subthreshold swing of 0.25 V/decade. Owing to the structural relaxation by 400 °C annealing, both trap states of a-IZTO film and the interface trap states at the a-IZTO/SiO2 interface decrease to \(2.16\!\times \! 10^{{\mathbf {17}}}\) cm \(^{\mathbf {-3}}\) eV \(^{{\mathbf {-1}}}\) and \(4.38\times 10^{\mathbf {12}}\) cm \(^{\mathbf {-2}}\) eV \(^{\mathbf {-1}}\) , respectively. The positive bias stability of 400 °C annealed a-IZTO TFTs is also effectively improved with a V \(_{\rm th}\) shift of 0.92 V. [ABSTRACT FROM AUTHOR]

In this letter, microwave annealing technology is proposed to reduce thermal budget for the manufacture of transparent conductive oxide thin-film transistor (TFT). With microwave annealing, a nitrogenated amorphous In-Ga-Zn-O (a-IGZO:N) TFT fabricated on glass panel behaves as a carrier mobility of 4.21 cm^2/V~s and threshold voltage of 2.91 V. The performance of microwave-treated a-IGZO:N TFT with annealing process duration of 300 s is well competitive with its counterpart treated by thermal furnace annealing at 350 C for 1 h. Owing to its low thermal budget and selective heating to materials of interest, the microwave annealing has great potential for flexible oxide TFT applications. [ABSTRACT FROM PUBLISHER]

In this study, indium gallium zinc oxide (InGaZnO [IGZO]) active layer capped with an ultrathin p‐type stannous oxide (SnO) is demonstrated to be a thin film transistor (TFT) for color scanning and photosensing device applications. Typically, the sole IGZO‐based TFT is blind to visible light and hard to be developed for visible light sensing. The combination of IGZO and SnO layers can extend the light detection spectrum into visible light wavelengths and ameliorate the photosensing characteristics. The optical responsivity and signal to noise ratio can even be enhanced from 1.05 × 10−2 to 398.02 A W−1 and from 2.1 × 101 to 6.8 × 105 with at least four orders of magnitude, respectively. With the detailed material analysis and physical model discussed, it suggests that the large amount of additional light‐excited carrier generated in the capping layer is the key factor for the significant improvement. Furthermore, the phenomenon of persistent photoconductivity can be effectively suppressed by its natural recombination under the heterojunction structure without applying charge‐pumping method. The electrical uniformity of the sensor device is also highly potential for the next‐generation displays integrating the photosensing functions. An ultrathin p‐type stannous oxide with suitable bandgap, high stability, good process compatibility, and uniformity is proposed to be the light‐absorbing layer, that improves the optical responsivity and signal to noise ratio of an amorphous indium gallium zinc oxide based sensor thin film transistor by at least four orders of magnitude. Besides, the persistent photoconductivity effect can also be suppressed by its heterojunction structure. [ABSTRACT FROM AUTHOR]

In this study, a Pt/BiFeO3/TiN device was fabricated and the resistance switching characteristics were investigated. After the first forming process, the conduction path was formed and exhibited unstable bipolar switching characteristics. Subsequently, the original conduction path was destroyed thoroughly by high negative bias. By reconstructing the conduction path after a second forming process (re-forming process), the device exhibits stable bipolar switching characteristics. Transmission electron microscopy analysis indicates that the stability of switching behavior was enhanced because of the joule heating effect, and is an easy way to improve the resistance switching characteristics. [ABSTRACT FROM AUTHOR]

Abstract In order to effectively enhance the carrier mobility and device stability, simultaneously, a multi-stacked active layer of thin film transistor with a novel type of channel material, amorphous indium-tungsten-oxide, is proposed in this work. Atop-cappingoxygen-rich indium-tungsten-zinc-oxide thin film is used for suppressing the influence of the molecular adsorption or desorption from the ambient at the back channel in the gate bias stress test. In addition, a bottom-bufferingoxygen-rich indium-tungsten-zinc-oxide thin film is deposited to avoid the oxygen vacancy generation during the following thermal process. On the other hand, a 1-nm thick WO 3 film is inserted between the high-k gate insulator and active layer, which play important roles as interfacial layer for improving the interface quality and keeping the stability of front channel film. Besides, an HfO 2 dielectric film is chosen as gate insulator for realizing the low-voltage operation. As a result, the novel tungsten doped channel material with both-sideoxygen-rich active layer exhibits a high I ON /I OFF current ratio of ~6 × 107 for low gate leakage current, attributing to the top-cappingoxygen-rich thin film. Then, a high field-effect mobility of ~27.9 cm2/V.s and a low sub-threshold swing of 0.079 V/decade are achieved by the good interface quality. This structure with both-sideoxygen-rich active layer exhibits its potential application for the future high-resolution and large-size display manufacture. Highlights • The TFT devices with a novel multi-stacked tungsten doped channel material structure are discussed in this report. • The TFT devices with both-side oxygen-rich active layer exhibit an obvious enhancement on the electrical performance. • The reliability characteristics of TFT device can also be improved by this both-side oxygen-rich active layer structure. [ABSTRACT FROM AUTHOR]

Abstract The electrical characteristics and XPS analysis for the amorphous tungsten and zinc doped indium oxide thin film transistor, which was performed with single or double different fluorine based remote plasma treatment, were investigated in this study. A high mobility TFT device with the tungsten doped channel was fabricated in the previous study, but there was an inevitable negative shift for the threshold voltage, which will be a limit for the application of systemic circuit design. Therefore, a double fluorine based remote plasma treatment process is proposed for the high electronegativity of fluorine element and its similar radius as oxygen, which can be used to terminate the donor-like oxygen vacancy. It may induce a positive shift of threshold voltage, while carrier concentration and field effect mobility might be maintained. As a result, the sample with CF 4 /N 2 + O 2 plasma treatment exhibits a higher on/off current ratio of ~4.73 × 106, a lower sub-threshold swing value of 0.070 V/decade, and a lower interfacial trap density value of 5.21 × 1011 eV−1 cm−2 than other samples, while there is even a desirable positive shift of threshold voltage and acceptable field effect mobility of 31.2 cm2/Vs. This research proposes an effective approach to improve the reliability characteristic and adjust the inevitable negative shift of threshold voltage without sacrificing the carrier mobility of device. Highlights • The devices with tungsten doped channel and a fluorine based double remote plasma treatment process are discussed. • The devices with CF 4 /N 2 +O 2 plasma treatment exhibit an enhancement on the electrical characteristics and reliability. • The mechanism of fluorination and the interaction between different plasma have been investigated by XPS analysis. [ABSTRACT FROM AUTHOR]

The amorphous indium gallium zinc oxide thin-film transistors (TFTs) with a multilayer high-k gate stack are investigated in this research. In order to achieve a high quality gate insulator for plastic flexible display application, the multilayer high-k gate stacks (SiO 2 /TiO 2 /HfO 2 ) are deposited by a low-temperature physical vapor deposition (PVD) process. On the other hands, an interfacial layer between the high-k stack and metal oxide channel is important for the device performance. The effects of interfacial layer material (SiO 2 or Ga 2 O 3 ) are also discussed in this report. The devices with SiO 2 interfacial layer show a high on/off current ratio of ~7 × 10 7 for its low gate leakage current, a small sub-threshold swing of 0.093 V/decade and a high field-effect mobility of ∼37.8 cm 2 /Vs for its good interface condition and low interface defeats. This research shows that the interface engineering of multilayer PVD gate stacks is necessary for oxide TFT fabrication. [ABSTRACT FROM AUTHOR]

Amorphous Indium-Zinc-Tin-Oxide thin-film transistors (a-IZTO TFT) using different types of high-k materials (like HfO 2 , ZrO 2 and Al 2 O 3 ) as gate dielectric are studied in this work. All gate dielectric films were deposited by physical vapor deposition (PVD) process for better composition control. Compared with the traditional SiO 2 gate insulator, a high-k gate dielectric can reduce the operation voltage of TFT device significantly. The TFT device with ZrO 2 gate insulator exhibits a small subthreshold swing of 0.126 V/decade, high field-effect mobility of ~40.7 cm 2 /Vs, low threshold voltage of −0.05 V, and large On/Off current ratio of ~1.01 × 10 7 . The mechanisms for electrical improvements are also investigated. These results demonstrate the potential application of PVD-deposited ZrO 2 thin film as a promising gate dielectric in oxide-based thin-film transistors. [ABSTRACT FROM AUTHOR]