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This paper analyzes the effect of high current under illumination stress (HCIS) in self-aligned amorphous indium gallium zinc oxide transistors with Al2O3 as high- $\kappa $ gate dielectric. A negative parallel threshold voltage $({V}_{T}$) shift with the appearance of hysteresis $(\Delta {V}_{{hys}})$ is observed after HCIS. In contrast to the double ionized oxygen vacancy ($\text{V}_{\text O}^{\text 2+}$) theory, a peroxide donor theory based on ${ab~ initio}$ calculations is proposed to explain the degradation. Several methods are carried out to support the mechanism, including $\Delta {V}_{{hys}}$ generation, stress recovery behavior and capacitance-voltage ${(C-V)}$ measurements. A linear dependence between initial ${V}_{T}$ and negative ${V}_{T}$ shift is observed that further supports the peroxide theory. This work highlights the importance of evaluating the HCIS for oxide base semiconductor devices. [ABSTRACT FROM AUTHOR]

In this paper, the influence of oxygen partial pressure (${P}_{\textsf {O2}}$) during physical vapor deposition on the field-effect mobility of amorphous InGaZnO (IGZO) thin-film transistor (TFT) is investigated in a wide range of ${P}_{\textsf {O2}}$. The field-effect mobility reduced from 12 to 0.1 cm $^{\textsf {2}}/\textsf {V}~\cdot $ s when the ${P}_{\textsf {O2}}$ is increased from 0.3 to 1.5 mTorr. Temperature-dependent TFT measurements suggest that carrier transport in the TFTs deposited at the ${P}_{\textsf {O2}}$ of 0.3 mTorr can be described according to the multiple trap and release/percolation model. However, the carrier transport in the TFTs deposited at the ${P}_{\textsf {O2}}$ of 1.5 mTorr conforms to Mott’s variable-range hopping model. The elastic recoil detection analysis indicates that hydrogen concentration in the IGZO film increased with ${P}_{\textsf {O2}}$. The X-ray photoelectron spectroscopy results indicate that In vacancy (${V}_{\textsf {In}}$) defects formed in the IGZO film deposited at high ${P}_{\textsf {O2}}$. Scattering induced by hydrogen and pinning of Fermi level below the conduction band edge by ${V}_{\textsf {In}}$ are plausible reasons for the low field-effect mobility in TFTs deposited at high ${P}_{\textsf {O2}}$. [ABSTRACT FROM AUTHOR]

In this work, we have reported dual-gate amorphous indium gallium zinc oxide thin-film transistors (a-IGZO TFTs), where a top-gate self-aligned TFTs has a secondary bottom gate and the TFT integration comprises only five mask steps. The electrical characteristics of a-IGZO TFTs under different gate control are compared. With the enhanced control of the channel with two gates connected together, parameters such as on current (ION), sub-threshold slope (SS−1), output resistance, and bias-stress instabilities are improved in comparison with single-gate control self-aligned a-IGZO TFTs. We have also investigated the applicability of the dual-gate a-IGZO TFTs in logic circuitry such as 19-stage ring oscillators. [ABSTRACT FROM AUTHOR]

We present a qHD (960x540 with 3 sub-pixels) top-emitting AMOLED display with 340ppi resolution using a self-aligned (SA) IGZO TFT backplane on polyimide-foil with humidity barrier. The back plane process flow is based on a 7 layer photolithography process with a CD=4um. We implement a 2T1C pixel engine and use commercial source driver IC made for LTPS. By using IGZO TFT and leveraging the extremely low off-current, we can switch-off the power to the source and gate driver while maintaining the image un-changed for several minutes. We demonstrate that, depending on the image content, low-refresh operation yields reduction in power consumption of up to 50% compared to normal (continuous) operation. We show that with further increase in resolution, the power saving through state retention will be even more significant. [ABSTRACT FROM AUTHOR]

We present a qHD (960 × 540 with three sub-pixels) top-emitting active-matrix organic light-emitting diode display with a 340-ppi resolution using a self-aligned IGZO thin-film transistor backplane on polyimide foil with a humidity barrier. The back plane process flow is based on a seven-layer photolithography process with a CD = 4 μm. We implement a 2T1C pixel engine and use a commercial source driver IC made for low-temperature polycrystalline silicon. By using an IGZO thin-film transistor and leveraging the extremely low off current, we can switch off the power to the source and gate driver while maintaining the image unchanged for several minutes. We demonstrate that, depending on the image content, low-refresh operation yields reduction in power consumption of up to 50% compared with normal (continuous) operation. We show that with the further increase in resolution, the power saving through state retention will be even more significant. [ABSTRACT FROM AUTHOR]

In this study, we have compared the performance of self-aligned a-IGZO thin-film transistors (TFTs) whereby the source/drain (S/D) region's conductivity enhanced in three different ways, that is, using SiNx interlayer plasma (hydrogen diffusion), using calcium (Ca as reducing metal) and using argon plasma (changing the atomic ratio). All these TFTs show comparable characteristics such as field-effect mobility (μFE) of over 10.0 cm²/(V.s), sub-threshold slope (SS-1) of 0.5 V/decade, and current ratio (ION/ IOFF) over 108. However, under negative-bias-illumination-stress (NBIS), all these TFTs showed strong degradation. We attributed this NBIS stability issue to the exposed S/D regions and changes in the conductivity of S/D contact regions. The hydrogen plasma-treated TFTs showed the worst NBIS characteristics. This is linked to increased hydrogen diffusion from the S/D contact regions to the channel. [ABSTRACT FROM AUTHOR]

We present a QVGA (320x240 with 3 sub-pixel) top-emitting AMOLED display with 250ppi resolution using a self-aligned (SA) IGZO TFT backplane on polyimide-foil with full barrier. The back plane process flow is based on a 7 layer photolithography process. The aperture ratio of the top-emitting OLEDs is approx. 80%. An integrated gate driver is shown that can be driven at operation speed equivalent to a 4k2k display at 100Hz. [ABSTRACT FROM AUTHOR]

The Internet of Things is driving extensive efforts to develop intelligent everyday objects. This requires seamless integration of relatively simple electronics, for example through 'stick-on' electronics labels. We believe the future evolution of this technology will be governed by Wright's Law, which was first proposed in 1936 and states that the cost of a product decreases with cumulative production. This implies that a generic electronic device that can be tailored for application-specific requirements during downstream integration would be a cornerstone in the development of the Internet of Things. We present an 8-bit thin-film microprocessor with a write-once, read-many(WORM)instruction generator that can be programmed after manufacture via inkjet printing. The processor combines organic p-type and soluble oxide n-type thin-film transistors in a new flavor of the familiar complementary transistor technology with the potential to be manufactured on a very thin polyimide film, enabling low-cost flexible electronics. It operates at 6.5 V and reaches clock frequencies up to 2.1 kHz. An instruction set of 16 code lines, each line providing a 9 bit instruction, is defined by means of inkjet printing of conductive silver inks. [ABSTRACT FROM AUTHOR]

In this work, we compared the thin-film transistor (TFT) characteristics of amorphous InGaZnO TFTs with six different source-drain (S/D) metals (MoCr, TiW, Ni, Mo, Al, and Ti/Au) fabricated in bottom-gate bottom-contact (BGBC) and bottom-gate top-contact (BGTC) configurations. In the BGTC configuration, nearly every metal can be injected nicely into the a-IGZO leading to nice TFT characteristics; however, in the BGBC configuration, only Ti/Au is injected nicely and shows comparable TFT characteristics. We attribute this to the metal-containing deposits in the channel and the contact oxidation during a-IGZO layer sputtering in the presence of S/D metal. In bias-stress stability, TFTs with Ti/Au S/D metal showed good results in both configurations; however, in the BGTC configuration, not all the TFTs showed as good bias results as Ti/Au S/D metal TFTs. We attribute this to backchannel interface change, which happened because of the metal-containing deposits at the backchannel during the final the SiO2 passivation. [ABSTRACT FROM AUTHOR]

We present a QQVGA (160times120 with 3 sub-pixel) top-emitting AMOLED display with 85ppi resolution using a self-aligned (SA) IGZO TFT backplane on polyimide-foil. The back plane process flow is based on a 5 layer photolithography process. The aperture ratio of the top-emitting OLEDs is approx. 25%. For operation at 6 V supply voltage (VDD), the brightness of the display exceeds 150cd/m2. On the same substrate a 160 stage gate-driver was measured at FHD rate. [ABSTRACT FROM AUTHOR]

In this work, we report on high-performance bottom-gate top-contact (BGTC) amorphous-Indium-Gallium-Zinc-Oxide (a-IGZO) thin-film transistor (TFT) with SiO2 as an etch-stop-layer (ESL) deposited by medium frequency physical vapor deposition (mf-PVD). The TFTs show field-effect mobility (μFE) of 16.0 cm2/(V.s), sub-threshold slope (SS−1) of 0.23 V/decade and off-currents (IOFF) < 1.0 pA. The TFTs with mf-PVD SiO2 ESL deposited at room temperature were compared with TFTs made with the conventional plasma-enhanced chemical vapor deposition (PECVD) SiO2 ESL deposited at 300 °C and at 200 °C. The TFTs with different ESLs showed a comparable performance regarding μFE, SS−1, and IOFF, however, significant differences were measured in gate bias-stress stability when stressed under a gate field of +/−1 MV/cm for duration of 104 s. The TFTs with mf-PVD SiO2 ESL showed lower threshold-voltage (VTH) shifts compared with TFTs with 300 °C PECVD SiO2 ESL and TFTs with 200 °C PECVD SiO2 ESL. We associate the improved bias-stress stability of the mf-PVD SiO2 ESL TFTs to the low hydrogen content of the mf-PVD SiO2 layer, which has been verified by Rutherford-Back-Scattering-Elastic-Recoil-Detection technique. [ABSTRACT FROM AUTHOR]

Abstract: In this study, the authors report high‐quality amorphous Indium‐Gallium‐Zinc‐Oxide (a‐IGZO) thin film transistors (TFTs) fabricated using a new back‐channel‐etch (BCE) process flow on Polyethylene Naphthalate (PEN) foil. The BCE flow allows a better scalability of TFTs for high‐resolution backplanes and related circuits. The maximum processing temperature was limited to less than 165oC in order to ensure good overlay accuracy (< 1µm) on foil. The presented process flow differs from to previously reported by defining the Mo S/D contacts by dry etch prior to a‐IGZO patterning. The TFTs show good electrical performance, including field‐effect mobilities in the range of 15.0cm2/(V.s), sub‐threshold slopes of 0.3V/decade and off‐currents <1.0pA on foil. Finally, the applicability of this new BCE process flow was demonstrated for TFT backplane driving a 32 x 32 active‐matrix organic light‐emitting diode (AMOLED) display. [ABSTRACT FROM AUTHOR]

In this study, we report high-quality amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistors (TFTs) fabricated on a polyethylene naphthalate foil using a new back-channel-etch (BCE) process flow. The BCE flow allows a better scalability of TFTs for high-resolution backplanes and related circuits. The maximum processing temperature was limited to less than 165 °C in order to ensure good overlay accuracy (<1 µm) on foil. The presented process flow differs from the previously reported flow as we define the Mo source and drain contacts by dry etch prior to a-IGZO patterning. The TFTs show good electrical performance, including field-effect mobilities in the range of 15.0 cm2/(V·s), subthreshold slopes of 0.3 V/decade, and off-currents <1.0 pA on foil. The threshold voltage shifts of the TFTs measured were less than 1.0 V after a stressing time of 104 s in both positive (+1.0 MV/cm) and negative (−1.0 MV/cm) bias directions. The applicability of this new BCE process flow is demonstrated in a 19-stage ring oscillator, demonstrated to operate at a supply voltage of 10 V with a stage delay time of 1.35 µs, and in a TFT backplane driving a 32 × 32 active-matrix organic light-emitting diode display. [ABSTRACT FROM AUTHOR]

In this study, the authors report on high-quality amorphous indium-gallium-zinc oxide thin-film transistors (TFTs) based on a single-source dual-layer concept processed at temperatures down to 150°C. The dual-layer concept allows the precise control of local charge carrier densities by varying the O2/Ar gas ratio during sputtering for the bottom and top layers. Therefore, extensive annealing steps after the deposition can be avoided. In addition, the dual-layer concept is more robust against variation of the oxygen flow in the deposition chamber. The charge carrier density in the TFT channel is namely adjusted by varying the thickness of the two layers whereby the oxygen concentration during deposition is switched only between no oxygen for the bottom layer and very high concentration for the top layer. The dual-layer TFTs are more stable under bias conditions in comparison with single-layer TFTs processed at low temperatures. Finally, the applicability of this dual-layer concept in logic circuitry such as 19-stage ring oscillators and a TFT backplane on polyethylene naphthalate foil containing a quarter video graphics array active-matrix organic light- emitting diode display demonstrator is proven. [ABSTRACT FROM AUTHOR]

Abstract: We present a QQVGA top emitting monochrome AMOLED display with 85dpi resolution using an organic TFT backplane on low temperature PEN-foil. The backplane process flow is based on a 7 layer photolithography process that yields a final mobility of the OTFT of ∼0.4cm2/Vs. The aperture ratio of the top-emitting OLEDs is over 75%. For operation at 10V supply voltage (V DD), the brightness of the display using red and green OLEDs exceeds 200cd/m2. [Copyright &y& Elsevier]

The article presents research on n-type metal oxide thin-film transistors (TFTs) in flexible active-matrix organic light-emitting diode (AMOLED) displays. It discusses the performance of solution-based oxide n-type TFTs on low-voltage complementary circuitry on flexible polyimide foil. It explores the significance of the hybrid complementary technology on AMOLED displays.

Parameter variation in organic thin-film transistor (OTFT) technology is known to limit the yield of digital circuits. It is expected that complementary OTFT technology (C-TFT) will reduce the sensitivity to parameter variations. In this paper, we quantify the dependence of yield on transistor parameter variations for C-TFT and compare it to unipolar logic. First, a basic inverter model is developed and fitted to measured transfer characteristics of organic complementary inverters. Next, the inverter model is used in numerical simulations to determine how the noise margin of the inverter, a measure for its reliable operation, changes as a function of transistor parameter variations. The noise margin is significantly improved with respect to p-type-only inverters with similar parameters. Finally, we perform circuit-level yield predictions as a function of parameter spread using the noise-margin simulations performed earlier. [ABSTRACT FROM AUTHOR]

Abstract: We discuss the design and implementation of 64-bit and 128-bit plastic transponder chips for radio-frequency identification tags. The 64-bit chips, comprising 414 organic thin-film transistors, are integrated into fully functional plastic radio-frequency identification tags with 13.56MHz communication. The required supply voltage on the tag is generated from the AC input signal detected by the antenna, using a plastic double half-wave rectifier circuit. The tag is fully functional at a magnetic field strength of 1.26A/m, which is below the minimum required radio-frequency magnetic field stated in the standards. We discuss the reading distance that can be achieved with our plastic rectifiers, and show that this reading distance is not limited by the performance of the plastic rectifier or transponder chip. The 128-bit transponder chip includes further features such as Manchester data encoding and a basic ALOHA anti-collision protocol. It employs 1286 organic thin-film transistors and generates the 128bit sequence at 24V supply voltage at a data rate of 1.5kb/s. Data rates up to 2kb/s could be achieved on chips with an 8-bit transponder chip. [Copyright &y& Elsevier]

AMOLED backplanes were fabricated on both rigid glass and flexible plastic substrates using a solution processed oxide semiconductor processed at temperatures <250C with mobilities greater than 2 cm2/Vs. The backplanes were integrated onto a thin film moisture barrier and QQVGA AMOLED displays were successfully fabricated. [ABSTRACT FROM AUTHOR]

Abstract: We present experimental results using an alternative cross-linker for poly(4-vinylphenol) (PVP) that allows lowering of the thermal budget of the cross-linking reaction to 130°C which compares very favorable to the 180°C required by the commonly used cross-linking agent poly(melamine-co-formaldehyde). Furthermore, we characterize the dielectric properties of a 200nm thick layer and realize high quality organic thin film transistors using this low-temperature PVP as a gate-dielectric. [ABSTRACT FROM AUTHOR]

Recently, complex circuits of organic thin-film transistors have been shown. The use of complementary logic can significantly ease the design of large integrated circuits. However, the performance of complementary logic in organic thin-film technology has not been able to equivale that of unipolar logic, due to the difficulty to densely integrate and simultaneously optimize p-type and n-type transistors on a single substrate. Here, we develop an optimized complementary process for C60 n-type and pentacene p-type transistors, both having bottom-gate bottom-contact geometry. Using this complementary technology, we show ring-oscillators with a stage-delay below 1 μs at a supply-voltage of 20 V. [ABSTRACT FROM AUTHOR]

All applications of organic thin film transistors require patterning of the organic thin film to achieve a low off current and to prevent cross talk between neighboring transistors. A common method for patterning consists of using a protective layer and etching the uncovered small molecule film by oxygen plasma. One of the handicaps of this process is the observed degradation of the transistor characteristics. By varying the resist overlap, the authors show that the main cause of this performance degradation is, in fact, a far-reaching underetch of the oxygen plasma which can be overcome by choosing the right geometry of the resist pattern. [ABSTRACT FROM AUTHOR]

We have developed a method for integrating n- and p-type organic thin-film transistors (OTFTs) on the same substrate. An integrated shadow mask was used for the n- and p-type semiconductor patterning. The integrated shadow mask can be aligned with submicron accuracy relative to the OTFT substrate. This allows for the integration at transistor level of n- and p-type OTFTs on the same substrate. A complementary inverter was fabricated, showing excellent performance while operating at a supply voltage of 2 V. [ABSTRACT FROM AUTHOR]

The properties of the dielectric strongly influence the performance of organic thin-film transistors. In this letter, we show experimental results that quantify the influence of the roughness of the dielectric on the mobility of pentacene transistors and discuss the cause of it. We consider the movement of charge carriers out of the “roughness valleys” or across those valleys at the dielectric–semiconductor interface as the limiting step for the roughness-dependent mobility in the transistor channel. [ABSTRACT FROM AUTHOR]

In this work, we present the impact of S/D contact formation, that is, by SiN plasma doping (hydrogen incorporation), metallic reduction (by calcium) and by argon plasma (compositional change) on NBIS instabilities of self-aligned a-IGZO TFTs. [ABSTRACT FROM AUTHOR]

Abstract: In this work, a completely scalable integration process is presented for organic–inorganic complementary logic, based on low-temperature spin-coated n-type metal oxide TFTs and thermally evaporated p-type pentacene TFTs. Both transistor types are photolithographically processed side-by-side, without the use of any shadow mask. High performance n-type metal oxide TFTs, post-annealed at a maximum temperature of only 250°C, exhibit saturation mobilities exceeding 2cm2/(Vs), subthreshold swing as low as 0.19V/decade and I on/I off ratios beyond 107 after integration with p-type pentacene TFTs. Using this hybrid complementary technology, 5-stage and 19-stage ring-oscillators are demonstrated, operating at supply voltages as low as 2.5V. The ring-oscillators oscillate at a frequency of more than 110kHz, corresponding to stage delays as low as 0.74μs, at a supply bias of 20V. [Copyright &y& Elsevier]