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International audience; To face the growing complexity of System-on-Chips (SoCs) and their tight time-to-market constraints, Virtual Prototyping (VP) tools based on SystemC/TLM2.0 must get faster while maintaining accuracy. However, the ASI SystemC reference implementation remains sequential and cannot leverage the multiple cores of modern workstations. In this paper, we present SCale 2.0, a new implementation of a parallel and standard-compliant SystemC kernel, reaching unprecedented simulation speeds. By coupling a parallel SystemC kernel with shared resources access monitoring and process-level rollback, we can preserve SystemC atomic thread evaluation while leveraging the available host cores. We also generate process interaction traces that can be used to replay any simulation deterministically for debug purpose. Evaluation on baremetal applications shows ×15 speedup compared to the ASI SystemC kernel using 33 host cores reaching speeds above 2300 Million simulated Instructions Per Second (MIPS). Challenges related to parallel simulation of full software stack with modern operating systems are also addressed with speedup reaching ×13 during recording run and ×24 during the replay run.

International audience; Transaction level models of systems-on-chip in SystemC are commonly used in the industry to provide an early simulation environment. The SystemC standard imposes coroutine semantics for the scheduling of simulated processes, to ensure determinism and reproducibility of simulations. However, because of this, sequential implementations have, for a long time, been the only option available, and still now the reference implementation is sequential. With the increasing size and complexity of models, and the multiplication of computation cores on recent machines, the parallelization of SystemC simulations is a major research concern. There have been several proposals for SystemC parallelization, but most of them are limited to cycle-accurate models. In this paper we focus on loosely timed models, which are commonly used in the industry. We present an industrial context and show that, unfortunately, most of the existing approaches for SystemC parallelization can fundamentally not apply in this context. We support this claim with a set of measurements performed on a platform used in production at STMicroelectronics. This paper surveys existing techniques, presents a visualization and profiling tool and identifies unsolved challenges in the parallelization of SystemC models at transaction level.

International audience; SystemC/TLM models are commonly used in the industry to provide an early SoC simulation environment. The open source implementation of the SystemC simulator is sequential. The standard doesn't impose sequential executions, but makes this choice the easiest by imposing coroutine semantics. With the increasing size and complexity of models, and the multiplication of computation cores on recent machines, the parallelization of SystemC simulations is a major research concern. There have been several proposals for SystemC parallelization, but most of them are limited to cycle-accurate models. In this paper we give an overview of the practices in one industrial context. We explain why loosely timed models are the only viable option in this context. We also show that unfortunately, most of the existing approaches for SystemC parallelization can fundamentally not apply to these models. We support this claim with a set of measurements performed on a platform used in production at STMicroelectronics. This paper both surveys existing techniques and identifies unsolved challenges in the parallelization of SystemC/TLM models.

International audience; Modern systems-on-chips need sophisticated power-management policies to control their power consumption and temperature. These power-management policies are usually implemented partly in software, with hardware support. They need to be validated early, hence power and temperature-aware simulation techniques at the system-level need to be developed. Existing approaches for system-level power and thermal analysis usually either completely abstract the functionality (allowing only simple scenarios to be simulated), or run the functional simulation independently from the non-functional one. The approach presented in this paper allows a coupled simulation of a SystemC/TLM model, possibly including the actual embedded software, with a power and temperature solver such as ATMI or the commercial tool ACEplorer. Power and temperature analysis is done based on the stimuli sent by the SystemC/TLM platform, which in turn can take decisions based on the non-functional simulation.

International audience; The SystemC/TLM technologies are widely accepted in the industry for fast system-level simulation. An important limitation of SystemC regarding performance is that the reference implementation is sequential, and the official semantics makes parallel executions difficult. As the number of cores in computers increase quickly, the ability to take advantage of the host parallelism during a simulation is becoming a major concern. Most existing work on parallelization of SystemC targets cycle-accurate simulation, and would be inefficient on loosely timed systems since they cannot run in parallel processes that do not execute simultaneously. We propose an approach that explicitly targets loosely timed systems, and offers the user a set of primitives to express tasks with duration, as opposed to the notion of time in SystemC which allows only instantaneous computations and time elapses without computation. Our tool exploits this notion of duration to run the simulation in parallel. It runs on top of any (unmodified) SystemC implementation, which lets legacy SystemC code continue running as-it-is. This allows the user to focus on the performance-critical parts of the program that need to be parallelized.

International audience; Today's consumer electronics industry uses modeling and simulation to cope with the complexity and time-to-market challenges of designing high-tech devices. In such context, Transaction-Level Modeling (TLM) is a widely spread modeling approach often used in conjunction with the IEEE standard SystemC discrete-event simulator. In this paper, we present a novel approach to modeling time that distinguishes between instantaneous actions and tasks with a duration. We argue that this distinction should be natural to the user. In addition, we show that it gives us important insight and better comprehension of what actions can overlap in time. We are able to exploit this distinction to parallelize the simulation, achieving an important speedup and exposing subtle software bugs related to parallelism. We propose a set of primitives and discuss the design decisions, expressiveness and semantics in depth. We present a research simulator called jTLM that implements all these ideas.

Virtual prototypes are simulators used in the consumer electronics industry. Transaction-level Modeling (TLM) is a widely used technique for designing such virtual prototypes. In particular, they allow for early development of embedded software. The SystemC modeling language is the current industry standard for developing virtual prototypes. Our experience suggests that writing TLM models exclusively in SystemC leads sometimes to confusion between modeling concepts and their implementation, and may be the root of some known bad practices. This paper introduces jTLM, an experimentation framework that allow us to study the extent to which common modeling issues come from a more fundamental constraint of the TLM approach. We focus on a discussion of the two modes of simulation scheduling: cooperative and preemptive. We confront the implications of these two modes on the way of designing TLM models, the software bugs exposed by the simulators and the performance.

International audience; SystemC is the de facto standard for modeling embedded systems. It allows system design at various levels of ab- stractions, provides typical object-orientation features and incorporates timing and concurrency concepts. A SystemC program is typically processed by a SystemC front-end in order to verify, debug and/or optimize the architecture. De- signing a SystemC front-end is a difficult task and existing approaches suffer from limitations. In this paper, we present a new approach that addresses most of these limitations. We detail this approach, based on an executable intermediate representation. We introduce PinaVM, a new, open-source SystemC front-end and implementation of our contributions. We give experimental results on this tool.

SystemC is a widely used tool for prototyping Systems-on-a-Chip. Being implemented as a C++ library, a plain C++ compiler is sufficient to compile and simulate a SystemC program. However, a SystemC program needs to be processed by a dedicated tool in order to visualize, formally verify, debug and/or optimize the architecture. In this paper we focus on the tools (called front-ends) used in the initial stages of processing SystemC programs. We describe the challenges in developing SystemC front-ends and present a survey of existing solutions. The limitations and capabilities of these tools are compared for various features of SystemC and intended back-end applications. We present typical examples that front-ends should ideally be able to process, and give theoretical limitations as well as experimental results of existing tools.

International audience; SystemC has become a de facto standard for the system-level description of systems-on-a-chip. SystemC/TLM is a library dedicated to transaction level modeling. It allows to define a virtual prototype of a hardware platform, on which the embedded software can be tested. Applying formal validation techniques to SystemC descriptions of SoCs requires that the semantics of the language be formalized. The model of time and concurrency underlying the SystemC definition is intermediate between pure synchrony and pure asynchrony. We list the available solutions for the semantics of SystemC/TLM, and explain how to connect SystemC to existing formal validation tools.

International audience; SystemC is becoming a de-facto standard for the early simulation of Systems-on-a-chip (SoCs). It is a parallel language with a scheduler. Testing a SoC written in SystemC implies that we execute it, for some well chosen data. We are bound to use a particular deterministic implementation of the scheduler, whose specification is non-deterministic. Consequently, we may fail to discover bugs that would have appeared using another valid implementation of the scheduler. Current methods for testings SoCs concentrate on the generation of the inputs, and do not address this problem at all. We assume that the selection of relevant data is already done, and we generate several schedulings allowed by the scheduler specification. We use dynamic partial-order reduction techniques to avoid the generation of two schedulings that have the same effect on the system's behavior. Exploring alternative schedulings during testing is a way of guaranteeing that the SoC description, and in particular the embedded software, is scheduler-independent, hence more robust. The technique extends to the exploration of other non-fully specified aspects of SoC descriptions, like timing.

International audience; We describe a toolbox for the analysis of Systems-on-a-chip described in SystemC at the transactional level. The tools are able to extract information from SystemC code, and to build a set of parallel automata that capture the semantics of a SystemC design, including the transaction-level specific constructs. As far as we know, this provides the first executable formal semantics of SystemC. Being implemented as a traditional compiler front-end, it is able to deal with general SystemC designs. The intermediate representation is now connected to existing formal verification tools via appropriate encodings. The toolbox is open and other tools will be used in the future.

International audience; We describe a toolbox for the analysis of Systems-on-a-chip written in SystemC at the transaction level. The tool is able to extract information from SystemC code, and to build a set of parallel automata that capture the semantics of a SystemC design, including the transaction-level specific constructs. As far as we know, this provides the first executable formal semantics of SystemC. Being implemented as a traditional compiler front-end, it is able to deal with general SystemC designs. The intermediate representation is now connected to existing formal verification tools via appropriate encodings. The toolbox is open and other tools will be used in the future.

A System-on-Chip (SoC) is a complete digital electronic system integrated on a single silicon chip called the hardware. This hardware is usually accompanied by dedicated software, the complexity and development time of which increases year by year. However, the highly competitive environment of SoC design imposes limited time-to-market. It is therefore necessary to develop hardware and software simultaneously in a process called "hardware-software codesign". Since hardware prototypes are initially unavailable, software developers rely on virtual prototypes of the targeted SoC. A virtual prototype is a simulator capable of running the software for the SoC being designed and executable on a conventional computer called the host. The SystemC/TLM-2.0 library is one of the most popular libraries for virtual prototyping of SoC. It allows hardware modeling and simulation using the principle of discrete event simulation (DES). This simulation technique sequentially executes the various processes representing the behavior of the modeled hardware according to the so-called coroutine semantics. This guarantees the reproducibility of the simulations while simplifying the writing of the models. However, DES also constrains the use of a single host core, greatly limiting simulation speed. This thesis proposes a parallelization technique for SystemC loosely timed TLM simulation that preserves coroutine semantics. SCale 2.0, the proposed parallel SystemC kernel, is based on the parallel evaluation of the processes of each evaluation phase as well as on the observation of their interactions, mainly via shared memory. Each shared resource is thus associated with a state machine designed to classify these resources and to define the access policy to them. Thus, each process can possibly be sequentialized before accessing a certain shared resource to prevent any interaction with other processes, which could violate the semantics of coroutines. In spite of this, dependencies can form between processes, for example when accessing the same memory address. In particular, in case of circular dependency between processes called conflict, the coroutine semantics is no longer respected and the simulation becomes invalid. All interactions are therefore controlled at the end of each evaluation phase to validate its evaluation. The storage of these dependencies also allows to replay a simulation identically. In the event of an error, a backtracking is performed using a CRIU-based Linux process backup and restore system to re-execute the simulation and avoid the error. However, the simulation of a complete operating system such as Linux generates a very high number of conflicts in this configuration, the cost of which cancels the benefits obtained by parallelization. As the conflicts are mostly caused by the operating system code itself, it was decided to detect the latter via the privilege level of the simulated processors and to force the sequential simulation of the operating system code. This method was evaluated on a variety of models composed of 1 to 32 simulated RISC-V cores, running benchmarks with and without Linux and simulated on a dual-processor machine with 36 cores. In the parallel simulation of 32 cores, the speedup against the reference SystemC Accellera kernel was up to x15 on the benchmarks without Linux with speeds between 800 and 2000 million simulated instructions per second. The speedup varies between x9 and x13 for Linux-based benchmarks and between x12 and x24 when replaying these simulations, Un système sur puce (SoC) est un système électronique numérique complet intégré sur une unique puce de silicium appelée le matériel. Ce matériel est généralement assorti d'un logiciel dédié dont la complexité et le temps de développement augmentent d'année en année. Le contexte hautement concurrentiel de la conception de systèmes sur puce impose cependant des temps de mise sur le marché restreints. Il est de ce fait nécessaire de recourir au développement simultané du matériel et du logiciel au sein d'un processus dénommé "hardware-software codesign". Les prototypes matériels étant initialement indisponibles, les développeurs logiciel s'appuient sur des prototypes virtuels du SoC visé. Un prototype virtuel est un simulateur capable d'exécuter le logiciel destiné au SoC en cours de conception et exécutable sur un ordinateur conventionnel appelé l'hôte. La bibliothèque SystemC/TLM-2.0 est parmi les plus populaires pour le prototypage virtuel de SoC. Elle permet la modélisation du matériel ainsi que sa simulation suivant le principe de la simulation à événements discrets (DES). Cette technique de simulation exécute séquentiellement les divers processus représentant le comportement du matériel modélisé d'après la sémantique dite de coroutines. Cela garanti la reproductibilité des simulations tout en simplifiant l'écriture des modèles. Cependant, la DES contraint également à l'utilisation d'un unique cœur de l'hôte, limitant grandement la vitesse de simulation. Cette thèse propose une technique de parallélisation de simulation SystemC à temps dit relâché et qui préserve la sémantique de coroutine. SCale 2.0, le noyau SystemC parallèle proposé, repose sur l'évaluation parallèle des processus de chaque phase d'évaluation ainsi que sur l'observation de leurs interactions, principalement via mémoire partagée. Chaque ressource partagée est ainsi associée à une machine-à-états conçue afin de classifier ces ressources et de définir la politique d'accès à ces dernières. Ainsi, chaque processus peut éventuellement être séquentialité avant l'accès à une certaine ressource partagée afin d'empêcher toute interaction avec les autres processus, ce qui risquerait de violer la sémantique de coroutines. Malgré cela, des dépendances peuvent se former entre les processus, lors de l'accès à une même adresse mémoire par exemple. En particulier, en cas de dépendance circulaire entre processus appelée conflit, la sémantique de coroutine n'est plus respectée et la simulation devient invalide. L'intégralité des interactions est donc contrôlée à l'issue de chaque phase d'évaluation afin de valider son bon déroulement. Le stockage de ces dépendances permet aussi de rejouer une simulation à l'identique. En cas d'erreur, un retour en arrière est opéré à l'aide d'un système de sauvegarde et restauration de processus Linux basé sur CRIU afin de réexécuter la simulation en évitant l'erreur. La simulation d'un système d'exploitation complet tel que Linux engendre cependant dans cette configuration un nombre très important de conflits dont le coût annule les bénéfices obtenus par parallélisation. Les conflits étant très majoritairement causés par le code du système d'exploitation lui-même, il a été choisi de détecter ce dernier via le niveau de privilège des processeurs simulés et de forcer la simulation séquentielle du code du système d'exploitation. Cette méthode a été évaluée sur une variété de modèles composés de 1 à 32 cœurs RISC-V simulés, exécutant des benchmarks avec et sans Linux et simulés sur une machine biprocesseur comportant 36 cœurs. Lors de la simulation parallèle de 32 cœurs, les gains de performance (speedup) face au noyau SystemC de référence Accellera atteignent alors x15 sur les benchmarks sans Linux avec des vitesses entre 800 et 2000 millions d'instructions simulées par seconde. Le speedup varie entre x9 et x13 dans le cas des benchmarks s'appuyant sur Linux et entre x12 et x24 en rejouant ces simulations