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The potential of electrophoretic deposition as a shaping process of free-standing objects with a gradient in composition is investigated. The capability to produce relatively thick continuously graded ZrO2-Al2O3 and WC-Co-Ti(C,N) discs was explored. After electrophoretic deposition, the dried deposits were cold isostatically pressed and pressureless sintered. In order to create a symmetric gradient profile along the thickness of the plates, a mathematical model for the EPD process was developed in order to predict the composition and slope of the gradient profile in the discs from the starting composition of the suspension, the EPD operating parameters and the powder-specific EPD characteristics. The sintered graded materials have a continuous variation in composition, microstructure and mechanical properties. In the illustrated ZrO2-Al2O3 example, the ZrO2 content increases from 0 vol% on the outer surface up to 25 vol% in the core. For the WC-Co-Ti(C,N) discs, the Ti(C,N) content decreases from 5 wt% on the outer edge to 0 wt% in the bulk of the material. In both materials, a hard outer rim and a tough core are obtained. Finally, the residual surface stresses of the densified graded ZrO2-Al2O3 discs were investigated. [ABSTRACT FROM AUTHOR]

Abstract: A comparative investigation of high-energy neutrons effect on strained and non-strained devices with different geometries is presented. Both single-gate planar and multiple-gate (MuG) silicon-on-insulator (SOI) devices are considered. Device response to the neutron irradiation is assessed through the variations of threshold voltage and transconductance maximum. The difference between strained and non-strained device response to the high-energy neutrons exposure is clearly evidenced. The reasons for such a difference are discussed. Analysis of the experimental results allows for suggesting that strain relaxation is one of the probable causes. [Copyright &y& Elsevier]

Abstract: Strain engineering based on either a global approach using high-mobility substrates or the implementation of so-called processing-induced stressors has become common practice for 90 nm and below CMOS technologies. Although the main goal is to improve the performance by increasing the drive current, other electrical parameters such as the threshold voltage, the multiplication current, the low frequency noise and the gate oxide quality in general may be influenced. This paper reviews the impact of different global and local strain engineering techniques on the gate stack quality and its reliability, including hot carrier performance, negative bias temperature instabilities, time dependent dielectric breakdown and radiation hardness. Recent insights will be discussed and the influence of different strain engineering approaches illustrated. [Copyright &y& Elsevier]

Abstract: The impact of strain-engineering on the low frequency of n-channel tri-gate FinFETs fabricated on silicon on insulator (SOI) substrates noise is reported. The work is first focused on the study of nFinFETs with a standard structure and with strain-engineered channel structures, using either global or local straining techniques, or a combination of both. A carrier number fluctuation dominant flicker noise has been observed for all devices. Whereas no clear correlation between the applied strain techniques and the 1/f noise level has been found, an unusual noise spectral density was observed for the devices with selective epitaxial grown (SEG) source and drain regions. This unusual noise behaviour has been investigated for different fin widths (0.15μm up to 3μm) and different temperature conditions (150K up to 300K). An empirical model is proposed in order to explain this unusual noise behaviour. Moreover, two Lorentzians attributed to defects in the depletion region of the silicon fin were observed, and energy level and cross-section of these defects were estimated. [Copyright &y& Elsevier]