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We present a U-bend design for traveling wave III-V gain devices, such as semiconductor optical amplifiers and laser diodes. The design greatly simplifies the butt-coupling between the III-V chip and silicon-on-insulator photonic circuit by bringing the I/O ports on one facet. This removes the need for precise dimension control otherwise required for 2-side coupling, therefore increasing the yield of mounted devices towards 100%. The design, fabrication and characterization of the U-bend device based on Euler bend geometry is presented. The losses for a bend with a minimum bending radius of 83 μm are 1.1 dB. In addition, we present an analysis comparing the yield and coupling losses of the traditionally cleaved devices with the results that the Euler bend approach enable, with the final conclusion that the yield is improved by several times while the losses are decreased by several dB.

In this paper, we report the fabrication of an optical tranceiver engine that is based on a 12μm silicon on insulator (SOI) waveguide platform and directly modulated vertical cavity surface emitting lasers (VCSELs). The main motivation for using 12 μm thick SOI waveguides is low-loss coupling to standard SM fibers with relaxedalignment tolerances. We demonstrate 25.7Gb/s operation of the complete optical interconnect link channel.

Stimulated by a series of important breakthrough, silicon photonics has been experiencing a significant development for several years. Indeed, due to exponential growth of data traffic inside datacenters, an alternative solution to metallic interconnects has been proposed to address very high transmission rates while ensuring a low energy consumption and a reasonable cost. Promising applications are in the field of both long- and short-distance optical communications. Long-range interconnects between datacenter equipment currently target an aggregate throughput of 400 Gb/s while short-reach interconnects are involved in high performance computers between a processor and a memory bank.STMicroelectronics has been developing a silicon photonic platform on 300 mm wafers since 2012. The main objectives are: the design of passive and active optical components to achieve an elementary 20 Gb/s transceiver, the increased integration of electro-optic devices to form a photonic interposer, the ability to manage several wavelengths.In this context, this PhD report deals with a testchip development at wafer level, proposing the integration of anelectro-optic transmitter. This solution benefits from the three dimensions assembly architecture of the dies within the photonic interposer and can handle the heterogeneity of electrical and optical components.This work first proposes to study the optical modulator which is based on a ring resonator. The ring bandwidth is optimized to operate up to 50 Gb/s. Secondly, the 55nm CMOS electrical driver design is described and the trade-off between transmitter speed and power consumption is highlighted. Both devices are fabricated on distinct technological platforms, then characterized and analyzed with respect to their respective models. A first integration of the complete transmitter is assembled through wire-bonding method, which enables to validate the transmitter operation. Finally, the last part of the report is devoted to the preparation of a 3D demonstrator based on micro-copper pillars assembly. The demonstrator integrates a wavelength division multiplexed link with 16 channels, which is expected to achieve a total throughput of 320 Gb/s. In addition, the system study enables to ensure that the final interconnect will respect power consumption constraints., La photonique sur silicium connaît depuis plusieurs années un fort développement avec la démonstration d’importants résultats concernant les interconnexions optiques. En effet, l’explosion du trafic de données au sein des centres de données a nécessité de trouver une solution annexe aux interconnexions métalliques afin de supporter de très hauts débits de transmission, tout en assurant une faible consommation énergétique et un coût raisonnable. Les applications de la photonique se situent d’une part dans le domaine des communications à longue distance entre équipements dont les standards actuels visent un débit de 400 Gb/s, et d’autre part dans le domaine des calculateurs à haute performance afin de réaliser les interconnexions courte distance entre un processeur et une banque de mémoires.STMicroelectronics s’est lancé depuis 2012 dans le développement d’une plateforme photonique sur silicium sur wafers de 300mm. Les principaux objectifs sont : la conception des composants optiques passifs et actifs pour réaliser un transceiver élémentaire à un débit de 20 Gb/s, l’intégration accrue des dispositifs électro-optiques afin de constituer un interposeur photonique, la capacité à gérer plusieurs longueurs d’onde.Dans ce contexte, le sujet de cette thèse porte sur la mise au point d’un circuit de qualification proposant l’intégration d’un transmetteur électro-optique à l’échelle de la puce.Cette solution tire bénéfice de l’architecture de l’assemblage en trois dimensions des éléments constitutifs au sein de l’interposeur et permet de traiter l’hétérogénéité des composants électriques et optiques.Dans ces travaux, nous proposons dans un premier temps d’étudier le modulateur optique. Celui-ci repose sur l’utilisation d’un anneau résonant dont la bande passante est optimisée afin de permettre des débits jusqu’à 50 Gb/s. Dans un second temps, nous décrivons la conception du driver électrique en technologie CMOS 55nm et expliquons le compromis mis en jeu entre la vitesse et la puissance consommée par le transmetteur. Les deux dispositifs sont fabriqués sur des plateformes distinctes, puis caractérisés et analysés par rapport à leur modèle respectif. Puis, nous réalisons une première intégration du transmetteur complet via un assemblage wire-bonding, ce qui nous permet de valider son fonctionnement et d’identifier les difficultés d’une telle co-intégration. Enfin, la dernière partie de la thèse est consacrée à la préparation d’un démonstrateur intégrant, dans un assemblage 3D à base de micro-piliers en cuivre, un lien électro-optique capable de transmettre 16 canaux à 20 Gb/s. Le multiplexage en longueurs d’onde déployé dans ce lien devrait permettre d’atteindre un débit total de 320 Gb/s. De plus, l’étude énergétique du système permet de s’assurer que l’interconnexion finale respectera les contraintes de consommation de puissance.

Stimulated by a series of important breakthrough, silicon photonics has been experiencing a significant development for several years. Indeed, due to exponential growth of data traffic inside datacenters, an alternative solution to metallic interconnects has been proposed to address very high transmission rates while ensuring a low energy consumption and a reasonable cost. Promising applications are in the field of both long- and short-distance optical communications. Long-range interconnects between datacenter equipment currently target an aggregate throughput of 400 Gb/s while short-reach interconnects are involved in high performance computers between a processor and a memory bank.STMicroelectronics has been developing a silicon photonic platform on 300 mm wafers since 2012. The main objectives are: the design of passive and active optical components to achieve an elementary 20 Gb/s transceiver, the increased integration of electro-optic devices to form a photonic interposer, the ability to manage several wavelengths.In this context, this PhD report deals with a testchip development at wafer level, proposing the integration of anelectro-optic transmitter. This solution benefits from the three dimensions assembly architecture of the dies within the photonic interposer and can handle the heterogeneity of electrical and optical components.This work first proposes to study the optical modulator which is based on a ring resonator. The ring bandwidth is optimized to operate up to 50 Gb/s. Secondly, the 55nm CMOS electrical driver design is described and the trade-off between transmitter speed and power consumption is highlighted. Both devices are fabricated on distinct technological platforms, then characterized and analyzed with respect to their respective models. A first integration of the complete transmitter is assembled through wire-bonding method, which enables to validate the transmitter operation. Finally, the last part of the report is devoted to the preparation of a 3D demonstrator based on micro-copper pillars assembly. The demonstrator integrates a wavelength division multiplexed link with 16 channels, which is expected to achieve a total throughput of 320 Gb/s. In addition, the system study enables to ensure that the final interconnect will respect power consumption constraints.; La photonique sur silicium connaît depuis plusieurs années un fort développement avec la démonstration d’importants résultats concernant les interconnexions optiques. En effet, l’explosion du trafic de données au sein des centres de données a nécessité de trouver une solution annexe aux interconnexions métalliques afin de supporter de très hauts débits de transmission, tout en assurant une faible consommation énergétique et un coût raisonnable. Les applications de la photonique se situent d’une part dans le domaine des communications à longue distance entre équipements dont les standards actuels visent un débit de 400 Gb/s, et d’autre part dans le domaine des calculateurs à haute performance afin de réaliser les interconnexions courte distance entre un processeur et une banque de mémoires.STMicroelectronics s’est lancé depuis 2012 dans le développement d’une plateforme photonique sur silicium sur wafers de 300mm. Les principaux objectifs sont : la conception des composants optiques passifs et actifs pour réaliser un transceiver élémentaire à un débit de 20 Gb/s, l’intégration accrue des dispositifs électro-optiques afin de constituer un interposeur photonique, la capacité à gérer plusieurs longueurs d’onde.Dans ce contexte, le sujet de cette thèse porte sur la mise au point d’un circuit de qualification proposant l’intégration d’un transmetteur électro-optique à l’échelle de la puce.Cette solution tire bénéfice de l’architecture de l’assemblage en trois dimensions des éléments constitutifs au sein de l’interposeur et permet de traiter l’hétérogénéité des composants électriques et optiques.Dans ces travaux, nous proposons dans un premier temps d’étudier le modulateur optique. Celui-ci repose sur l’utilisation d’un anneau résonant dont la bande passante est optimisée afin de permettre des débits jusqu’à 50 Gb/s. Dans un second temps, nous décrivons la conception du driver électrique en technologie CMOS 55nm et expliquons le compromis mis en jeu entre la vitesse et la puissance consommée par le transmetteur. Les deux dispositifs sont fabriqués sur des plateformes distinctes, puis caractérisés et analysés par rapport à leur modèle respectif. Puis, nous réalisons une première intégration du transmetteur complet via un assemblage wire-bonding, ce qui nous permet de valider son fonctionnement et d’identifier les difficultés d’une telle co-intégration. Enfin, la dernière partie de la thèse est consacrée à la préparation d’un démonstrateur intégrant, dans un assemblage 3D à base de micro-piliers en cuivre, un lien électro-optique capable de transmettre 16 canaux à 20 Gb/s. Le multiplexage en longueurs d’onde déployé dans ce lien devrait permettre d’atteindre un débit total de 320 Gb/s. De plus, l’étude énergétique du système permet de s’assurer que l’interconnexion finale respectera les contraintes de consommation de puissance.

Silicon photonics with micron-scale Si waveguides offers most of the benefits of submicron SOI technology while avoiding most of its limitations. In particular, thick silicon-on-insulator (SOI) waveguides offer 0.1 dB/cm propagation loss, polarization independency, broadband single-mode (SM) operation from 1.2 to >4 μm wavelength and ability to transmit high optical powers (>1 W). Here we describe the feasibility of Thick-SOI technology for advanced optical interconnects. With 12 μm SOI waveguides we demonstrate efficient coupling between standard single-mode fibers, vertical-cavity surface-emitting lasers (VCSELs) and photodetectors (PDs), as well as wavelength multiplexing in small footprint. Discrete VCSELs and PDs already support 28 Gb/s on-off keying (OOK), which shows a path towards 50-100 Gb/s bandwidth per wavelength by using more advanced modulation formats like PAM4. Directly modulated VCSELs enable very power-efficient optical interconnects for up to 40 km distance. Furthermore, with 3 μm SOI waveguides we demonstrate extremely dense and low-loss integration of numerous optical functions, such as multiplexers, filters, switches and delay lines. Also polarization independent and athermal operation is demonstrated. The latter is achieved by using short polymer waveguides to compensate for the thermo-optic effect in silicon. New concepts for isolator integration and polarization rotation are also explained.

In this presentation, we give an overview of our recent progress in exploiting direct-write two-photon lithography for additive 3D fabrication of freeform micro-optical elements. These elements can be printed with highest precision in direct contact with the facets of photonic integrated circuits or optical fibers, thereby greatly simplifying alignment and improving coupling efficiency. The approach offers new perspectives for a wide variety of applications, ranging from advanced photonic multi-chip modules for high-speed communications and optical sensing to highly efficient astro-photonic systems. We are currently working on transferring the concept from laboratory demonstrations to industrial manufacturing.

Silicon-based integrated systems are actively pursued for sensing and imaging applications. A major challenge to realize highly sensitive systems is the integration of electronic, optical, mechanical and fluidic, all on a common platform. Further, the interface quality between the tiny optoelectronic structures and the substrate for alignment and coupling of the signals significantly impacts the system’s performance. These systems also have to be low-cost, densely integrated and compatible with current and future mainstream technologies for electronic-photonic integration. To address these issues, proper selection of the fabrication, integration and assembly technologies is needed. In this paper, wafer level bonding with advanced features such as surface activation and passive alignment for vertical electrical interconnections are identified as candidate technologies to integrate different electronics, optical and photonic components. Surface activated bonding, superior to other assembly methods, enables low-temperature nanoscaled component integration with high alignment accuracy, low electrical loss and high transparency of the interface. These features are preferred for the hybrid integration of silicon-based micro-opto-electronic systems. In future, new materials and assembly technologies may emerge to enhance the performance of these micro systems and reduce their cost. The article is a detailed review of bonding techniques for electronic, optical and photonic components in silicon-based systems.

International audience; This conference talk will sum up our recent contributions related to the integration of semiconductor carbon nanotubes (s-SWNTs) as an active material in silicon photonics. This work is motivated by the possible use of s-SWNTs for light emission, detection, and modulation relying on the same hybrid on-silicon integration platform. We will first describe experimental results carried out to prepare high quality thin polymer layers doped with purified s-SWNTs. Our efforts to integrate this effective active material in silicon photonic resonators and nanocavities will be then described. We report cavity enhanced near infrared emission from nanotubes accompanied with a spectral narrowing effect when increasing pumping power levels and a threshold-like behavior regarding device light emission.

This Ph.D. work is a contribution to the modeling and the experimental study of slot photonic crystal cavities for hybrid on-silicon integration. Among the design works, we first have used plane the wave expansion and finite-difference time-domain methods to design a series of mechanically robust (non-free membrane) SOI slot photonic crystal heterostructure cavities with resonance wavelengths in the telecommunication range, i.e. from 1.3 µm – 1.6 µm, with Q-factors of around several tens of thousands and mode volumes around 0.03(lambda/n)^3 after being infiltrated by cladding materials with typical index values around 1.5. We have then analytically and numerically studied the coupling between a slot photonic crystal cavity and a slot photonic crystal waveguide by using the coupled mode theory and FDTD simulation. Then we confirmed the ability to excite the cavity slot modes from a waveguide by using FDTD simulation. Finally, as a preliminary step towards the use of several coupled slotted cavities for future hybrid integration schemes, we have numerically and semi-analytically investigated photonic molecules made of two coupled slot photonic crystal cavities providing two different supermodes (bonding and antibonding ones) with controllable wavelength splitting. We successfully employed the tight-binding (TB) approach, which relies on the overlap of the two tightly confined cavity electric fields, to predict the supermodes frequencies and spatial distributions in several coupled slot photonic crystal cavity configurations.This exploratory work was supplemented by an experimental part, which focused on the investigation of a family of slot photonic crystal heterostructure cavities. The fabricated silicon on insulator hollow core cavities showed quality factors of several tens of thousands, i.e. from 18,000 to 31,000 and mode volume V of ~0.03(λ/n)3 after being infiltrated with liquids of ~1.46 refractive index, yielding Q/V ratio larger than 600,000, and reaching 1,000,000 in the best case (at λ ≈ 1.3 μm).This preliminary experimental stage gave rise to two types of additional developments.Firstly, the properties of the studied slot photonic crystal cavities have been investigated for index sensing applications by using different liquids with refractive index values ranging from 1.345 to 1.545. The considered photonic crystal resonators have demonstrated quality factors of several tens of thousands with sensitivities of ~235 nm/RIU and index sensing FOMs around 3,700, i.e. at the state of the art considering hollow core silicon integrated resonators.Secondly, in the view of the integration of active materials on silicon, the potential of these hollow core nanoresonators has been considered to enhance the photo-luminescence (PL) of semiconductor single-walled carbon nanotubes (SWNTs) integrated in thin films deposited on top of silicon. We have brought the first experimental demonstration of SWNTs PL collection (around lambda=1.28 µm) under vertical pumping at short wavelength (lambda=740 nm) from a slotted resonator into millimeter long integrated silicon waveguides, providing a first proof-of-concept step towards nanotube/Si-PhC integration as an active photonic platform. The reported works demonstrate the feasibility of integrating telecommunication wavelength nanotube emitters in silicon photonics as well as emphasize the role of slot photonic crystal cavities for on-chip hybrid integration.; Cette thèse est une contribution à la modélisation et à l'étude expérimentale de cavités à cristaux photoniques à fente développées en vue d’un intégration hybride de matériaux actifs sur silicium. Parmi les travaux de conception, nous avons d'abord utilisé la méthodes des ondes planes et la méthode des différences finies (FDTD) pour concevoir une série de cavités SOI à hétérostructures, mécaniquement robustes, infiltrées par des liquides d’indices (n environ 1,5), présentant des longueurs d'onde de résonance dans la gamme des télécommunications (1,3 μm - 1,6 μm), des facteurs de qualité de plusieurs dizaines de milliers, et des volumes modaux proches de 0,03 (lambda/n)3. Nous avons ensuite étudié analytiquement et numériquement le couplage entre une cavité à cristaux photoniques à fente et un guide d'onde à fente par la théorie des modes couplés, complétée par des simulations FDTD, qui ont permis de confirmer la possibilité d'exciter efficacement les modes de fente des cavités à partir d'un guide externe. Enfin, nous avons étudié numériquement et semi-analytiquement des géométries de molécules photoniques constituées de deux cavités à cristaux photoniques à fentes couplées, dont l’écart fréquentiel entre les supermodes a pu être ajusté en amplitude et en signe. Nous avons utilisé une méthode perturbative (« Tight binding ») pour estimer les distributions spatiales des modes des molécules photoniques et prédire leurs fréquences dans plusieurs configurations de cavités à cristaux photoniques à fentes couplées.Ce travail exploratoire a été complété par une partie expérimentale qui a porté sur l'étude d'une famille de cavités de hétérostructure à cristaux photoniques à fente. Les cavités à cœur creux fabriquées ont montré des facteurs de qualité (Q) de plusieurs dizaines de milliers, associés à des volumes modaux de l’ordre de V=0,03 (λ/n)^3 après infiltration de la fente et des trous des structures par des liquides d'indice de réfraction proches de 1,46. Des facteurs Q/V supérieurs à 600 000 et atteignant 1 000 000 dans le meilleur des cas (vers lambda=1,3µm) ont ainsi été observés. Cette phase expérimentale préliminaire a donné ensuite lieu à deux types de développements.Tout d'abord, les propriétés des cavités à cristaux photoniques à fentes ont été étudiées pour des applications en détection d'indice en volume, et testées en utilisant différents liquides d'indice de réfraction compris entre 1,345 à 1,545. Les résonateurs étudiés ont présenté des sensibilités de ~ 235 nm / RIU et des facteur de mérite de détection d'indice de l’ordre de 3700, à l’état de l’art pour des résonateurs silicium intégrés à cœur creux.Dans une autre direction, le potentiel des résonateurs diélectriques à fente a été exploré en vue d’une intégration des matériaux actifs sur silicium. Un polymère dopé aux nanotubes de carbone semiconducteurs a été déposé comme matériau de couverture en vue d’étudier le renforcement de la photoluminescence (PL) des nano-émetteurs sous pompage optique vertical à lambda=740nm. Les expériences conduites ont permis de corréler le renforcement de la PL des nanotubes avec les modes de résonance des cavités et de démontrer le couplage partiel de cette PL vers des guides SOI longs de plusieurs millimètres (collection par la tranche vers lambda=1.3µm), apportant une preuve de principe d’une possible intégration des nanotubes émetteurs en photonique sur silicium.

In this thesis, I have briefly introduced the background of my PhD research, current state-of-the-art design, and my PhD research objectives. Then, I demonstrate how to optimize the performance of PAM-4 transmitters based on lumped Silicon Photonic Mach-Zehnder Modulators (MZMs) for short-reach optical links. Firstly, we analyze the trade-off that occurs between extinction ratio and modulation loss when driving an MZM with a voltage swing less than the MZM’s Vπ. This is important when driver circuits are realized in deep submicron CMOS process nodes. Next, a driving scheme based upon a switched capacitor approach is proposed to maximize the achievable bandwidth of the combined lumped MZM and CMOS driver chip. This scheme allows the use of lumped MZM for high speed optical links with reduced RF driver power consumption compared to the conventional approach of driving MZMs (with transmission line based electrodes) with a power amplifier. This is critical for upcoming short-reach link standards such as 400Gb/s 802.3 Ethernet. The driver chip was fabricated using a 65nm CMOS technology and flip-chipped on top of the Silicon Photonic chip (fabricated using IMEC’s ISIPP25G technology) that contains the MZM. Open eyes with 4dB extinction ratio for a 36Gb/s (18Gbaud) PAM- 4 signal are experimentally demonstrated. The electronic driver chip has a core area of only 0.11mm 2 and consumes 236mW from 1.2V and 2.4V supply voltages. This corresponds to an energy efficiency of 6.55pJ/bit including Gray encoder and retiming, or 5.37pJ/bit for the driver circuit only. In the future, system level analysis should be carried out to investigate the critical pattern issue of the PAM4 optical transmitter. The potential solutions toward 1pJ/bit are given (lumped EAM and micro-ring modulator). In addition, the advanced modulation formats (16 QAM, discrete multitone modulation, and FFE) are presented based on the switched capacitor approach.

We present a vision for the hybrid integration of advanced transceivers at 1.3 μm wavelength, and the progress done towards this vision in the EU-funded RAPIDO project. The final goal of the project is to make five demonstrators that show the feasibility of the proposed concepts to make optical interconnects and packet-switched optical networks that are scalable to Pb/s systems in data centers and high performance computing. Simplest transceivers are to be made by combining directly modulated InP VCSELs with 12 μm SOI multiplexers to launch, for example, 200 Gbps data into a single polymer waveguide with 4 channels to connect processors on a single line card. For more advanced transceivers we develop novel dilute nitride amplifiers and modulators that are expected to be more power-efficient and temperatureinsensitive than InP devices. These edge-emitting III-V chips are flip-chip bonded on 3 μm SOI chips that also have polarization and temperature independent multiplexers and low-loss coupling to the 12 μm SOI interposers, enabling to launch up to 640 Gbps data into a standard single mode (SM) fiber. In this paper we present a number of experimental results, including low-loss multiplexers on SOI, zero-birefringence Si waveguides, micron-scale mirrors and bends with 0.1 dB loss, direct modulation of VCSELs up to 40 Gbps, ±0.25μm length control for dilute nitride SOA, strong band edge shifts in dilute nitride EAMs and SM polymer waveguides with 0.4 dB/cm loss.

A review of recent progress in hybrid integrated platforms for silicon photonics is presented. Integration of III-V semiconductors onto silicon-on-insulator substrates based on two different bonding techniques is compared, one comprising only inorganic materials, the other technique using an organic bonding agent. Issues such as bonding process and mechanism, bonding strength, uniformity, wafer surface requirement, and stress distribution are studied in detail. The application in silicon photonics to realize high-performance active and passive photonic devices on low-cost silicon wafers is discussed. Hybrid integration is believed to be a promising technology in a variety of applications of silicon photonics.

We present a vision for transceiver integration on a 3 µm SOI waveguide platform for systems scalable to Pb/s. We also present experimental results from the first building blocks developed in the EU-funded RAPIDO project. At 1.3 µm wavelength 80 Gb/s per wavelength is to be achieved using hybrid integration of III-V optoelectronics on SOI. Goals include athermal operation, low-loss I/O coupling, advanced modulation formats and packet switching. An example of the design results is an interposer chip that consists of 12 µm thick SOI waveguides locally tapered down to 3 µm to provide low-loss coupling between an optical single-mode fiber array and the 3 µm SOI chip. First example of experimental results is a 4x4 cyclic AWGs with 5 nm channel spacing, 0.4 dB/facet fiber coupling loss, 3.5 dB center-tocenter loss, and -23 dB adjacent channel crosstalk in 3.5x1.5 mm2 footprint. The second example result is a new VCSEL design that was demonstrated to have up to 40 Gb/s operation at 1.55 µm.

This thesis covers both the packaging of silicon photonic devices with fiber inputs and outputs as well as the integration of laser light sources with these same devices. The principal challenge in both of these pursuits is coupling light into the submicrometer waveguides that are the hallmark of silicon-on-insulator (SOI) systems. Previous work on grating couplers is leveraged to design new approaches to bridge the gap between the highly-integrated domain of silicon, the Interconnected world of fiber and the active region of III-V materials. First, a novel process for the planar packaging of grating couplers with fibers is explored in detail. This technology allows the creation of easy-to-use test platforms for laser integration and also stands on its own merits as an enabling technology for next-generation silicon photonics systems. The alignment tolerances of this process are shown to be well-suited to a passive alignment process and for wafer-scale assembly. Furthermore, this technology has already been used to package demonstrators for research partners and is included in the offerings of the ePIXfab silicon photonics foundry and as a design kit for PhoeniX Software’s MaskEngineer product. After this, a process for hybridly integrating a discrete edge-emitting laser with a silicon photonic circuit using near-vertical coupling is developed and characterized. The details of the various steps of the design process are given, including mechanical, thermal, optical and electrical steps. The interrelation of these design domains is also discussed. The construction process for a demonstrator is outlined, and measurements are presented of a series of single-wavelength Fabry-Pérot lasers along with a two-section laser tunable in the telecommunications C-band. The suitability and potential of this technology for mass manufacture is demonstrated, with further opportunities for improvement detailed and discussed in the conclusion.

Feasibility of micron-scale SOI waveguides for dense photonics integration is demonstrated. Compact circuits are obtained by applying multiple etching steps on 3-12 μm thick SOI layers. Optoelectronics is integrated on SOI using thermo compression bonding.

An overview of an integration platform with 1–10 µm thick silicon-on-insulator waveguides is given. It is suitable for the integration and packaging of optoelectronic and silicon photonic (nm-scale) chips. The platform can also contain many passive functions, such as spot-size converters, couplers, wavelength (de)multiplexers/filters and polarization splitters. The footprint of the platform is minimized by using multi-step patterning to realize e.g. mirrors and short MMI couplers

An overview of an integration platform with 1–10 µm thick silicon-on-insulator waveguides is given. It is suitable for the integration and packaging of optoelectronic and silicon photonic (nm-scale) chips. The platform can also contain many passive functions, such as spot-size converters, couplers, wavelength (de)multiplexers/filters and polarization splitters. The footprint of the platform is minimized by using multi-step patterning to realize e.g. mirrors and short MMI couplers

The European BOOM project aims at the realization of high-capacity photonic routers using the silicon material as the base for functional and cost-effective integration. Here we present the design, fabrication and testing of the first BOOMgeneration of hybrid integrated silicon photonic devices that implement key photonic routing functionalities. Ultra-fast all-optical wavelength converters and micro-ring resonator UDWDM label photodetectors are realized using either 4um SOI rib or SOI nanowire boards. For the realization of these devices, flip-chip compatible non-linear SOAs and evanescent PIN detectors have been designed and fabricated. These active components are integrated on the SOI boards using high precision flip-chip mounting and heterogeneous InP-to-silicon integration techniques. This type of scalable and cost-effective silicon-based component fabrication opens up the possibility for the realization of chip-scale, power efficient, Tb/s capacity photonic routers.

To enhance the functionality of the standard silicon photonics platform and to overcome its limitations, in particular for light emission, ultrafast modulation, and nonlinear applications, integration with novel materials is being investigated by several groups. In this paper, we will discuss, among others, the integration of silicon waveguides with ferroelectric materials such as lead zirconate titanate (PZT) and barium titanate (BTO), with electro-optically active polymers, with 2-D materials such as graphene and with III-V semiconductors through epitaxy. We discuss both the technology and design aspects.

The cost-effective integration of laser sources on Silicon Photonic Integrated Circuits (Si-PICs) is a key challenge to realizing the full potential of on-chip photonic solutions for telecommunication and medical applications. Hybrid integration can offer a route to high-yield solutions, using only known-good laser-chips, and simple freespace micro-optics to transport light from a discrete laser-diode to a grating-coupler on the Si-PIC. In this work, we describe a passively assembled micro-optical bench (MOB) for the hybrid integration of a 1550nm 20MHz linewidth laser-diode on a Si-PIC, developed for an on-chip interferometer based medical device. A dual-lens MOB design minimizes aberrations in the laser spot transported to the standard grating-coupler (15 μm x 12 μm) on the Si-PIC, and facilitates the inclusion of a sub-millimeter latched-garnet optical-isolator. The 20dB suppression from the isolator helps ensure the high-frequency stability of the laser-diode, while the high thermal conductivity of the AlN submount (300/W=m.°C), and the close integration of a micro-bead thermistor, ensure the stable and efficient thermo-electric cooling of the laser-diode, which helps minimise low-frequency drift during the approximately ~ 15s of operation needed for the point-of-care measurement. The dual-lens MOB is compatible with cost-effective passively-aligned mass-production, and can be optimised for alternative PIC-based applications.

In this paper, we report the fabrication of an optical tranceiver engine that is based on a 12μm silicon on insulator (SOI) waveguide platform and directly modulated vertical cavity surface emitting lasers (VCSELs). The main motivation for using 12 μm thick SOI waveguides is low-loss coupling to standard SM fibers with relaxedalignment tolerances. We demonstrate 25.7Gb/s operation of the complete optical interconnect link channel.

Combining photonic integrated circuits (PIC) with millimeter-wave electronics opens novel perspectives in generation and detection of ultra-broadband signals with disruptive potential for a wide variety of applications. Here, we will give an overview on our recent progress in the field of ultra-broadband photonic-electronic signal processing, covering device concepts such as silicon plasmonic integration, signal processing concepts such as Kramers-Kronig-based phase reconstruction of THz signals, as well as application demonstrations in the field of high-speed wireless data transmission.

Silicon photonics (SiPh) enables compact photonic integrated circuits (PICs), showing superior performance for a wide variety of applications. Various optical functions have been demonstrated on this platform that allows for complex and powerful PICs. Nevertheless, laser source integration technologies are not yet as mature, hampering the further cost reduction of the eventual Si photonic systems-on-chip and impeding the expansion of this platform to a broader range of applications. Here, we discuss a promising technology, micro-transfer-printing (mu TP), for the realization of III-V-on-Si PICs. By employing a polydimethylsiloxane elastomeric stamp, the integration of III-V devices can be realized in a massively parallel manner on a wafer without substantial modifications to the SiPh process flow, leading to a significant cost reduction of the resulting III-V-on-Si PICs. This paper summarizes some of the recent developments in the use of mu TP technology for realizing the integration of III-V photodiodes and lasers on Si PICs. (C) 2019 Author(s).