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We present a broadband parallel-combined compact Doherty power amplifier (PA) in a 28-nm bulk complementary metal–oxide–semiconductor (CMOS) device technology for fifth-generation (5G) millimeter-wave (mm-Wave) frequency band (n257, n258, and n261) applications. The proposed Doherty PA has a single transformer (TF)-based output matching network and an equivalent quarter-wavelength line placed between the carrier and peaking amplifiers, absorbing transistors’ output parasitic capacitances. Therefore, the Doherty PA occupies a very small die area and has a wide bandwidth characteristic compared with the conventional Doherty PA output matching network topologies (e.g., parallel- and series-combined Doherty PA output matching networks). The two-stage differential Doherty PA is implemented, which shows a saturation output power ($P_{\mathrm {OUT}}$) of >18.8 dBm and a peak power-added efficiency (PAE) of >30% at 27 GHz. It also exhibits a linear $P_{\mathrm {OUT}}$ of 12.4 dBm and an average PAE of 20.2% for 100 MHz 5G NR signal ($P_{\mathrm {OUT}}$ of 11.4 dBm and PAE of 18.1% for 8 $\times $ 100 MHz carriers) at the EVM of −25 dB. Over the frequency range of 24.5–29.5 GHz, the PA achieves a linear $P_{\mathrm {OUT}}$ of >11.2 dBm and a PAE of >14.5% (drain efficiency >20.8%). This PA occupies 640 $\mu \text{m}\,\,\times $ 250 $\mu \text{m}$ (core only) and is successfully integrated into a 32-channel RF phased-array transceiver IC for the first time. The IC die area is 10.2 mm $\times $ 6.4 mm and consumes about 120 mW per channel at $P_{\mathrm {OUT}}$ of 10.0 dBm. [ABSTRACT FROM AUTHOR]

This work reports a monolithic RF front-end module integrating bulk acoustic wave (BAW) filters, Lamb acoustic wave filters, and electronic RF silicon-on-insulator (RFSOI) switches to deliver single-chip multiband RF front-end module (RF-FEM) manufactured on commercial 200mm RF silicon-on-insulator (RFSOI) foundry technology. BAW and Lamb filters built in the same chip and within the same process enable multiband operation. Vertical System-on-Chip (SoC) integration of MEMS and RFSOI components contributes to footprint reduction up to 50%, compared to system-in-package (SiP) modules, and reduces the integration and design complexity of the modules. At its current state of development, this technology is suitable for diversity receive modules (DRX) for 4G/LTE and 5G bands. Extensive characterization results and case studies demonstrate the robustness of the integrated platform. Further productization of this technology will enable the next generation of hundred-filter 5G sub-6GHz RF-FEMs. [2020-0304] [ABSTRACT FROM AUTHOR]

In this letter, a frequency-tunable rectifier in the $C$ -band designed by a hybrid semiconductor integrated circuit (HySIC) concept is proposed. A GaAs monolithic microwave integrated circuit (MMIC) and a Si radio frequency integrated circuit (RFIC) were utilized as the HySIC configuration in the rectifier design. For the purpose of initial confirmation of this design validity, the GaAs and Si chips were fabricated and packaged onto the copper tungsten plate with gold plating. As measured results, frequency-tunable range from 3.82 to 4.55 GHz was measured. Maximum radio frequency (RF)–direct current (dc) conversion efficiency and output dc power in the measured power range from −10.0 to 17.8 dBm were 28.7% and 17.3 mW, respectively. [ABSTRACT FROM AUTHOR]

Series‐connected rectenna associations are proposed to improve the harvesting performance of conventional rectenna circuits by recovering power from different directions. With an available input power of −20 dBm, post‐layout simulations evaluated the total output power of four series‐connected rectennas designed in Complementary Metal Oxide Semiconductor Fully Depleted Silicon On Insulator (CMOS FD‐SOI) 28 nm technology, to 14 µW at maximum power point (MPP), while the post‐layout simulation of a single rectenna yields 5 µW at the same input power level. However, the rectenna association performance may be significantly degraded when dealing with different input power levels among rectennas. Therefore, a passive bypass circuit has been added at the output of the series association to short‐circuit the weakest rectenna. The proposed design is cost‐effective since there is a negligible silicon penalty and no additional power losses. In the designed four series‐connected rectenna association, the total output power is 7 µW at MPP with the bypass circuit when the strongest and the weakest rectennas receive −20 and −35 dBm, respectively. Also, thanks to the bypass circuit, the efficiency of the rectenna association and the ratio of maximum achieved power are improved by, respectively, 10 and 20%. [ABSTRACT FROM AUTHOR]

We integrate carbon nanotube (CNT) fabrication with standard commercial CMOS very large scale integration on a single substrate suitable for emerging hybrid nanotechnology applications. This cointegration combines the inherent advantages of CMOS and CNTs. These emerging applications include CNT optical, biological, chemical, and gas sensors that require complex CMOS electronics for sensor control, calibration, and signal processing. We demonstrate the successful cointegration on a single chip with a vehicle circuit, a two-transistor cascode megahertz amplifier utilizing both silicon n-channel MOSFET and CNT transistors with a total power consumption of 62.5 muW. [ABSTRACT FROM PUBLISHER]

A new T-model has been proposed for on-chip spiral inductors in this letter. In this model, we use less number of elements (only ten elements) than the conventional single-π model (11 elements), but it overcomes the main drawback of the latter. A simple parameter extraction method is proposed to get the elements' values without any optimization, and a good match with the measured data proves the model's accuracy up to the resonant frequency. Two partition factors are introduced to demonstrate the asymmetrical characteristics of the spiral layout, and their approximate invariability proves the model's validity. The factors are directly determined by the extracted model parameters instead of estimation. [ABSTRACT FROM AUTHOR]

In this paper, the technical considerations and broad business implications of RFID are focused. The basic RFID hardware elements are tags and readers. The data exchanged between these two elements may be encrypted or processed as needed. From a technical point of view, the challenges in designing an RFID tag are many. Silicon technology can deliver the required circuit performance at low cost and high volume and efforts are made to design a system on chip (SOC) at RF frequency. [ABSTRACT FROM PUBLISHER]

This study proposes a proper layout of on-chip inductors to diminish the coupling effect in silicon-based technology. Keeping self inductance constant, the mutual inductance is measured to characterize coupling effect in three test keys. A layout with variable metal width of inductor is found to alleviate mutual inductance. Experiment results demonstrate the mutual inductance decreases 33.5% compared with standard layout. This information will be helpful in implementation of more than one inductor into radio frequency integrated circuits (RFICs). [ABSTRACT FROM PUBLISHER]

A new compact model for monolithic transformers on silicon substrates is presented. The new lumped-element equivalent circuit model employs transformer loops to represent skin and proximity effects including eddy current loss in the windings of the transformer. In addition to the self-resistances and self-inductances of the windings, the effects of the frequency-dependent mutual resistance and mutual inductance are included in the model. The new compact model has been applied to a stacked transformer on a 10-Ω·cm CMOS substrate. The extracted circuit model shows very good agreement with data obtained by full-wave electromagnetic simulation and measurement over the frequency range of 0.1-10GHz. [ABSTRACT FROM PUBLISHER]

Conventional spiral inductors on silicon wafer have suffered low quality (Q) factor due to substrate loss. In this work, a technique that combines optimized shielding poly and proton implantation treatment is utilized to improve inductor Q-value. The optimized poly-silicon and proton-bombarded substrate have added 37% and 54% increment to the Q-value of inductors, respectively. If two techniques are combined, a phenomenal Q-value increment as high as 122% of 4-nH spiral inductors can be realized. The combination of the two means has created a multiplication of their individual contribution rather than addition. The technique used in this work shall become a critical measure to put inductors on silicon substrate with satisfactory performance for Si-based radio frequency integrated circuit applications. [ABSTRACT FROM PUBLISHER]

We have improved the Q-factor of a 4.6 nH spiral inductor, fabricated on a standard Si substrate, by more than 60%, by using an optimized proton implantation process. The inductor was fabricated in a 1-poly-6-metal process, and implanted after processing. The implantation increased the substrate impedance by ∼ one order of magnitude without disturbing the inductor value before resonance. The S-parameters were well described by an equivalent circuit model. The significantly improved inductor performance and VLSI-compatible process makes the proton implantation suitable for high performance RF ICs. [ABSTRACT FROM PUBLISHER]

A substrate coupling analysis flow is presented. The proposed method is fully compatible with the industry analogue/radio‐frequency design methodology, seamlessly integrates into the design environment, provides accurate estimation of the coupling effects and can model adequately all the mask design level isolation performance trends. Its accuracy is confirmed by correlating simulation results against on‐wafer silicon measurements in a 28 nm CMOS set of ring oscillators with a carrier frequency of 670 MHz. The mean error of the proposed method is 665 μV, whereas the error sigma is 765 μV. [ABSTRACT FROM AUTHOR]