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We report on the characterization, thanks to Raman spectroscopy and imaging of tensely strained Si films pseudomorphically grown on (001), (110), and (111) SiGe virtual substrates. The samples studied here are those described in the work of Destefanis et al. [J. Appl. Phys 106, 043508 (2009)]. They consist in 17-nm-thick strained Si layers grown at 650 °C with SiH4 as a gaseous precursor on top of polished SiGe virtual substrates of various surface orientations. We first derived the exact component array of the strain/stress field along the different growth directions. Because the relation between strain or stress and the Raman frequencies are complex, we also derive the strain-shift coefficients for the different substrate orientations considered in this work and the polarization selection rules. Visible and near-UV Raman spectroscopies were used to extract the in-plane lattice parameter of the SiGe virtual substrates and the tensile strain in the thin Si epitaxial layers on top. We have notably investigated thanks to Raman imaging the in-plane distribution of strain in Si layer/SiGe buffer stacks grown on (110) and (111) Si substrates. Original surface arrays have been highlighted for each surface orientation. Promising results have been obtained for (110) SiGe virtual substrates in terms of strain and layer quality while the technological usefulness of the (111) ones is more questionable. [ABSTRACT FROM AUTHOR]

We have grown by reduced pressure chemical vapor deposition Si/Si[sub 1-y]C[sub y]/Si heterostructures for electrical purposes. The incorporation of substitutional carbon atoms into Si creates a carrier confinement in the channel region of metal-oxide-semiconductor (MOS) transistors. Indeed, tensile strain Si[sub 1-y]C[sub y] layers present a type II band alignment with Si, with a conduction band offset of the order of 60 meV per at. % of substitutional carbon atoms. For small SiH[sub 3] CH[sub 3] flows, all the incoming carbon atoms are incorporated into substitutional sites. At 600 °C, when the SiH[sub 3] CH[sub 3] flow increases, the substitutional carbon concentration saturates at 1.12%. Meanwhile, the total carbon concentration C[sub T] still increases, following a simple law: C[sub T]/(1-C[sub T])=0.88 [sup *] [F(SiH[sup 3]CH[sub 3]) /F(SiH[sub 4])]. This is a sign that a growing number of C atoms incorporates into interstitial sites. The hydrogenated chemistry adopted does not enable one to achieve selectivity over SiO[sub 2]-masked wafers, but does not however generate any adverse loading effect. We have integrated Si/Si[sub 1-y]C[sub y]/Si stacks (which have been shown to be stable versus conventional gate oxidations and electrical activation anneals) into the channel region of ultrashort gate length (50 nm) nMOS transistors. Secondary ions mass spectrometry profiling has shown that C atoms segregate from the Si[sub 1-y]C[sub y] layer into the Si cap and the SiO[sub 2] gate, but also that they block the diffusion paths of B coming from the antipunch through layer towards the gate, generating very retrograde doping profiles. The addition of C leads to a degradation of the electron mobility which seems to be linked to the high amount of C atoms into interstitial sites. [ABSTRACT FROM AUTHOR]

Recent demonstrations of optically pumped lasers based on GeSn alloys put forward the prospect of efficient laser sources monolithically integrated on a Si photonic platform. For instance, GeSn layers with 12.5% of Sn were reported to lase at 2.5 µm wavelength up to 130 K. In this work, we report a longer emitted wavelength and a significant improvement in lasing temperature. The improvements resulted from the use of higher Sn content GeSn layers of optimized crystalline quality, grown on graded Sn content buffers using reduced pressure CVD. The fabricated GeSn micro-disks with 13% and 16% of Sn showed lasing operation at 2.6 µm and 3.1 lm wavelengths, respectively. For the longest wavelength (i.e., 3.1 µm), lasing behavior was demonstrated up to 180 K, with a threshold of 377 kW/cm² at 25 K. [ABSTRACT FROM AUTHOR]

Strain boosters are an effective way to improve performances in advanced CMOS FDSOI devices. Hole mobility is higher in pFETs with compressive channels. Meanwhile, electron mobility is higher for nFETs with tensile channels. We present an alternative technique to blanket sSOI substrates. The efficiency of the "Strained Silicon by Top Recrystallization of Amorphized SiGe on SOI" technique has been previously successfully demonstrated on blanket SOI (+ 1.6 GPa tensile strain achieved). Here we demonstrate a simple and efficient STRASS module integration in an advanced FDSOI route (14 nm design rules) which allows to cointegrate tensile Si for nFETs and unchanged pFETs. After pFETs have been protected (SiN), the STRASS technique has been used in the SOI nFET patterns. This process requires SiGe selective epitaxy, buried amorphization by ion implantation, recrystallization and SiGe removal. Raman spectroscopy is used to characterize the stress in Si areas with respect to process conditions (implantation, active area dimensions). Moreover, the mechanisms of SiGe relaxation will be discussed as function of device dimensions and SiGe layer properties (thickness, Ge content). We demonstrate the successful integration of localized STRASS module: tensile Si patterns (for nFETs) with a level of stress of + 1.6 GPa, cointegrated with unmodified pFETs. [ABSTRACT FROM AUTHOR]

We have obtained Anti-Phase Boundary (APB) free GaAs epilayers on "quasi-nominal" (001) silicon substrates, while using a thick germanium strain relaxed buffer between the GaAs layer and the silicon substrate in order to accommodate the 4% lattice mismatch between the two. As silicon (001) substrates always have a small random offcut angle from their nominal surface plane, we call them "quasi-nominal." We have focused on the influence that this small (≤0.5°) offcut angle has on the GaAs epilayer properties, showing that it greatly influences the density of APBs. On 0.5° offcut substrates, we obtained smooth, slightly tensile strained (R=106%) GaAs epilayers that were single domain (e.g., without any APB), showing that it is not necessary to use large offcut substrates, typically 4° to 6°, for GaAs epitaxy on silicon. These make the GaAs layers more compatible with the existing silicon manufacturing technology that uses "quasi-nominal" substrates. [ABSTRACT FROM AUTHOR]

Strained silicon on insulator wafers are today envisioned as a natural and powerful enhancement to standard SOI wafers and/or bulk-like strained Si layers. This paper is intended to demonstrate through miscellaneous structural results how a layer transfer technique such as the Smart CutTM technology can be used to obtain good quality tensile-strained silicon on insulator wafers. Such a technique uses preferentially hydrogen implantation to peel-off the very top part of an epitaxial stack and transfer it onto another silicon substrate. The formation of an insulator, prior to the bonding onto a new silicon substrate enables the formation of a “semiconductor on insulator” structure. Two approaches based on the Smart Cut technique are considered in this paper. The first one relies on the formation by layer transfer of a relaxed SiGe on insulator (“SGOI”) substrate on which a tensile-strained Si layer is then grown. The second one is based on the transfer of a SiGe relaxed buffer/Si cap stack. A SiGe-free tensile-silicon on insulator (sSOI) substrate is then obtained after the selective etching of the top SiGe layer. The epitaxial layers studied in this article are of two kinds: (i) the thick, nearly fully relaxed SiGe layers (with or without tensile-strained Si layers on top depending on the final structure targeted: SGOI or sSOI) used as the donor wafers in layer transfer operations, and (ii) the thin, relaxed SiGe layers and the thin, tensile-strained Si epitaxial films grown on SGOI substrates. In-depth physical characterizations of these epitaxial layers are used to evaluate the quality of the transferred layers in terms of thickness uniformity, Ge content, strain control, dislocation densities etc… Detailed experiments are also used to demonstrate that these final substrates are compatible with future CMOS applications. The sSOI approach is particularly challenging in this respect as the strain needs to be maintained during many technological operations such as layer transfer, selective removal of the SiGe, high temperature thermal treatments etc. First results showing how the strain is changing during such operations are presented. [Copyright &y& Elsevier]

In this letter, the electrostatic and the performance of cylindrical silicon nanowire (NW) MOSFETs with an omega-shaped gate and diameters down to 8 nm are investigated. The impact of silicon nitride (SiN) spacer thickness (7, 10, or 15 nm) on short-channel performance is examined. The tradeoff between superior electrostatic confinement and electrical performance, which will be an essential consideration for the design of future NW devices, is clearly observed. Finally, a comparison with trigate NWs shows an improved electrostatic control for a cylindrical-shaped gate, as theoretically expected. [ABSTRACT FROM PUBLISHER]

Hole velocity and mobility are extracted from quantum-well (QW) biaxially strained \Si0.5\Ge0.5 channel metal–oxide–semiconductor field-effect transistors (MOSFETs) on silicon-on-insulator wafers. Devices have been fabricated at sub-100-nm gate length with \HfO2/\TiN gate stacks. A significant hole mobility enhancement over the strained Si mobility curve is observed for QW MOSFETs. We also discuss the relationship between velocity and mobility of the strained SiGe channels with high Ge content for \langle\100\rangle and \langle\110\rangle crystal directions. Whereas the mobility increases by 18% for \langle\100\rangle with respect to \langle\110\rangle, it translates into a modest 8% velocity increase. [ABSTRACT FROM AUTHOR]

Hole mobilities of quantum-well p-MOSFETs on strained Si (sSi)/Si0.5Ge0.5/strained SOI (sSOI) and Si/Si00.5Ge0.5/SOI heterostructure substrates are investigated as a function of temperature. Ge interdiffusion during annealing in highly strained Si0.5Ge0.5 on SOI is reduced by the growth of Si0.5Ge0.5 layer on biaxially tensely strained SOI. As a result, the sSi/Si0.5Ge0.5/sSOI transistors showed significantly higher hole mobilities than the Si/Si0.5Ge0.5/SOI device at low temperatures. [ABSTRACT FROM PUBLISHER]

We report on experimental and simulated results of tunneling field-effect transistors (TFETs) with a Si channel and a strained \Si1-x\Gex source. The fabricated TFET with a tensile strained Si channel shows comparably large on-currents and a subthreshold slope of 80 mV/dec at 300 K for a drain current range of three orders of magnitude. A novel TFET structure is proposed to enhance the on-currents by using a buried \Si1-x\Gex source. The overlap between the top thin Si channel and the buried SiGe source increases the tunneling area. Simulations indicate that this structure significantly improves the performance. [ABSTRACT FROM PUBLISHER]

In this letter, we demonstrate the optimization of localized silicon-on-insulator and the functionality of devices on (110) silicon substrates. The influence of several channel directions (i.e., 15 ^\circ, 30^\circ, 45^\circ, and 60^\circ away from the [001] direction) on both hole mobility and electron mobility has been investigated. Finally, the electrical characteristics of 55-nm-gate-length n-channel and p-channel metal–oxide–semiconductor transistors are presented, showing a good subthreshold behavior and confirming the interest of (110) ultrathin body/box devices for low-power applications. [ABSTRACT FROM AUTHOR]

Strain and crystalline quality of tensely strained silicon on insulator with thickness ranging from 8 to 100 nm have been evaluated by low temperature photoluminescence (PL). The strain conservation in the strained Si layers was checked by Raman spectroscopy. The PL clearly shows the emission related to the strained silicon optical band gap even for strained layers as much as seven times thicker than critical thickness (hc∼15 nm). For very thin layers (9 nm), a 21 meV blueshift is observed in the PL spectra, which corresponds to a 17 meV calculated one coming from quantum confinement in the sSi layer. [ABSTRACT FROM AUTHOR]

We have used low temperature photoluminescence measurements in order to quantify the impact of strain effect on the Si indirect band gap in 9 nm thick tensely strained silicon on insulator layers. A redshift of the transverse optical phonon excitonic recombination in the strained silicon layer was evidenced as the strain in the layer is increased. Band gap shrinkages in the Δ direction equal to 130±3 meV, 184±3 meV, and 239±3 meV were obtained for 0.87±0.03%, 1.22±0.05%, and 1.54±0.06% strain values. These measured indirect transitions are in good agreement with the calculated strained silicon indirect band gap values. [ABSTRACT FROM AUTHOR]

Four level matrices of round, 35 nm in diameter Si nanowires (NWs) are obtained thanks to a top-down approach. In particular, we report optimized H2 annealing conditions (800 to 900 °C) in order to reconstruct the plasma-etched surfaces of the suspended nanowires. The nanowire shape evolution has been studied in scanning electron microscopy, transmission electron microscopy, and atomic force microscopy. The side roughness decrease and the rounding of the NWs have been quantified. The instability of the anchors of the NWs to the contact regions has been evidenced and confirmed by surface diffusion simulations. [ABSTRACT FROM AUTHOR]

We report the fabrication and the characterization of interdigited metal-germanium on silicon metal photodetectors (metal-semiconductor-metal or MSM) for operation at both optical telecommunication wavelengths: 1.31 and 1.55 μm. Femtosecond impulse and frequency experiments have been carried out to characterize those MSM Ge photodetectors. For both wavelengths, the measured 3 dB bandwidth under 2 V bias are close to 10, 18, 20, and 35 GHz for electrode spacings equal to 2000, 1000, 700, and 500 nm, respectively. [ABSTRACT FROM AUTHOR]

We investigated Raman vibrational modes in silicon-germanium-tin layers grown epitaxially on germanium/silicon virtual substrates using reduced pressure chemical vapor deposition. Several excitation wavelengths were utilized to accurately analyze Raman shifts in ternary layers with uniform silicon and tin content in 4-19 and 2-12 at. % ranges, respectively. The excitation using a 633 nm laser was found to be optimal leading to a clear detection and an unambiguous identification of all first order modes in the alloy. The influence of both strain and composition on these modes is discussed. The strain in the layers is evaluated from Raman shifts and reciprocal space mapping data and the obtained results are discussed in the light of recent theoretical calculations. [ABSTRACT FROM AUTHOR]

B diffusion measurements are used to probe the basic nature of self-interstitial point defects in Ge. We find two distinct self-interstitial forms—a simple one with low entropy and a complex one with entropy ~30 k at the migration saddle point. The latter dominates diffusion at high temperature. We propose that its structure is similar to that of an amorphous pocket—we name it a morph. Computational modeling suggests that morphs exist in both self-interstitial and vacancylike forms, and are crucial for diffusion and defect dynamics in Ge, Si, and probably many other crystalline solids. [ABSTRACT FROM AUTHOR]

Abstract: We report on n-channel tunneling field-effect transistors (TFET) with a tensile strained Si channel and a compressively strained Si0.5Ge0.5 source. The device shows good performance with an average subthreshold swing S of 80mV/dec over a drain current range of more than 3 orders of magnitude. We observed that the on-current increases exponentially with the back gate voltage. At a back gate voltage of 8V, the on-current was enhanced by a factor of 1.6. The back gate also improves the on/off current ratio. Low temperature measurements show a slightly temperature dependent S, characteristic for a tunneling dominated device. [Copyright &y& Elsevier]

Abstract: We present the integration scheme we have optimized to fabricate very short gate length MOSFETs with 2D and 3D arrays of silicon nanowires (NW) and higk-k/metal gate stacks. Aggressively scaled NWs with sub-5nm diameters are obtained. In particular, we report a 3D matrices technology with up to 13 levels of stacked single-crystal Si nanowires that can be most interesting for memory applications. In addition, we present a careful study of the electrical properties of such devices. Our electrical measurements reveal that the NWs’ size, shape and surface treatment have a significant influence on transport properties. We identify peculiar transport and interface properties and we show that surface effects are significant for diameters equal or lower than 20nm. The use of nanowires (whatever the process) in standard sub-11nm CMOS nodes circuits will depend mainly on lithography progress in the coming years, but also on contact and metal interconnects. Ultra dense 3D arrays of Si nano-wires can however be fabricated in R&D facilities for high current, ultra-dense transistors or capacitors, sensors and NAND flash memories purposes. They are also useful for mobility and gate dielectric/nanowire interface characterization. [Copyright &y& Elsevier]

Si/Si1−yCy/Si epitaxial layers grown by reduced pressure chemical vapor deposition (RPCVD) were integrated in nMOS devices. A direct correlation between the interface state density introduced by C at the Si/SiO2 interface and the effective mobility of the electron inversion region has been demonstrated. Interface state densities can be reduced by lowering the growth and subsequent process temperatures. This way, a large amount of carbon atoms are incorporated into substitutional sites and the migration of mobile carbon atoms to the Si cap/SiO2 interface is limited. This leads to a significant improvement of the electrical performances, even for an aggressive channel stack design (ultra-thin epilayer and oxide thickness, high carbon concentrations). [Copyright &y& Elsevier]