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The missing link: Ferrocene and porphyrin monolayers are tethered on silicon surfaces with short (see picture, left) or long (right) linkers. Electron transfer to the silicon substrate is faster for monolayers with a short linker.Ferrocene and porphyrin derivatives are anchored on Si(100) surfaces through either a short two-carbon or a long 11-carbon linker. The two tether lengths are obtained by using two different grafting procedures: a single-step hydrosilylation is used for the short linker, whereas for the long linker a multistep process involving a 1,3-dipolar cycloaddition is conducted, which affords ferrocene-triazole-(CH(2))(11)-Si or Zn(porphyrin)-triazole-(CH(2))(11)-Si links to the surface. The modified surfaces are characterized by X-ray photoelectron spectroscopy and Fourier transform infrared spectroscopy. Cyclic voltammetry experiments show that the redox activity of the tethered ferrocene or porphyrin is maintained for both linker types. Microelectrode capacitor devices incorporating these modified Si(100) surfaces are designed, and their capacitance-voltage (C-V) and conductance-voltage (G-V) profiles are investigated. Capacitance and conductance peaks are observed, which indicates efficient charge transfer between the redox-active monolayers and the electrode surface. Slower electron transfer between the ferrocene or porphyrin monolayer and the electrode surface is observed for the longer linker, which suggests that by adjusting the linker length, the electrical properties of the device, such as charging and discharging kinetics and retention time, could be tuned.

We study the role that the denuded zone around Si nanocrystals obtained by chemical vapor deposition plays on the fluctuations of the dot surface coverage. In fact, the capture mechanism of the silicon adatoms in the proximity of existing dots restricts the number of possible nucleation sites, the final dot size, and the dot position, thus driving the process toward partial self-order. We numerically evaluate the relative dispersion of surface coverage for several gate areas and compare the results to the fully random case. The coverage dispersion is related to the fluctuations from bit to bit of the threshold voltage window (ΔVth) distribution of nanocrystal memories. The evaluations, compared to experimental data on ΔVth extrapolated to small gate areas, provide very favorable projections on the scalability of these memories. [ABSTRACT FROM AUTHOR]

We report the experimental realization of a compact, efficient coupler between silicon waveguides and vertical metal-insulator-silicon-metal (MISM) plasmonic waveguides. Devices were fabricated using complementary metal-oxide-silicon technology processes, with copper layers that support low-loss plasmonic modes in the MISM structures at a wavelength of 1550 nm. By implementing a short (0.5 μm) optimized metal-insulator-silicon-insulator structure inserted between the photonic and plasmonic waveguide sections, we demonstrate experimental coupling loss of 2.5 dB, despite the high optical confinement of the MISM mode and mismatch with the silicon waveguide mode. [ABSTRACT FROM AUTHOR]

In this paper, memory devices integrating a double layer of silicon nanocrystals (Si-ncs) as a trapping medium and a HfAlO-based control dielectrics are presented. We will show that the use of two stacked Si-nc layers significantly improves the memory window compared with the single Si-nc layer devices, without introducing anomalies on the charging dynamics. Then, we also evaluate the potential use of a hybrid Si-nc double-layer/SiN layer charge trapping stack. These devices show a good memory window in a Fowler–Nordheim (FN)/FN mode and a good retention (> 3 V after ten years) with small activation energy (0.35 eV up to 200 ^\circ\C), thus showing promise for future high-temperature memory applications. A model implying valence-band electron tunneling and a floating-gate-like approximation is used to explain the memory window improvement of the Si-nc double-layer memory devices. [ABSTRACT FROM AUTHOR]

In part I of this paper, we study the physicochemical structure and the electrical properties of low-pressure-chemical-vapor-deposited silicon nitride (SiN) aimed to serve as storage layers for nonvolatile memory applications. An in-depth material analysis has been carried out together with a comprehensive electrical characterization on two samples fabricated with recipes yielding rather standard SiN and Si-rich SiN. The investigation points out the impact of SiN stoichiometry and hydrogen content on the electrical characteristics of gate stacks designed in view of channel hot-electron/hole-injection program/erase (P/E) operation and tunnel P/E operation. The extensive and detailed characterization establishes a sound experimental basis for the development of the physics-based trap models proposed in the companion paper. [ABSTRACT FROM PUBLISHER]

Abstract: In this paper, silicon nanocrystals (Si-NCs) fabricated by Chemical Vapor Deposition (CVD) are successfully integrated in a 32Mb ATMEL NOR Flash memory product, processed in a 130nm technology platform. Different Si-NC deposition conditions are explored and the threshold voltage distributions of the arrays are correlated to the Si-NC size/dispersion. Main reliability characteristics, as endurance and data-retention after cycling, are studied. Results obtained on large arrays are related to single cell characteristics. The large set of data measured on arrays clearly demonstrates the robustness of our process and integration scheme. [Copyright &y& Elsevier]

In this paper, we present an overview of memory structures fabricated by our group by using silicon nanocrystals as storage nodes. These devices show promising characteristics as candidates for future deep-submicron non-volatile memories. [Copyright &y& Elsevier]

In this paper, we present a nanometer-sized floating-gate memory device, fabricated on silicon-on-insulator substrate and using silicon nanocrystals as storage nodes. Single electron charging and discharging phenomena occurring at room temperature will be demonstrated and discussed by means of simple analytical models. A deeper investigation of the impact of critical dimensions of the memory cell (i.e., active area and channel width and length) on the device operation (in particular, memory programming window), performed on a large number of samples, will be reported. Qualitative explanations for the observed experimental behaviors will be given. [ABSTRACT FROM PUBLISHER]

In this work, we present a silicon nanocrystal memory showing single electron charging/discharging phenomena at room temperature. A clear staircase behavior in the drain current characteristic, measured as a function of the gate voltage and of time, is observed, where each step corresponds to the capture/emission of one electron in a silicon dot over the channel. A simple model, which allows for the evaluation of the average charging/discharging time in a silicon dot and for the impact of a charged silicon dot over the channel, is finally proposed. [Copyright &y& Elsevier]

We present a detailed study of the growth of Si quantum dots (Si QDs) by low pressure chemical vapor deposition on alumina dielectric deposited by atomic layer deposition. The Si QDs density is very high, 10[SUP12] cm[SUP-2], for a mean diameter between 5 and 10 nm. Al[SUB2]O[SUB3]/Si QD stacks have been integrated in memory devices as granular floating gate. The devices demonstrate good charge storage and data retention characteristics. [ABSTRACT FROM AUTHOR]

In this work, we present a new memory device concept, named the multi-tunnel-junction (MTJ) memory, which uses a thin silicon nanocrystals layer embedded between two ultra-thin oxides as charge injector medium. We show that this device offers low programming voltages and fast writing/erasing characteristics. A simple characterization method, suitable for nanosecond range phenomena characterization and overcoming the limitation of the classical electrical characterization tools, has been also developed. This method allows us to characterize the dynamic behaviors of the MTJ devices. [Copyright &y& Elsevier]

Abstract: This paper presents the investigation of the electrical properties of charge-trap memories with AlN based storage layers. The memory performance and reliability are studied in details and compared with the ones of a reference device using standard Si3N4 as storage layer. An engineered charge trapping layer is also proposed, made by an AlN/Si3N4 double layer, which shows reduced program/erase voltages, combined with 106 excellent endurance and good retention (ΔV T >5V after 10years at 125°C). [Copyright &y& Elsevier]

Abstract: In this paper, we evaluate the potentiality of hafnium aluminium oxide (HfAlO) high-k materials for control dielectric application in non-volatile memories. We analyze the electrical properties (conduction and parasitic trapping) of HfAlO single layers and SiO2/HfAlO/SiO2 triple layer stacks as a function of the HfAlO thickness and Hf:Al ratio. A particular attention is given to the electrical behaviour of the samples at high temperature, up to 250°C. Experimental results obtained on silicon nanocrystal memories demonstrate the high advantage of HfAlO based control dielectrics on the memory performances for Fowler–Nordheim operation. Then an analytical model is presented, to simulate the program erase characteristics in the transient regime and at saturation, depending on the high-k control dielectric properties. A very good agreement is obtained between the experimental data and the simulation results. [Copyright &y& Elsevier]

We have realized Si nanocrystal memory cells in which the Si dots have been deposited by CVD on SiO2 and then covered by a CVD control oxide. In this paper, we report a study on the potential of these cells for dual bit storage. [Copyright &y& Elsevier]