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This article reports Si-passivated Ge nFinFETs with significantly improved GmSAT/SSSAT and positive bias temperature instability (PBTI) reliability enabled by an improved replacement metal gate (RMG) high-k last process. SiO2 dummy gate oxide (DGO) deposition on Ge fin is shown to form (Six)Ge1-xOy, which is, compared to a pure SiO2, more difficult to remove completely during the dry clean prior to the gate-stack formation. By extending the DGO removal clean, improved PBTI reliability, reduced DIT, and increased electron mobility are demonstrated. Moreover, by suppressing the Ge channel oxidation through the choice of less-oxidizing DGO or inserting an Si-cap layer prior to the DGO deposition, a greatly improved long-channel electron mobility is obtained at a scaled fin width. Finally, together with the PBTI maximum VOV of 0.13 V, the best GmSAT/SSSAT of 5.4 is achieved, which is today’s record value among the sub-100-nm-Lg n-channel Ge Fin and gate-all-around nanowire FETs. These results clearly show the importance of the pre-gate-stack channel surface preparation on the scaled Ge FinFETs to benefit from a previously optimized Si-passivated Ge gate-stack. [ABSTRACT FROM AUTHOR]

In this letter, we show that conventional III–V MOSFETs with moderate/high In content channels (In0.53Ga0.47As or In0.70Ga0.30As) at scaled nodes are incompatible with mobile SoC designs, which often operate at intermediate/high V{\mathrm {dd}} (0.7 V to $\geq 1$ V) to achieve high frequency including during burst-mode. The incompatibility is due to conventional III–V FETs having too small bandgap, and thus too high leakage when operated at the increased voltages. We show that FETs with a more optimal lower In content, In0.35Ga0.65As, have the necessary combination of larger bandgap (~Si) and sufficiently high injection velocity (~2.5 times Si) to enable both low leakage and high performance (versus Si), across the entire V{\mathrm {dd}} range of mobile SoC operation. We report for the first time the growth and characterization of ultra-thin In0.35Ga0.65As FETs with a standard 1nm EOT gate dielectric. Calibrated models show that In0.35Ga0.65As enables the highest performance at very low leakages at intermediate/high V{\mathrm {dd}} in short channel FETs. [ABSTRACT FROM PUBLISHER]

The low frequency (LF) noise has been studied in n-channel triple-gate bulk fin Field-Effect Transistors (FinFETs), which are developed for one-transistor (1T) memory applications. Significant variation in the noise spectral density has been observed, which is related to the random occurrence of excess Lorentzian components, associated with generation–recombination (GR) noise. Both gate-voltage-dependent and gate-voltage-independent GR noise peaks have been found, which are assigned to gate oxide traps or traps in the silicon fins, respectively. In addition, excess \1/f noise in weak inversion has sometimes been observed and is ascribed to surface-roughness fluctuations. Overall, the gate oxide quality seems to be the major contributor to the LF noise and not the channel and source–drain engineering investigated here. [ABSTRACT FROM PUBLISHER]

The ability to build structures with atomic precision is one of the defining features of nanotechnology. Achieving true atomic-level functionality, however, requires the ability to control the wavefunctions of individual atoms. Here, we investigate an approach that could enable just that. By collecting and analysing transport spectra of a single donor atom in the channel of a silicon FinFET, we present experimental evidence for the emergence of a new type of hybrid molecule system. Our experiments and simulations suggest that the transistor’s gate potential can be used to control the degree of hybridization of a single electron donor state between the nuclear potential of its donor atom and a nearby quantum well. Moreover, our theoretical analysis enables us to determine the species of donor (arsenic) implanted into each device as well as the degree of confinement imposed by the gate. [ABSTRACT FROM AUTHOR]

Abstract: In this work, the effective mobility in n- and p-channel FinFETS with silicon oxynitride and HfO2 gate dielectrics and TaN gate electrode is studied as a function of the inversion charge density using a split C-V technique. The mobility behavior in narrow-fin devices is compared to that in quasi-planar wide-fin devices, and the mechanisms responsible for the observed differences are discussed. The devices with HfO2 and silicon oxynitride gate dielectrics exhibit similar mobility behavior. [Copyright &y& Elsevier]

In this letter, we describe the observation of the interference of conduction paths induced by two donors in a nanoscale silicon transistor, resulting in a Fano resonance. This demonstrates the coherent exchange of electrons between two donors. In addition, the phase difference between the two conduction paths can be tuned by means of a magnetic field, in full analogy to the Aharonov–Bohm effect. One of the crucial ingredients for donor based quantum computation is phase coherent manipulation of electrons. This has not been achieved as yet, and this work presents a stepping stone. [ABSTRACT FROM AUTHOR]

The authors investigate the subthreshold behavior of triple-gate silicon field-effect transistors by low-temperature transport experiments. These three-dimensional nanoscale devices consist of a lithographically defined silicon nanowire surrounded by a gate with an active region as small as a few tens of nanometers down to 50×60×35 nm3. Conductance versus gate voltage shows Coulomb blockade oscillations with a large charging energy due to the formation of a small potential well below the gate. According to dependencies on device geometry and thermionic current analyses, the authors conclude that subthreshold channels, a few nanometers wide, appear at the nanowire edges, hence providing an experimental evidence for the corner effect. [ABSTRACT FROM AUTHOR]

In this work, we demonstrate a High-k Metal Gate (HKMG) Implant Free Quantum Well (IFQW) SiGe-pFET device used as a DRAM periphery device. Using a c:Si 0.55 Ge 0.45 channel and embedded e:Si 0.75 Ge 0.25 source/drain (S/D), a very significant source current of 625 μA/μm @ I OFF =100 pA/μm (at supply voltage V DD =−1 V) is demonstrated. The current improvement compared to DRAM compatible unstrained Silicon baseline technology (featuring HKMG) is large, and IFQW transistors are also competitive with regards to Strained Si devices. In particular, IFQW have a specific potential for Sense Amplifiers, with a demonstrated very good drive current/transconductance boost in the range of targeted gate lengths and excellent matching properties. [ABSTRACT FROM AUTHOR]

Abstract: Strained Ge channel PFETs have the potential to outperform state-of-the-art strained Si channel PFETs. This paper describes the integration aspects for strained Ge channel devices based on TCAD simulations and experimental observations. The most scalable way of introducing channel stress is by the use of Si1− x Ge x strain relaxed buffers (SRB) and/or high Ge-content source/drain stressors, selectively grown in STI. Reduction of the thermal budget, damage and Ge loss during subsequent processing are key to maintain the high strain in the Ge channel till the end of processing. [Copyright &y& Elsevier]

We report the observation of lifetime-enhanced transport (LET) based on perpendicular valleys in silicon by transport spectroscopy measurements of a two-electron system in a silicon transistor. The LET is manifested as a peculiar current step in the stability diagram due to a forbidden transition between an excited state and any of the lower energy states due to perpendicular valley (and spin) configurations, offering an additional current path. By employing a detailed temperature dependence study in combina- tion with a rate equation model, we estimate the lifetime of this particular state to exceed 48 ns. The two- electron spin-valley configurations of all relevant confined quantum states in our device were obtained by a large-scale atomistic tight-binding simulation. The LET acts as a signature of the complicated valley physics in silicon: a feature that becomes increasingly important in silicon quantum devices. [ABSTRACT FROM AUTHOR]

Abstract: Modern MOSFET devices with undoped channel have a non-trivial current distribution, which is gate voltage dependent. In our work we have studied the sub-threshold behavior of undoped triple gate MOSFETs (FinFETs) using a thermionic transport model. We have analyzed the conductance data of such devices, and from this, we have been able to determine the evolution of both the active cross-section area of the channel and the barrier height as a function of the gate voltage. The result of our experiments shows good agreement with tight binding simulations and with analytical results. This confirms the validity of the use of our thermionic approach to study transport in sub-micrometer size FinFET devices and not only in micrometer size samples specially made for characterizations. [Copyright &y& Elsevier]