Search

The admittances and subthreshold characteristics of capacitors and MOSFETs on buried and surface In0.53Ga0.47As channel flatband wafers, with a dielectric of Al2O3 deposited on In0.53Ga0.47As, are reported. The admittance characteristics of both wafers indicate the presence of defect states within the oxide, in common with a number of other oxides on In0.53Ga0.47As. The two wafers studied have not been hydrogen annealed, but do show some similar features to FGA treated oxides on n+ substrates. We discuss how the possible presence of residual hydroxyl ions in as-grown Al2O3 may explain these similarities and also account for many of the changes in the properties of FGA treated n+ samples. The issues around the comparison of subthreshold swing (SS) results and the impact of transistor design parameters on the energy portion of the defect state distribution affecting efficient device switching are discussed. The interface state model is applied to low source-drain voltage SS data to extract an effective interface state density (Dit) that includes interface and oxide traps. The logarithmic gate voltage sweep rate dependence of the SS Dit is used to extract an oxide trap density (Dot) and a simple method is used to estimate the Fermi level position within the band gap, Et. The Al2O3 Dit(Et) and Dot(Et) distributions are found to be similar to each other and to the results of our analysis of Gd0.25Ga0.15O0.6/Ga2O3 and HfO2/Al2O3 on In0.53Ga0.47As, adding weight to the suggestion of there being a common defect state distribution and perhaps a common cause of defects states for a number of oxides on In0.53Ga0.47As. [ABSTRACT FROM AUTHOR]

The admittances and subthreshold characteristics of capacitors and MOSFETs on buried InxGa1-xAs channel wafers with a dielectric stack of Gd0.25Ga0.15O0.6/Ga2O3 deposited on GaAs and In0.53Ga0.47As are reported. Both the GaAs and InGaAs interface samples show admittance characteristics indicative of the presence of defect states within the oxide, in agreement with previously reported data from the same oxides on n+ substrates. The interface state model is applied to the admittance data to extract an apparent interface state density (Dit) that includes interface and oxide states. The Dit profiles are very different and have pronounced effects on the device performance. The device subthreshold swings (SS) at low source-drain voltages are also used to extract an apparent Dit. A simple method is used to estimate the Fermi-level position within the bandgap (Et) at threshold, and the resulting Dit(Et) are found to be in good agreement with the admittance data. The importance of proper interpretation of SS and Dit in general and in GaAs interface devices in particular is emphasized. A model that accounts for the logarithmic sweep rate dependence of the extracted Dit due to the presence of oxide states is reported and used to estimate their density from SS measurements. The implications of the band parameters of an oxide with defect states within it for the comparison of different oxides on the same substrate and the issues around the comparison of results in general are discussed. [ABSTRACT FROM AUTHOR]

We show the experimental realization of a 108-GHz planar Gunn diode structure fabricated in GaAs/AlGaAs. There is a considerable interest in such devices since they lend themselves to integration into millimeter-wave and terahertz integrated circuits. The material used was grown by molecular beam epitaxy, and devices were made using electron beam lithography. Since the frequency of oscillation is defined by the lithographically controlled anode—cathode distance, the technology shows great promise in fabricating single chip terahertz sources. [ABSTRACT FROM AUTHOR]

GaAs-based transistors with the highest ƒT and lowest noise figure reported to date are presented in this letter. A 50-nm T-gate In0.52Al0.48As/In0.53Ga0.47As Metamorphic high-electron mobility transistors (mHEMTs) on a GaAs substrate show ƒT of 440 GHz, fmax of 400 GHz, a minimum noise figure of 0.7 dB and an associated gain of 13 dB at 26 GHz, the latter at a drain current of 185 mA/mm and gm of 950 mS/mm. In addition, a noise figure of below 1.2 dB with 10.5 dB or higher associated gain at 26 GHz was demonstrated for drain currents in the range 40 to 470 mA/mm at a drain bias of 0.8 V. These devices are ideal for low noise and medium power applications at millimeter-wave frequencies. [ABSTRACT FROM AUTHOR]

The 300-K admittance characteristics of n+ In0.53Ga0.47As MOS capacitors with a dielectric stack of Gd0.25Ga0.15O0.6/Ga2O3 in as-grown condition are examined in detail and compared to an oxide trap model that we previously introduced. The model explains many of the observed features not contained in the interface state model. By fitting the model to experimental data, we extract a distribution of defect states in space and energy within the oxide and at the oxide/semiconductor interface separately. Oxide states are the dominant defects over a wide range of energy. The defect state densities are not subject to the usual resolution limits of conventional analyses. Using this approach, it is possible to characterize relatively rapidly a wide range of energies at a single temperature without the need for reaching the low or high limits of frequency. The implications for the conventional interface state density (Dit) extraction techniques are explored. It is shown how oxide states can affect the extraction of sample parameters, particularly the insulator capacitance, and can result in a range of extracted Dit values. We believe these contribute to the wide range of Dit reported in the literature from similar admittance characteristics of a number of oxides on In0.53Ga0.47As. [ABSTRACT FROM AUTHOR]

The impact of the stress in room temperature inductively coupled plasma chemical vapour deposited (ICP-CVD) SiNx surface passivation layers on off-state drain (IDS-off) and gate leakage currents (IGS) in AlGaN/GaN high electron mobility transistors (HEMTs) is reported. IDS-off and IGS in 2 μm gate length devices were reduced by up to four orders of magnitude to ~10 pA/mm using a compressively stressed bilayer SiNx passivation scheme. In addition, Ion/Ioff of ~1011 and subthreshold slope of 68 mV/dec were obtained using this strain engineered surface passivation approach. [ABSTRACT FROM AUTHOR]

This article describes a process flow which has enabled the first demonstration of functional, fully self-aligned, 40 nm gate length replacement gate enhancement mode GaAs metal-oxide-semiconductor field-effect transistors (MOSFETs) with GaxGdyOz as high-κ dielectric, Pt/Au metal gate stack, and SiN sidewall spacers. The flow uses blanket metal and dielectric deposition and low damage dry etch modules. As a consequence, no critical dimension lift-off processes are required. As a gate replacement approach has been developed, the process is suitable for easily incorporating different gate metals, opening the way to work function engineering to control threshold voltage and so is a significant step forward to the demonstration of high performance 'siliconlike' III-V MOSFETs. [ABSTRACT FROM AUTHOR]