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The production of integrated circuits (IC) is key to the development of the world economy. The system of intellectual property offers different means of protection for the products of the IC industry. Those are mainly the patents for inventions, registration of topologies of ICs, trade secrets, copyright. The economics of the IC industry in the late 20th century moves different processes in different regions of the world. This economic reality provides an opportunity for those companies to invest heavily in R&D, to create valuable intellectual property and to develop a competitive advantage. The historical development of integrated circuit manufacturing, the development of the main companies involved in the sector and the existing supply chains, raise a number of questions that are related to the concentration of innovation and intellectual property, the potential problems for global supply and economic development, as well as the steps towards overcoming those problems. [ABSTRACT FROM AUTHOR]

This study evaluates the accuracy of two alternative models for the kill rate of different visual defects and the yield estimation by using large amount of practical inspection data (140 6-inch wafers containing 70 560 dies) in semiconductor manufacturing. One model assumed that the visual defects are randomly distributed on a wafer die; another model considered that clustering visual defects may occur on a wafer die. The results show that two models are both capable of predicting the yield precisely. The results also suggest that the model assuming clustering visual defects on a die is more accurate based on the analysis of Taguchi's signal-to-noise (SN) ratio. The same practices can be implemented with other types of wafer such as 8 inch and 12 inch. Precise prediction for the kill rate of different types of visual defects and the yield in the long supply of semiconductor industry is critical since the requirement of material and the reserved capacity can be largely reduced. [ABSTRACT FROM AUTHOR]

Inspection plays an important role in the semiconductor industry. In this paper, we focus on the inspection task after wire bonding in packaging. The purpose of wire bonding (W/B) is to connect the bond pads with the lead fingers. Two major types of defects are (1) bonding line missing and (2) bonding line breakage. The numbers of bonding lines and bonding balls are used as the features for defect classification. The proposed method consists of image preprocessing, orientation determination, connection detection, bonding line detection, bonding ball detection, and defect classification. The proposed method is simple and fast. The experimental results show that the proposed method can detect the defects effectively. [ABSTRACT FROM AUTHOR]

Taking issue with the classical theory of path dependence, we capture the active agency involved in collective efforts aimed at extending a current technological path and, in parallel, at creating a new path in the field of leading-edge international semiconductor manufacturing. We apply structuration theory in order to analyse the practices of path constitution that traditional evolutionary views of lock-in and irreversibility in path processes have neglected. Drawing on 96 interviews since 2003 and extensive secondary sources in the field of semiconductor manufacturing in Europe, Japan and the United States, we perform a qualitative, longitudinal and multi-level case analysis; in this analysis we trace, in particular, the strategic development of a path-extending technological option besides a potentially path-breaking new generation of lithography for chip manufacturing systems. Our results provide deep insights into the collective and collaborative dimension of organizing R&D in processes of technology development. Thereby, we contribute to a theory of technological paths that considers collective embedded agency and takes into account interorganizational forms for an understanding of the innovation dynamics in science-based industries such as semiconductor manufacturing. [ABSTRACT FROM PUBLISHER]

Hsinchu Science Park (HSP) is a high-tech cluster where semiconductor industry plays a decisive role in Taiwan's economy as well as global supply chains. Semiconductor industry is capital intensive, in which capacity utilization significantly affects the capital effectiveness and profitability of semiconductor companies. Thus, demand forecasting provides critical input to support strategic decisions of capacity planning and the associated capital expenditure that require long lead-time. This study aims to predict the sales of semiconductor industry in HSP as a reference signal for supporting the decisions of individual companies and the government to maintain a healthy ecosystem. Empirical data of semiconductor industry in HSP from 1983 to 2010 was collected and analyzed. Furthermore, this study incorporated historical events to adjust the prediction. The results have shown practical viability of this research to support companies to improve the demand forecast as well as to make strategic decisions for semiconductor ecosystem as a whole. [ABSTRACT FROM AUTHOR]

Lapping is a critical step of wafer manufacture. Some wafer quality characteristics, such as total thickness variation (TTV) and thickness, are largely determined by lapping. A lapping process has a collection of factors. In practice, some factors are seldom changed once been fixed; while some others are tuned online continuously. We classify the factors into online factors, offline factors, uncontrollable factors, and noises. In this work, we analyze the physical mechanism of lapping factors then conduct experiments to study the lapping process. Offline factors are optimized via the robust parameter design (RPD); online factors are optimized via the double exponential weighted moving average Run-to-Run control. Verifying experiments proved that the RPD and RtR control can help to improve the TTV and the batch-to-batch thickness variation, respectively. [ABSTRACT FROM AUTHOR]

This study presents operational methods which improves tools control plan. To face challenges linked with quality, cost, cycle time, development and environment, semiconductors industries set classical process control methods. However many interactions between product-processes and tools are not exploited in practice for fine tuning controls operations and detecting premises of non conformities occurrences. [ABSTRACT FROM AUTHOR]

In the modern world, computing is essential in all aspects of manufacturing activity. Computers have brought to life terms like artificial intelligence, and have played a critical role in reinvention of manufacturing industry. In continuing quest to decrease the interval time between conceptualization of a product, information technology has been fused with manufacturing practice. This paper describes the use of an expert system shell to develop a knowledge-based system (KBS) for an automatic wire bonding machine in the hitech semiconductor industry. The main aim of the KBS is to diagnose and solve the problem of an automatic wire bond machine. The diagnosis method was based on maintenance requirements such as measurement, machine, and material. In the semiconductor industry, production equipment and machine have depended heavily on the use of human expertise for maintenance and it is costly. Without a knowledge-based system, their experience will be lost when they are unavailable or resign. With the developed KBS, the diagnosis process for the automatic wire bond machine is standardized and accuracy will be increased compared to the conventional way. Therefore, the quality of products that are produced will improve. The constrain values for KBS are based on the design data and experience of the engineer. The KBS is to improve bonding quality by reducing the production yield loss. [ABSTRACT FROM AUTHOR]

Fabrication technologies for the semiconductor industry have enabled ever-smaller devices but now face fundamental limits in creating nanoscale products. Self-assembly has recently emerged as a promising alternative fabrication technology for functional nanoscale systems. Such processes can be made parallel and are capable of producing three-dimensional structures with 10 nm precision. This paper reviews recent developments, applications and challenges of self-assembly methods for the semiconductor industry. Although a fully self-assembled nanoscale system has not yet been commercially achieved, the work reviewed and discussed here demonstrates a solid scientific foundation in pursuing this goal. [ABSTRACT FROM AUTHOR]

The article discusses the characteristics of an addressable array technology for systematic yield monitoring at 65 nanometer (nm). Random yield, once dominated by random defects, is increasingly dominated by systematic issues at 65nm and below. However, while the semiconductor industry has an established method for monitoring and improving random defect-limited yields, a similar methodology for addressing systematic yield issues is not in widespread use.

Realizing environmentally benign silicon-wafer cleaning has become one of the most important topics in the semiconductor industry. We have developed an ultra-diluted HF/nitrogen-gas jet spray procedure for single-wafer spin cleaning, which can efficiently remove not only particulate but also metallic contaminants in 20 s from both silicon and silicon-dioxide surfaces without causing damage to fragile 45-nm wide polycrystalline-silicon gate structures. The use of a very low HF concentration makes the silicon and oxide losses negligible, below 0.003 and 0.03 nm, respectively. This simple, single-step, single-wafer Spin CLeaning with use of Ultra-Diluted HF/nitrogen jet spray (SCLUD) drastically reduces the chemical and water consumption as well as electrical energy per wafer due to the short spraying time with the ultra-diluted HF at room temperature. HF wastewater, the only effluent of this cleaning, is recycled by forming CaF2, which can be a raw material for HF or Portland cement. This cleaning, therefore, meets the requirements with respect to the environmental control. [ABSTRACT FROM AUTHOR]

China's IC industry is evolving rapidly, driven by seemingly insatiable demand. There is concern, however, whether China can overcome other countries' reluctance to do business and build a significant semiconductor industry. In addition, China's semiconductor ambitions are thwarted by other issues, such as its evolving attitudes to joint ventures, and the international controls on access to the most advanced technology. These concerns also affect where large chip companies choose to make their manufacturing investments. [ABSTRACT FROM AUTHOR]

Abstract: A challenge for semiconductor industry is to reach low permittivity required by ITRS (k <2.4) integrating porous interconnect insulator for the sub-65nm technology nodes keeping high mechanical performances as close as possible to dense a-SiOC:H material (H =[1.5–1.8GPa], E =[8–11GPa]). Thus, UV post-deposition treatments were carried out on single PECVD non-porogen porous methylsilsesquioxane (MSQ) films, proposed for 45nm node and below. UV curing is able to enhance stiffness revealing a 50% increase in reduced modulus without degrading k-value. The paper reveals that UV efficiency is actually limited by a top SiO2-like dense layer. Indeed, without this capping, 8min of UV cure exposure enable to reach a 300% increase in reduced modulus and a 600% increase in hardness maintaining k at 2.27. Finally, UV curing on 300nm porous MSQ film stacks is investigated. The study correlates the limited UV effect by the capping layer and demonstrates that the best stack mechanical properties improvement with limited k degradation is achieved performing UV curing on each layer combined with interfacial hydrogen plasma treatment. [Copyright &y& Elsevier]

One of the buzzwords currently in use across the semiconductor industry is “three-dimensional integration,” which sounds as though it is a new, beefed-up form of miniaturization. Indeed, 3-D integration does involve further miniaturization, generally by including the z-axis along with the x- and y-axes. But the term also has a deeper and more important connotation: higher speed through the replacement of long wires with shorter pathways. [Copyright &y& Elsevier]

This paper attempts to propose a conceptual framework that explains the relationship between knowledge co-evolutionary mechanisms and innovation development. Combining strategic management, innovation management and organisational ecology theories, we try to review and explain the development of product innovation or process innovation through organisational knowledge interactions between two or more firms. We focus on the knowledge co-evolutionary cycle and suggest two sub-mechanisms that should be considered: the knowledge micro-evolutionary mechanism (intra-organisation) and the knowledge macro-evolutionary mechanism (inter-organisation). We illustrate this framework by discussing the case study of a leading semiconductor firm, United Microelectronics Corp., (UMC) in Taiwan. Combining its strategic partners' fundamental research knowledge systems, the vendor's IP knowledge systems, the customer's IC design knowledge systems, and UMC's process innovation knowledge system, UMC not only enhances the process innovation capability for itself but also accelerates its customers' product innovation performance to market. Through partnership in the co-evolutionary ecosystem, UMC generates and accumulates dynamic capabilities. [ABSTRACT FROM AUTHOR]

Overall equipment effectiveness (OEE) is a metric that has been accepted completely in the semiconductor industry. OEE is simple and clear, and standards and guidelines have been developed. Nonetheless, literature indicates imperfections in applying 011 with regard to time base and rate efficiency. As literature lacks a basic framework for OEE, effectiveness has been approached systematically that resulted in it new equipment effectiveness E. The main difference between 011 and E concerns the choice of the time base. 011 does include equipment-independent conditions, such as lack of input items. This condition is not caused by the equipment but by the environment of the equipment. E has been defined to get a performance measure that is related to equipment-dependent states only, viz, effective state consisting of productive state, scheduled down state, and unscheduled down state. Because of the stand-alone condition, the equipment effectiveness expresses the (equipment) internal losses, while utilization expresses the external losses. By using E, equipment can be compared and improved. It can be concluded that the advantage of E over 011 is that real equipment effectiveness is measured as the influence of utilization (equipment-independent conditions) is eliminated. [ABSTRACT FROM AUTHOR]

Biofilter technology is a cost-effective technique with an excellent efficiency for volatile organic compound (VOC) treatment. It is an attractive alternative to conventional air pollution abatement technologies. In this project, a combination of a Biosrubber and a Bioffiter (called Biofilter System) was tested with VOC-laden exhaust air from a semiconductor fab. This Bioffiter System meets all requirements of German and European law and protects the environment. The results of this project demonstrate that it is possible to establish this innovative and emerging technology in the semiconductor industry. [ABSTRACT FROM AUTHOR]

The article presents information on X-ray microscopy. In the last decade advances in nanostructuring technology led to rapid progress of the diffractive x-ray optics quality, e.g., Fresnel zone plates which became the key elements for high resolution and energy resolving x-ray imaging techniques performed at synchrotron sources. X-ray microscopy is a powerful method which can investigate whole cells in their aqueous environment avoiding potential artifacts introduced by the dehydration or fixation necessary with other methods. X-ray microscopy can give 3-D structural information of whole cells. In addition, its potential as a non-destructive technique for physical failure analysis and as a new tool for investigations of electromigration mechanism in semiconductor industry was demonstrated.

Discusses the importance of ion implantation in silicon technology to integrated-circuit (IC) manufacturing. Features of ion implantation technique; Details for dose and energy requirement of major implantation applications; Need for IC designers to reduce implanter-induced contamination; Share of major IC manufacturers of ion implantation equipment in the market.

The article focuses on the reconsideration of the use of germanium in the integrated circuit industry instead of silicon. It is stated that the limitations of silicon are becoming more evident. Silicon's electrical properties and carrier mobility are found to be merely average next to germanium and other alternatives. An obstacle to germanium's re-introduction is the lack of passivating native oxide.

Focuses on the growth of the integrated circuit industries in China. Paradigm of low-cost systems manufacturing fueled by foreign capital; Opportunities on the imbalance between consumption and production of semiconductors; Balance development in INC and electronic system industries.

Reports on the shift in the dynamics between the large silicon foundry base and leading integrated device manufacturers in Taiwan. Efforts of the pure-play foundry giants to compete with leaders in shipping advanced integrated circuit technologies; Technology gap between process generations; Acceleration of the research and development efforts of the foundries to meet the demands for more complex integrated circuits.

A first reported method of measuring coupling capacitance (both inter- and intralevel) between any two lines in the presence of any other lines in a very large scale integration (VLSI) chip, to an accuracy of atto-farad range, is discussed. The setup simply requires de current measurement and the method has been tested for 180 nm and 130 nm technologies. Furthermore, the method can be easily implemented for on-wafer e-test measurement in a fab, to study die-to-die and wafer-to-wafer coupling capacitance variation due to manufacturing process variation. In one process, it has been observed that the coupling capacitance between parallel lines could vary as much as 17%. Index Terms—Capacitance modeling, current measurement, on-chip capacitance, very large-scale integration (VLSI) interconnect. [ABSTRACT FROM AUTHOR]