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5,445 results on '"Integrated circuits -- Intellectual property"'

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1. From 'Made in China' to 'Created in China': Intellectual Property Rights in the People's Republic of China

3. Researchers Submit Patent Application, 'Field-Aware Metal Fills For Integrated Circuit Passive Components', for Approval (USPTO 20250012893)

4. Patent Issued for Clock generating circuit and clock distribution network and semiconductor apparatus including the clock generating circuit (USPTO 12189416)

5. Researchers Submit Patent Application, 'Storage Devices That Support Sub-Block Reclaim Operations Therein Upon Detection Of Uncorrectable Errors', for Approval (USPTO 20250014670)

6. Researchers Submit Patent Application, 'Integrated Power Device With Energy Harvesting Gate Driver', for Approval (USPTO 20250015707)

7. Researchers Submit Patent Application, 'High-Voltage Gate Driver Integrated Circuit Using Galvanic Isolator', for Approval (USPTO 20250015077)

8. Patent Application Titled 'Semiconductor Device Structure Including Fuse Structure Embedded In Substrate' Published Online (USPTO 20250017002)

9. 'Nonvolatile Memory Devices And Memory Packages Including The Same' in Patent Application Approval Process (USPTO 20250014645)

10. 'Integrated Circuit Memory Devices Having Highly Integrated Memory Cells Therein With Enhanced Landing Pad Structures' in Patent Application Approval Process (USPTO 20250016981)

11. 'Integrated Circuit Memory Devices Having Enhanced Memory Cell Layouts' in Patent Application Approval Process (USPTO 20250016991)

12. Researchers Submit Patent Application, 'Clock Doubler, A Clock Generating Device And A Semiconductor System Using The Same', for Approval (USPTO 20250015786)

13. Patent Issued for Transmitting a response with a request and state information about the request (USPTO 12189544)

14. Patent Application Titled 'Integrated Inductor Including Magnetic Layer' Published Online (USPTO 20250006631)

15. Researchers Submit Patent Application, 'Programmable Delay Testing Circuit', for Approval (USPTO 20250004048)

17. Patent Application Titled 'Power Stage Safety And Latch-Up Prevention In Multi-Phase Dc-Dc Converter By Ensuring Safe Pwm Sequencing' Published Online (USPTO 20250007390)

19. 'Phase Aligning Multiple Channel Dividers Without Stopping Vco Root Clock' in Patent Application Approval Process (USPTO 20250007522)

20. 'Inter-Integrated Circuit (I²c) Interface With Device Address Used For Device Configuration' in Patent Application Approval Process (USPTO 20250004977)

21. 'Adaptive Refresh Rate Generator' in Patent Application Approval Process (USPTO 20250006245)

22. Patent Issued for Manipulation zone for qubits in quantum dots (USPTO 12182041)

23. Patent Application Titled 'Timing Constraint Auto-Creation For Integrated Circuit Testing' Published Online (USPTO 20250005244)

24. Researchers Submit Patent Application, 'Semiconductor Packages With Multiple Types Of Conductive Components', for Approval (USPTO 20250006585)

25. Researchers Submit Patent Application, 'Double-Sided Polishing Of Semiconductor Wafers With Dynamic Control', for Approval (USPTO 20250001546)

26. Researchers Submit Patent Application, 'Double-Sided Integrated Circuit With Damage Sensor', for Approval (USPTO 20250006629)

27. Patent Application Titled 'Semiconductor Packages With Multiple Types Of Conductive Components' Published Online (USPTO 20250006685)

29. Patent Application Titled 'Semiconductor Package' Published Online (USPTO 20250006625)

30. Patent Application Titled 'Electrostatic Discharge (Esd) Protection Circuit Including An Avalanche Semiconductor Controlled Rectifier (Scr) With Parallel Connected Static Trigger Control Circuit (Tcc)' Published Online (USPTO 20250006724)

32. 'Semiconductor Device' in Patent Application Approval Process (USPTO 20250006604)

33. 'Double-Sided Integrated Circuit With Electrostatic Guard Ring' in Patent Application Approval Process (USPTO 20250006663)

35. Researchers Submit Patent Application, 'Machine-Readable Code In Integrated Circuit', for Approval (USPTO 20250006650)

36. Patent Issued for Signal processing in bridge chip in semiconductor storage device and memory system (USPTO 12182411)

37. Patent Issued for Multi-purpose IO pads/bumps on semiconductor chips to maximize chip-to-chip data connectivity (USPTO 12182051)

39. Patent Issued for Interface circuit and information processing system for detecting a connection state based on a notification received through a hot plug detect line (USPTO 12184589)

40. Patent Issued for Display panel, integrated chip, and display apparatus (USPTO 12183238)

41. Patent Issued for Application processors and electronic devices including the same (USPTO 12183388)

42. 'Quantum Device' in Patent Application Approval Process (USPTO 20250005416)

45. Researchers Submit Patent Application, 'Integrated Circuit Device Including Peripheral Circuit And Cell Array Structures, And Electronic System Including Same', for Approval (USPTO 20240429187)

47. Patent Application Titled 'Optical Memory Module And Optical Computing System Including The Same' Published Online (USPTO 20240427715)

49. 'Transformer-Based Distributed Multicore Oscillator And Integrated Circuit And Terminal Thereof' in Patent Application Approval Process (USPTO 20240429863)

50. Patent Application Titled 'Hierarchical Power Estimation And Throttling In A Processor-Based System In An Integrated Circuit (Ic) Chip' Published Online (USPTO 20240427410)

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