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Low-frequency noise (LFN) measurements are largely used for interface quality characterization in MOSFETs. In this work, a detailed investigation of LFN technique applied to pseudo-MOSFETs in bare silicon-on-insulator (SOI) substrates is provided. A physical model capable to describe the experimental results is proposed and validated using different die areas and inter-probe distances. The effective silicon area contributing to the noise signal, the impact of defects induced by probes and the possibility to extract interface trap density are addressed. [ABSTRACT FROM AUTHOR]

• Double gate structures for channel material and gate stack characterization. • Easy and simple techniques based on the pseudo-MSOFET configuration. • Fast fabrication loop of double gate MOSFET. • Test structures for parameter extraction. • Double-gate pseudo-MOSFET for rapid material characterization. Pseudo-MOSFET delivers a fast, simple and reliable way of characterizing electrically SOI substrates without the need of full CMOS fabrication. However, the information refers to the back interface. Here, to probe the front interface, we extend the concept to a double-gate pseudo-MOSFET. The structure provides a pertinent test vehicle for the characterization and development of transistors channel and gate stack materials in a configuration similar to fully fabricated transistors. We show that the devices with undoped terminals need specialized modeling development to describe the double gate effect. Devices with doped terminals are immediately exploitable for parameter extraction. [ABSTRACT FROM AUTHOR]

The feasibility of split C-V measurements for direct evaluation of carrier mobility in as-fabricated silicon-on-insulator wafers has been demonstrated. Here, we complete this letter by modeling the frequency dependence of capacitance curves. The peculiarity of the pseudo-MOSFET (Ψ-MOSFET) configuration with respect to standard MOSFET comes from the possible distribution of mobile carriers beyond the source and drain contacts. This implies a variation in charge spreading and capacitance with frequency that we address with an RC low-pass filter model. Experimental C-V measurements with one and two probes were used for validation of the proposed model. [ABSTRACT FROM AUTHOR]

Abstract: Low-frequency noise (LFN) is generated by interactions of the channel carriers with interface traps and oxide charges. Therefore, noise measurements on silicon on insulator (SOI) wafers can give important information about the state of the interfaces and their defect density. Here, noise measurements at wafer level were performed using the pseudo-MOSFET (Ψ-MOSFET) configuration. 1/f noise behavior in relatively thick and ultra-thin SOI layers is obtained. No probe pressure dependence of the noise is observed. The influence of wafer surface states is showed and further confirmed in passivated SOI samples. Origins of noise generation are discussed. [Copyright &y& Elsevier]

Back-gated InGaAs-on-insulator lateral N + NN + MOSFETs are successfully fabricated by direct wafer bonding and selective epitaxial regrowth. These devices were characterized using a revisited pseudo-MOSFET configuration. Two different transport mechanisms are evidenced: volume conduction in the undepleted region of the film and surface conduction at the interface between InGaAs and buried insulator. We propose extraction techniques for the volume mobility and interface mobility. The impact of film thickness, channel width, and length is evaluated. Additional measurements reveal the variation of the transistor parameters at low temperature and under externally applied uniaxial tensile strain. [ABSTRACT FROM AUTHOR]

This paper discusses the impact of both contact and channel resistance on capacitance and conductance characteristics measured with pseudo-MOSFET method by analyzing the impedance and admittance in frequency domain. We clarify the mechanisms affecting the ac response of pseudo-MOSFET structure for SOI wafer with thin SOI film by using simple series and parallel circuits composed of resistance and capacitance. Our measurement results show the gate bias range where the influence of the contact resistance becomes dominant in measurements with single and multiple probes. The degradation of the capacitance measured at high frequency is also analyzed by constructing an equivalent circuit, which detach the influence of the contact and channel resistances quantitatively. The necessity to carefully account for the influence of the contact resistance in pseudo-MOS method is clarified. [ABSTRACT FROM AUTHOR]