Search

Low‐temperature polycrystalline silicon (LTPS) thin‐film transistor devices can be used as core components of pixel driving circuits for active matrix organic light‐emitting displays （AMOLED）. Poly silicon (P‐Si) film and device performance directly affects the display effect. This paper investigates polysilicon grain boundary reduction for LTPS devices on PI substrates, exploring the effects of grain boundary reduction on LTPS devices and image sticking. Reduction of polysilicon grain boundaries through optimization of a‐Si deposition process, a‐Si two‐step deposition and excimer laser annealing (ELA) doublescan process, ELA double‐scan process reduces grain boundaries by 67 %. We prepared LTPS devices with thinner gate interlayers (GI) based on P‐Si grain boundary reduction, LTPS devices with positive threshold voltage bias and increased mobility, AMOLED displays with thinner GI can have 23% better image sticking. [ABSTRACT FROM AUTHOR]

This paper reports the development and integration of (Poly‐Si/Air)n Distributed BRAGG Reflectors (DBR) in a MOEMS Fabry‐Pérot‐Interferometer (FPI) concept. The realized reflectors constitute a promising and resource‐efficient alternative to complex Ion‐Assisted Deposition based DBRs while maintaining their advantages. Compared to state of the art MOEMS FPIs the (Poly‐Si/Air)n DBRs can be integrated into two moveable reflector carriers based on two individually fabricated wafers which are bonded. The (Poly‐Si/Air)n DBRs are investigated as (HL) and (HL)2 reflector stacks showing a reflectance above 91% within the wavelength range of 2.8–5.7 μm. © 2023 The Authors. IEEJ Transactions on Electrical and Electronic Engineering published by Institute of Electrical Engineer of Japan and Wiley Periodicals LLC. [ABSTRACT FROM AUTHOR]

In the present work, Automat FOR Simulation of HETerostructures (AFORS-HET v2.5) simulation software was used to investigate the performance of p-type tunnel oxide passivated contact (p-TOPCon) solar cells. Firstly, the influence of SiOx thickness on the device performance at different rear surface recombination velocity (SRV) was studied thoroughly; the same was followed by the incorporation of pinholes at different oxide thickness to realize the impact of pinhole density (Dph) on the charge carrier transport mechanisms through the ultra-thin SiOx tunneling layer. Next, the doping concentration of p+ poly-Si layer was varied to reveal its impact on the device output and it was noticed that presence of pinholes might facilitate the transformation of charge carriers through ultra-thin SiOx tunneling layer even at relatively lower poly-Si doping concentration. Furthermore, the consequence of wafer thickness at different wafer lifetime and at different front SRV on the performance of p-TOPCon solar cells was studied thoroughly. A relative analysis on the device performance in between the conventional TOPCon and TOPCore (TOPCon with p-type wafer and n+ poly-Si as rear emitter) solar cell architecture based onto p-type base substrate was conducted. Eventually, an in-depth comparative analysis of the thermal stability among TOPCon, TOPCore and baseline BSF (back surface field) solar cells was carried out for both thicker and thinner wafers. The role of pinholes on the thermal stability of the devices was also pinpointed and it was yielded that our optimized device parameters might enable the best possible thermal stability along with higher power output. [ABSTRACT FROM AUTHOR]

Metallization of polycrystalline‐silicon/silicon oxide (poly‐Si/SiOx) passivating contacts with fire‐through silver paste is a crucial process for implementation of passivating contacts in industrial manufacturing of solar cells. For a microscopic understanding of the metallization process, the contact forming interface between the Ag crystallites and the poly‐Si layer is investigated with high‐resolution transmission electron microscopy. For this purpose, multilayer atmospheric pressure chemical vapor deposition poly‐Si samples with a SiOx layer between the individual poly‐Si layers are fabricated, screen printed with a lead‐free Ag paste, and contact fired. Electron micrographs show that in this process the etching of the paste and the subsequent Ag crystallite formation is stopped by this interface with the SiOx layer. Additionally, energy‐dispersive X‐Ray mapping reveals the presence of an oxide layer around the Ag crystallites. This finding differs significantly from well‐investigated classical cell concepts with contact formation on diffused crystalline silicon. Moreover, an analysis of the Ag crystallite orientation in correlation to the neighboring Si crystallite orientation indicates no direct relationship. Finally, it is shown that the use of this multilayer approach is favorable for integration into a solar cell concept leading to a higher passivation quality at the metallized area and lower contact resistivity. [ABSTRACT FROM AUTHOR]

Passivated emitter and rear contact (PERC) on p‐type mono silicon has a roadmap for achieving >24% efficiency. The decrease of the full‐area rear metal contact to partial rear contact (<10%) accounts for the majority of the increase in efficiency of PERC solar cells over Al‐BSF solar cellswhich reached its maximum efficiency around 19.5%. P‐type tunnel oxide passivated contacts (TOPCon) solar cells have achieved further improvement in efficiency ≥25% by completely removing the partial rear metal contact and introducing a thin tunneling oxide layer at the rear. Thus passivating the partial rear and front metal contacts using SiOx/poly‐Si tunnelling layer stacks and an AlOx/SiNx stack on the entire back surface to passivate the remaining areas might lead to further advancements in PERC solar cells. Therefore, by integrating TOPCon and PERC architectures, as originally proposed by Fraunhofer lab, a modified design known as TOPerc solar cell has been studied in depth in this paper. Using 3D Sentaurus TCAD simulation software, a thorough numerical simulation of a p‐TOPerc solar cell has been performed. It is shown that efficiency of 25.2% and 26.0% is obtained for a p‐type wafer of bulk lifetime of 400 μs and 5.0 ms, respectively. [ABSTRACT FROM AUTHOR]

This article presents a multiple trapping and release model (MTR) based technology computer-aided design (TCAD) investigation of low-temperature poly-silicon (LTPS) thin film transistors (TFTs). To consider the role of localized and delocalized states in carrier transport, the proposed simulation framework considers the inclusion of interface traps in the TFTs, which effectively represent the defects present in the poly-Si/ gate dielectric interface and the grain boundaries (GBs). The device performance is reported for Gaussian and double-exponential deep and tail state trap distribution of acceptor-like and donor-like interface traps by varying the trap-distribution parameters such as peak trap concentration (N0) and location of peak (Emid). Electrical parameters such as on and off-state currents, threshold voltage and subthreshold swing are reported for the parametric investigation. As the trap distribution penetrates deeper into the bandgap from the band edges, the performance deteriorates, as evident from the increase in subthreshold swing and threshold voltage. The impact and results of the analyses infer that the proposed framework can be applied to predict and model LTPS TFTs through a design-and-simulation approach as proposed in the article. [ABSTRACT FROM AUTHOR]

This work reports an ingenious hybrid thin-film transistor (TFT) process platform that allows monolithic integration of poly-Si and oxide-semiconductor (OS) TFT-based circuits using three-mask processes. The effectiveness of the proposed fabrication approach is demonstrated by a hybrid poly-Si/indium-gallium-zinc oxide (IGZO) TFT cell, in which source/drain (S/D) contacts of poly-Si TFTs were simultaneously formed during the fabrication of IGZO TFTs. A thin Ti layer is intentionally inserted between poly-Si and IGZO channels in order to improve the contact resistivity of the $n^{+}$ poly-Si/IGZO structure. The integrated poly-Si/IGZO TFT cells exhibit sharp transition slopes (~ −35 mV/dec) in the transfer curves. With this feature, the sensitivity of the proposed hybrid TFT cells is greatly improved in comparison to individual IGZO TFTs, as evidenced in the detection measurements of NO2 gas.

• Optimisation for poly-Si passivating contacts prepared by sputtering and ex-situ diffusion. • The difference in performance between POCl 3 diffusion and spin-on doping is due tocrystallinity and diffusion mechanism. • With POCl 3 diffusion: an i V oc of ∼720 mV, a J 0 of 2.6 fA/cm2 after a hydrogenation, and a contact resistivity ρ c of less than 10 mΩ.cm2 were achieved. • Quokka3 simulations show that cell efficiencies as high as 25% are possible using the optimised passivating contacts. We present ex-situ phosphorus-doped polycrystalline silicon (poly-Si) passivating contacts fabricated by the physical vapour deposition method, specifically sputtering. This technique is currently of great interest to the photovoltaics (PV) community due to its low deposition temperature, small footprint, high throughput, and use of low-hazard, solid targets and gases. We optimise the performance of the passivating contacts by adjusting various parameters from the sputtering of amorphous Si films to the formation of the poly-Si layers by a high-temperature thermal diffusion (with phosphorus oxychloride – POCl 3 , or phosphorus spin-on glass as the dopant sources). For the case of POCl 3 diffusion, a high iV oc of ∼720 mV together with a low J 0 of 2.6 fA/cm2 after a hydrogenation treatment by atomic layer deposition (ALD) AlO x and forming gas annealing (FGA), and a low contact resistivity ρ c of less than 10 mΩ cm2 were achieved. Meanwhile, with spin-on doping, a low average iV oc of ∼600 mV was observed. This variation in performance could be explained by the difference in the crystallinity and the diffusion mechanism of the sputtered Si films after different subsequent thermal diffusion processes. Quokka3 simulations show that cell efficiencies as high as 25% are possible using the optimised passivating contacts. The results demonstrate the potential of these PVD poly-Si films as a promising candidate for future industrial solar cells. [ABSTRACT FROM AUTHOR]

ISFH is following a distinct cell development roadmap, which comprises—as a short‐term concept—the combination of an n‐type doped electron‐collecting poly‐Si on oxide (POLO) junction with an Al‐alloyed p+ junction for hole collection. This combination can be integrated either in front‐ and back‐contacted back junction cells (POLO‐BJ) or in interdigitated back‐contacted cells (POLO‐IBC). Here, we present recent progress with these two cell concepts. We report on a certified M2‐sized 22.9% efficient POLO‐BJ cell with a temperature coefficient TCη of only −(0.3 ± 0.02) %rel/K and a certified 23.7% (4 cm2 d.a.) efficient POLO‐IBC cell. We discuss various specific conceptual aspects of this technology and present a simulation‐based sensitivity analysis for quantities related to the quality of the hole‐collecting alloyed Al‐p+ junction which are subject to continuous improvement and thus hard to predict exactly. We report that the measured pseudo fill factor values decrease more due to metallization than would be expected from recombination in the metallized regions with an ideality factor of one only. The gap to pseudo fill factor values that are theoretically achievable at the respective open‐circuit voltages is 1.1%abs (Ga‐doped wafer) for POLO‐IBC and 1.4%abs (B‐doped wafer) to 2%abs (Ga‐doped wafer) for POLO‐BJ. With an embedded blocking layer for Ag crystallites in the poly‐Si, we present a concept to reduce this gap. [ABSTRACT FROM AUTHOR]

The bit density is generally increased by stacking more layers in 3D NAND Flash. Lowering dopant activation of select transistors results from complex integrated processes. To improve channel dopant activation, the test structure of vertical channel transistors was used to investigate the influence of laser thermal annealing on dopant activation. The activation of channel doping by different thermal annealing methods was compared. The laser thermal annealing enhanced the channel activation rate by at least 23% more than limited temperature rapid thermal annealing. We then comprehensively explore the laser thermal annealing energy density on the influence of Poly-Si grain size and device performance. A clear correlation between grain size mean and grain size sigma, large grain size mean and sigma with large laser thermal annealing energy density. Large laser thermal annealing energy density leads to tightening threshold voltage and subthreshold swing distribution since Poly-Si grain size regrows for better grain size distribution with local grains optimization. As an enabler for next-generation technologies, laser thermal annealing will be highly applied in 3D NAND Flash for better device performance with stacking more layers, and opening new opportunities of novel 3D architectures in the semiconductor industry. [ABSTRACT FROM AUTHOR]

The negative gate bias stress (NBS) reliability of n-type polycrystalline silicon (poly-Si) thin-film transistors (TFTs) with a distinct defective grain boundary (GB) in the channel is investigated. Results show that conventional NBS degradation with negative shift of the transfer curves is absent. The on-state current is decreased, but the subthreshold characteristics are not affected. The gate bias dependence of the drain leakage current at V ds of 5.0 V is suppressed, whereas the drain leakage current at V ds of 0.1 V exhibits obvious gate bias dependence. As confirmed via TCAD simulation, the corresponding mechanisms are proposed to be trap state generation in the GB region, positive-charge local formation in the gate oxide near the source and drain, and trap state introduction in the gate oxide. [ABSTRACT FROM AUTHOR]

I Microhotplates are critical devices in various MEMS sensors that could provide appropriate operating temperatures. In this paper, a novel design of poly-Si membrane microhotplates with a heat compensation structure was reported. The main objective of this work was to design and fabricate the poly-Si microhotplate, and the thermal and electrical performance of the microhotplates were also investigated. The poly-Si resistive heater was deposited by LPCVD, and phosphorous doping was applied by in situ doping process to reduce the resistance of poly-Si. In order to obtain a uniform temperature distribution, a series of S-shaped compensation structures were fabricated at the edge of the resistive heater. LPCVD SiNx layers deposited on both sides of poly-Si were used as both the mechanical supporting layer and the electrical isolation layer. The Pt electrode was fabricated on the top of the microhotplate for temperature detection. The area of the heating membrane was 1 mm × 1 mm. Various parameters of the different size devices were simulated and measured, including temperature distribution, power consumption, thermal expansion and response time. The simulation and electrical–thermal measurement results were reported. For microhotplates with a heat compensation structure, the membrane temperature reached 811.7 °C when the applied voltage was 5.5 V at a heating power of 148.3 mW. A 3.8 V DC voltage was applied to measure the temperature distribution; the maximum temperature was 397.6 °C, and the area where the temperature reached 90% covered about 73.8% when the applied voltage was 3.8 V at a heating power of 70.8 mW. The heating response time was 17 ms while the microhotplate was heated to 400 °C from room temperature, and the cooling response time was 32 ms while the device was recovered to room temperature. This microhotplate has many advantages, such as uniform temperature distribution, low power consumption and fast response, which are suitable for MEMS gas sensors, humidity sensors, gas flow sensors, etc. [ABSTRACT FROM AUTHOR]

We have developed a process to grow high-crystallinity silicon films on insulators by intermittent pulse heating (IPH)-assisted plasma-enhanced chemical vapor deposition to address a drawback of incubation layer formation at the early stage of growth. By applying electrical pulses (22 V, 5 Hz, 10% duty ratio) to a Mo strip underneath a SiO2 layer, the surface is instantaneously heated to 1050 K while maintaining a steady substrate temperature of 670 K. The growth mechanism similar to that of solid-phase epitaxy enhanced its growth rate up to 1.2 nm s−1, which is five times greater than that of a-Si grown outside the Mo strip. The grown films assisted with IPH also showed a 97% crystalline volume fraction with no incubation layer. [ABSTRACT FROM AUTHOR]

This study demonstrated a polycrystalline-silicon (poly-Si)-based double-gate (DG) ion-sensitive field-effect transistors (DG-ISFETs) using APTES/SiO2 stack-sensing membrane. The APTES/SiO2 stack-sensing membrane enhanced the single-gate (SG) sensitivity, and suppressed the hysteresis. The DG structure was preferred to have a capacitive coupling effect and to amplify the sensitivity of ISFETs. The sensitivities of SG- and DG-ISFETs were approximately 56.8 and 294 mV pH−1, respectively. In addition, the corresponding amplifying factor was approximately 5.2. With this approach, the poly-Si DG-ISFETs can be a candidate for future high-performance biochemical sensing applications. [ABSTRACT FROM AUTHOR]

Poly-Si on oxide (POLO) structure is a passivation contact structure formed by growing a polysilicon layer on an extremely thin interface oxide layer based on the surface of the crystalline silicon. The passivation contact technology based on the POLO structure can not only obtain excellent surface passivation characteristics, but also avoid direct contact between the metal and the crystalline silicon surface, and greatly reduce the contact recombination of the metal and the crystalline silicon surface. At present, the conversion efficiency of small-area crystalline silicon solar cells made with POLO passivation contact structure is as high as 26.1%, and the industrialization efficiency of large-area crystalline silicon solar cells has exceeded 24.5%. At the same time, the POLO passivation contact technology applied to the production of crystalline silicon cells can withstand high-temperature processes and is compatible with existing crystalline silicon cell industrialization equipment. It is a passivation contact technology solution with great industrialization potential in the future. This paper mainly reviews the carrier transport mechanism in the POLO passivation contact structure and the corresponding quantitative parameter characterization methods. The methods of interfacial oxide layer growth, polysilicon layer deposition, doping and hydrogenation treatment in the preparation of POLO structure are compared. The parasitic absorption effect of the polysilicon layer, the morphological structure of the crystalline silicon surface, and the influence of the doping concentration distribution on the passivation contact characteristics of the POLO structure are summarized. The research progress of the POLO passivation contact technology and the difficulties in POLO solar cells production are briefly described. [ABSTRACT FROM AUTHOR]

Herein, an analysis on the impact of laser contact opening of TOPCon/SiNx stacks is presented. By etching in tetramethylammonium hydroxide (TMAH), the defect distribution in the interfacial tunnel oxide is accessed and analyzed. The defect density is significantly increased in areas where adjacent laser contact openings (LCO) overlap. Using microscopic photoluminescence (μ‐PL) spectroscopy, it is verified that correlates with an increase in the local recombination rate and thus an increase in the J0,Met. Therefore, overlapping LCO of SiNx in TOPCon/SiNx stacks should be avoided as much as possible. Furthermore, the investigations indicate that defects in the interfacial oxide are dominantly created along exposed structures like tips and edges of (etched‐back) pyramids. A comparison of TOPCon/SiNx stacks with a variation of TOPCon thicknesses indicate that etch pits, and thus the defect density, related to LCO become more significant at lower thicknesses. [ABSTRACT FROM AUTHOR]

This study investigates a device’s ability to boost its on-state current and subthreshold behavior using a ferroelectric field-effect transistor (FeFET) with an ultrathin sub-5-nm Hf1-xZrxO2 (HZO). A conventional field-effect transistor (FET) with pure hafnium (HfO2) is used as a control measure and the impact of an internal metal gate (IMG) is also discussed. The study was conducted by using a sub-5-nm HZO and seed layer to fabricate a gate-all-around (GAA) nanowire (NW); a FeFET with a metal-ferroelectric–metal-insulator-semiconductor (MFMIS) structure; and a double layer (DL) of the channel. The channel size used in the experiment was approximately $9.6\times16$ nm2 and the total thickness of the gate stack was 9.2 nm. This thickness is 50.5% less than our previous experiment. The FeFET exhibits a considerably high ${I}_{on}$ – ${I}_{off}$ ratio exceeding 107. The IMG serves as a potential equalizer and the ferroelectric material is arranged in a more symmetrical electric field. This results in a lower subthreshold (sub- ${V}_{TH}$ ) swing ( $S.S._{min}=$ 49.3mV/decade) with a wide range ( $10^{3}$ ) of drain currentcompared to that without an IMG. The findings indicate that a high-performance GAA FET can be achieved by combining a DL channel, GAA NW, ferroelectric material, and an IMG.

In this study, hysteresis-free double-layer gate-all-around stacked poly-Si nanosheet channel ferroelectric HfxZr1-xO2 negative capacitance field-effect transistors (DL GAA NS FE-HZO NC-FETs) with an internal metal gate (IMG) and NH3 plasma nitridation were experimentally investigated and comprehensively discussed for the first time. The results revealed that NH3 plasma nitridation at both the ZrO2/TiN and TiN/HZO interfaces can effectively enhance the HZO ferroelectricity and quality by suppressing the generation of oxygen vacancies (${V}_{o}{)}$. Furthermore, the SiON interfacial layer quality can be enhanced by passivating bulk defects within the SiON interfacial layer through NH3 plasma nitridation at the ZrO2/TiN interface. When NH3 plasma nitridation is performed at both the ZrO2/TiN and TiN/HZO interfaces, the devices exhibit excellent electrical characteristics: 1) an extremely low subthreshold swing (SS) of 45.77 mV/decade; 2) an ultrasteep average SS (ASS) of 61.39 mV/decade; 3) a relatively high ON/OFF current ratio (${I}_{ \mathrm{\scriptscriptstyle ON}} / {I}_{ \mathrm{\scriptscriptstyle OFF}}{)}$ of $ > 5\,\,\times \,\,10^{{7}}$ ; and 4) a quite high effective breakdown voltage (${V}_{\text {EBD}}$) of 6.7 V at ${V}_{D}$ = 0.1 V. Thus, these devices are promising candidates for low-power-consumption monolithic 3-D integrated circuit (IC) applications. [ABSTRACT FROM AUTHOR]

We demonstrated that channel mobility and cell current could be increased through Ge diffusion engineering and H2 plasma treatment in a poly-Si channel. Even though the Ge channel has a higher intrinsic mobility than the Si channel, a typical poly-SiGe channel has inferior channel characteristics due to high interface trap density (Dit) and bulk trap density caused by Ge. We propose a novel technique to control the Ge profile along the depth direction of the channel to realize lower Ge concentration at the gate dielectric interface and higher Ge concentration at the channel bulk. This Ge profile could achieve reduced Dit and enhanced channel mobility. Furthermore, the bulk traps caused by Ge are effectively reduced by H2 plasma treatment. These techniques increased the channel mobility to 32%, which can help increase the channel mobility of devices where poly-Si channels are used. [ABSTRACT FROM AUTHOR]

This work presents the development and the application of innovative and sustainable transparent conductive oxide (TCO) materials for contacting polysilicon (poly-Si) on oxide (SiOx) stacks used as passivating contacts in solar cell devices. Adding hydrogen into ZnO:Al (AZO) layers deposited by magnetron sputtering potentially leads to a twofold positive effect. First, it brings hydrogen atoms into the layers, which can enhance both electrical and optical material properties of the TCO. Second, hydrogen can significantly improve cell performances, by fixing dangling bonds at the SiOx/substrate interface and by passivating bulk defects. In situ and ex situ hydrogenation processes have been compared on those multiple aspects with investigation about anneals at 350 °C. AZO layers have been successfully integrated on the front side of complete solar cells featuring poly-Si/SiOx-based passivating contacts, leading to a record conversion efficiency of 22.4% for a cell with AZO. The results show that using AZO instead of an indium based TCO is suitable for passivated contacts solar cell with high temperature route. Thus, it increases the credibility towards large-scale deployments of TCO-based high efficiency silicon solar cells in terms of cost and resources. [ABSTRACT FROM AUTHOR]

The bit density is generally increased by stacking more layers in 3D NAND Flash. Lowering dopant activation of select transistors results from complex integrated processes. To improve channel dopant activation, the test structure of vertical channel transistors was used to investigate the influence of laser thermal annealing on dopant activation. The activation of channel doping by different thermal annealing methods was compared. The laser thermal annealing enhanced the channel activation rate by at least 23% more than limited temperature rapid thermal annealing. We then comprehensively explore the laser thermal annealing energy density on the influence of Poly-Si grain size and device performance. A clear correlation between grain size mean and grain size sigma, large grain size mean and sigma with large laser thermal annealing energy density. Large laser thermal annealing energy density leads to tightening threshold voltage and subthreshold swing distribution since Poly-Si grain size regrows for better grain size distribution with local grains optimization. As an enabler for next-generation technologies, laser thermal annealing will be highly applied in 3D NAND Flash for better device performance with stacking more layers, and opening new opportunities of novel 3D architectures in the semiconductor industry.

One-time programmable (OTP) memory is essential to the security and gaming industries because of its “write once, read many” capability. This device supports N-metal–oxide–semiconductor polycrystalline-silicon junctionless gate-all-around (GAA) nanowire transistor technology and can perform multistate antifuse. It is capable of functioning in four states instead of in the standard two states (open/short). Furthermore, the states can be read as fully open (0, 0), drain–gate breakdown (0, 1), source–gate breakdown (1, 0), and full breakdown (1, 1) states. The antifuse is formed from the oxide breakdown between the gate and the source or drain (S/D). Moreover, because multiple samples have been successfully produced, its information can be displayed as a chart or table to instantly convey information about the current device’s state to programmers by reading the S/D current. [ABSTRACT FROM AUTHOR]

A doping technique for p‐type poly‐Si/SiOx passivating contacts using a spin‐on method for different mixtures of Ga and B glass solutions is presented. Effects of solution mixing ratios on the contact performance (implied open circuit voltage iVoc, contact resistivity ρc) are investigated. For all as‐annealed samples at different drive‐in temperatures, increasing the percentage of Ga in the solution shows a decrement in iVoc (from ∼680 to ∼610 mV) and increment in ρc (from ∼3 to ∼800 mΩ cm2). After a hydrogenation treatment by depositing a SiNx/AlOx stack followed by forming gas annealing, all samples show improved iVoc (∼700 mV with Ga‐B co‐doped, and ∼720 mV with all Ga). Interestingly, when co‐doping Ga with B, even a small amount of B in the mixing solution shows negative effects on the surface passivation. Active and total dopant profiles obtained by electrical capacitance voltage and secondary‐ion mass spectrometry measurements, respectively, reveal a relatively low percentage of electrically‐active Ga and B in the poly‐Si and Si layers. These results help understand the different features of the two dopants: a low ρc with B, a good passivation with Ga, their degree of activation inside the poly‐Si and Si layers, and the annealing effects. [ABSTRACT FROM AUTHOR]

Recent progress in surface passivation technology and wafer pretreatment already resulted in significant improvements in the achievable minority charge carrier lifetime of crystalline silicon. Herein, this is further exemplified by studying the lifetime on lowly doped crystalline silicon wafers passivated by poly‐Si. To ensure credible lifetime measurements multiple measurement techniques are compared and good agreement between the investigated approaches is found. The resulting lifetime curves are analyzed in detail and the main limitation is very likely caused by silicon bulk recombination—most likely due to impurities. This analysis indicates that even very low impurity concentrations can be a limiting factor at the extraordinary high level of charge carrier lifetime observed in this study. Despite these limitations, lifetimes of 0.18 s on p‐type and 0.5 s on n‐type crystalline silicon wafers are measured, which to our knowledge exceed previously reported lifetimes. In both cases, these measured lifetimes correspond to an effective minority charge carrier diffusion length of ≈2.5 cm. [ABSTRACT FROM AUTHOR]

I Microhotplates are critical devices in various MEMS sensors that could provide appropriate operating temperatures. In this paper, a novel design of poly-Si membrane microhotplates with a heat compensation structure was reported. The main objective of this work was to design and fabricate the poly-Si microhotplate, and the thermal and electrical performance of the microhotplates were also investigated. The poly-Si resistive heater was deposited by LPCVD, and phosphorous doping was applied by in situ doping process to reduce the resistance of poly-Si. In order to obtain a uniform temperature distribution, a series of S-shaped compensation structures were fabricated at the edge of the resistive heater. LPCVD SiNx layers deposited on both sides of poly-Si were used as both the mechanical supporting layer and the electrical isolation layer. The Pt electrode was fabricated on the top of the microhotplate for temperature detection. The area of the heating membrane was 1 mm × 1 mm. Various parameters of the different size devices were simulated and measured, including temperature distribution, power consumption, thermal expansion and response time. The simulation and electrical–thermal measurement results were reported. For microhotplates with a heat compensation structure, the membrane temperature reached 811.7 °C when the applied voltage was 5.5 V at a heating power of 148.3 mW. A 3.8 V DC voltage was applied to measure the temperature distribution; the maximum temperature was 397.6 °C, and the area where the temperature reached 90% covered about 73.8% when the applied voltage was 3.8 V at a heating power of 70.8 mW. The heating response time was 17 ms while the microhotplate was heated to 400 °C from room temperature, and the cooling response time was 32 ms while the device was recovered to room temperature. This microhotplate has many advantages, such as uniform temperature distribution, low power consumption and fast response, which are suitable for MEMS gas sensors, humidity sensors, gas flow sensors, etc.

We developed a method of measuring microscopic ζ potential (ZP) from force vs distance (FD) curves observed by atomic force microscope (AFM). ZP in microscopic regions on wafer surfaces may be one of the most important design guides of chemical mechanical polishing slurries applicable to ultrafine patterned wafers, while ZP is generally observed as an average information for a wide area. Our method is based on the linear correlation between jump-in loads in FD curves observed by the AFM for the blanket wafers (SiO2, SiN and poly-Si) in water systems and ZP of each wafer surface measured by the flow potential method. In the applications of our AFM-based measurement method, material-dependency of ZP on the SiO2/SiN patterned wafer surface and an additive material in a slurry (anionic polymer) adsorbing selectively on the SiN surface of the SiO2/SiN patterned wafer were observed. [ABSTRACT FROM AUTHOR]

This study focused on optimizing the high-temperature crystallization annealing process in the production of TOPCon solar cells to enhance power conversion efficiency. The annealing process is employed to transform amorphous silicon into polycrystalline silicon (Poly-Si). Furthermore, during this annealing process, phosphorus atoms can form Si–P bonds to achieve effective doping in the Poly-Si layer. The experimental results indicated that, under high-temperature conditions, phosphorus atoms in the Poly-Si layer near the crystalline silicon wafer surface crossed the tunneling layer and infiltrated into the silicon substrate. Intensive inward diffusion resulted in the accumulation of phosphorus close to the wafer surface. The loss of numerous phosphorus atoms in the Poly-Si layer and the accumulation of phosphorus in the wafer readily lead to the formation of an undesirable N−/N+ high-low junction, which is detrimental to carriers' output. However, the annealing condition affects the crystallinity of the Poly-Si layer, which is crucial to providing an excellent passivation effect. This study achieved the optimal annealing conditions for the current N-type TOPCon solar cell production process by adjusting the annealing temperature and crystallization time. Ensuring Poly-Si crystallization and minimizing phosphorus inward diffusion resulted in an approximate 0.1% abs. improvement in cells' power conversion efficiency. [Display omitted] • The annealing process was optimized to reduce the phosphorus inward diffusion. • The N−/N+ high-low junctions inside the substrate were eliminated. • Barrier was decreased by the optimization, leading to high efficient electron transportation. • The efficiency of solar cells was increased by approximate 0.1% abs.. [ABSTRACT FROM AUTHOR]

In this paper, the influence of nitrous oxide (N2O) nitridation temperatures on p-type Pi-gate (PG) poly-Si junctionless accumulation mode (JAM) TFTs is experimentally investigated. The tetraethoxysilane (TEOS) gate oxide quality for PG JAM TFTs can be significantly improved by increasing N2O nitridation temperatures (TN) from 700°C to 800°C in N2O ambient, resulting in the improvement of average subthreshold swing (A.S.S.), increase of on current (ION), and enhancement of TEOS gate oxide breakdown E-field (EOBD). PG JAM TFTs by means of a proper channel doping concentration (Nch = 5 × 1018 cm-3) and a suitable TN (800°C) exhibit a steep A.S.S. ~96 mV/dec. and a large EOBD~12.1 MV/cm.

A self-limited low-temperature trimming process is demonstrated without surface morphology degradation. It shows great potential to control the trimming process with a large process window (400-900 s). Subthreshold characteristics are improved and Ioff is drastically reduced (~two orders of magnitude) with increasing trimming cycles. Full silicidation on the source/drain (FUSI-S/D) is performed to improve Ion. Surprisingly, after silicidation, both Ion and μFE shows degradation despite that the series resistance is improved. An ultrathin body junctionless (UTB-JL) device is fabricated to investigate the degradation cause by direct CV measurement on the device, which can give us an insight into the details of the change with the silicidation.

In this study, p-type Pi-gate (PG) poly-Si nanowire channel junctionless accumulation-mode (JAM) field-effect transistors (FETs) were successfully fabricated and their reliability was investigated. The reliability of these PG JAM FETs was found to be dependent on the effective channel doping concentration (Nch,eff). Through a negative gate bias stress (NGBS) test, we found that degradation in the average subthreshold swing (A.S.S.) and shift in the threshold voltage (VTH) increases as the Nch,eff of the PG JAM FETs decreases. Furthermore, the PG JAM FETs with a lower Nch,eff show the more severe rate of deterioration in the transconductance (Gm) and ON current (ION). By increasing Nch,eff to reduce the electric field (E-field) on the gate oxide and tune the carrier transport mechanism in the poly-Si nanowire channel, a better immunity against the NGBS test in the p-type PG JAM FETs can be achieved under a gate overdrive voltage (VGOD = VG – VTH = −3.5 V) to perform the NGBS test. [ABSTRACT FROM AUTHOR]

Summary: The world has witnessed a substantial upsurge in energy demand in the recent decades, which has concurrently led to increased environmental contamination due to the use of carbon‐based fuels to meet this demand. The increased pollution levels across the globe combined with the rapid depletion of these carbon‐based non‐renewable sources of energy has forced nations to adopt cleaner sources such as solar energy, wind energy, biomass etc. for meeting energy requirements. Utilities and power transmission companies, in several countries, have begun installation and operation of large‐scale solar energy projects in order to augment the present electricity generation capacity. India has a tremendous potential for solar energy as 58% of the total land area receives an average solar insolation above 5 kWh/m2/day, annually. However, PV installations require proper economic formulation and technical modelling of PV plants. The study presented in this paper investigates the feasibility of installing a 1 MW grid‐connected PV system in the arid climatic conditions of India. Four different regions of the Thar Desert: Barmer, Jodhpur, Jaisalmer, and Kalan Ghat have been considered for the study. A comparative study has been laid out based on energy yields, losses, and degradation of various module technologies namely mono‐Si, poly‐Si, CdTe, and CIS. The performance of the PV systems has been evaluated both in the fixed‐tilt and variable‐tilt configurations. Simulation results show that the daily yield in winter months ranges between 5.8 and 6.9 MWh/day whereas, during summer, it ranges between 5 and 7.1 MWh/day. The study suggests that CIS module is expected to produce highest annual energy yield of 2471 MWh with a PR of 86.1%, in the variable‐tilt configuration for the Jaisalmer region. Annual energy loss due to temperature is expected to be highest for mono‐Si technology (14.4%) in the variable‐tilt configuration and lowest for CIS technology (9.4%) in the fixed‐tilt configuation. Moreover, mismatch losses for all the four technologies lie in the range of 0.1‐1.1%. [ABSTRACT FROM AUTHOR]

After printing and sintering of the N type TOPCon (Tunnel Oxide Passivating Contacts) solar cells, the efficiency was improved significantly by light injection, which mainly manifested in the improvement of Voc and FF. The mechanism is to improve the passivation performance through adjusting the Fermi energy level by temperature and light intensity and controlling the total amount and valence state of H. The quality of the passivation film, the doping concentration of silicon substrate and the temperature during the light injection annealing process have great influence on the efficiency of the light injection annealing process. The experiments show that the lower the conversion efficiency of the battery is, the higher the efficiency is after light injection. The higher the conversion efficiency is, the smaller the defect will be, and the efficiency has almost no gain after the light injection annealing process. In addition, concentric circles can be eliminated obviously after light injection annealing process. This paper mainly studies the effects of temperature, light intensity, substrate resistivity, front surface metal contact area and poly-Si thickness on the efficiency of light injection annealing process. [ABSTRACT FROM AUTHOR]

This work presents the development and the application of innovative and sustainable transparent conductive oxide (TCO) materials for contacting polysilicon (poly-Si) on oxide (SiOx) stacks used as passivating contacts in solar cell devices. Adding hydrogen into ZnO:Al (AZO) layers deposited by magnetron sputtering potentially leads to a twofold positive effect. First, it brings hydrogen atoms into the layers, which can enhance both electrical and optical material properties of the TCO. Second, hydrogen can significantly improve cell performances, by fixing dangling bonds at the SiOx/substrate interface and by passivating bulk defects. In situ and ex situ hydrogenation processes have been compared on those multiple aspects with investigation about anneals at 350 °C. AZO layers have been successfully integrated on the front side of complete solar cells featuring poly-Si/SiOx-based passivating contacts, leading to a record conversion efficiency of 22.4% for a cell with AZO. The results show that using AZO instead of an indium based TCO is suitable for passivated contacts solar cell with high temperature route. Thus, it increases the credibility towards large-scale deployments of TCO-based high efficiency silicon solar cells in terms of cost and resources.

In this paper, the influence of channel doping concentration and reverse boron penetration on p-type Pi-gate (PG) poly-Si junctionless accumulation mode (JAM) FETs has been experimentally investigated and discussed. Effective carrier concentration (Neff) and threshold voltage (VTH) are found to be sensitive to doping concentration. Moreover, the positive shift in VTH and the degradation in the subthreshold behavior for PG JAM FETs are observed after an additional source/drain (S/D) activation process. Using a low thermal-budget S/D activation process, PG JAM FETs with a suitable channel doping concentration can show excellent electrical characteristics: 1) steep subthreshold swing of 86 mV/dec.; 2) low average subthreshold swing (A.S.S.) of 96 mV/dec.; and 3) high ON/OFF current ratio (ION/IOFF) of 7.7 × 107 (ION at VG - VTH = -2 V and VD = -1 V).

We present a semi‐analytical model for the calculation of the current through and the recombination in carrier‐selective junctions consisting of a poly‐Si/SiOx/c‐Si layer stack. We calculate the recombination parameter J0 and the contact resistance ρC after solving the band‐bending‐problem on both sides of the interfacial oxide. Comparisons with finite‐element simulations show that the current calculation is reliable at all bias conditions except for inversion and that current through pinholes is resolved adequately in the model. The model allows a coherent description of lifetime‐, current‐voltage‐ and capacitance‐voltage measurements performed on a sample with dominant tunneling. We use our model to investigate the influence of oxide thickness and pinhole density on J0 and ρC of our state‐of‐the‐art poly‐silicon‐on‐oxide (POLO) junctions and demonstrate its usefulness for the optimization of poly‐Si based junctions. [ABSTRACT FROM AUTHOR]

In this study, conventional CMOS and complementary field-effect transistor (CFET) inverters based on a vertically stacked-nanosheet (NS) structure were fabricated. The NS below 8-nm channel layer thickness (TSi) was obtained by dry etching and wet etching processes. The channel thickness is controlled by dry etching, and the channel width was shrunk down by wet etching. Compared to single nanowire field-effect transistors (NSFETs), stacked NSFETs exhibit higher ON-current performance. For the CMOS inverter, the voltage transfer characteristics (VTCs) could be matched much better by adjusting the channel widths and layers for N-channel MOSFET (NFET) and P-channel MOSFET (PFET), respectively. For the CFET inverter, layout areas could be reduced and requires less number of lithographic and ion implantation steps contrary to the CMOS inverter. However, we observe that the VTCs of the CFET inverters still show asymmetric behavior due to the difficulties of adjustment in NS layers and systematic behavior of threshold voltages for NFETs/PFETs. This work experimentally demonstrates the CMOS and CFET inverters on the vertically stacked NS structure, which is promising for system-on-panel (SoP) and 3-D-ICs applications. [ABSTRACT FROM AUTHOR]

In the OLED backplane process, we have succeeded in controlling the TFT characteristics by optimizing the condition of hydrogenation annealing. This resulted in the good gray level control of the OLED display. We have finally developed the OLED smartphone display using this technology. [ABSTRACT FROM AUTHOR]

We present a systematic study on the benefit of the implementation of poly‐Si on oxide (POLO) or related junctions into p‐type industrial Si solar cells as compared with the benchmark of Passivated Emitter and Rear Cell (PERC). We assess three aspects: (a) the simulated efficiency potential of representative structures with POLO junctions for none (=PERC+), one, and for two polarities; (b) possible lean process flows for their fabrication; and (c) experimental results on major building blocks. Synergistic efficiency gain analysis reveals that the exclusive suppression of the contact recombination for one polarity by POLO only yields moderate efficiency improvements between 0.23%abs and 0.41%abs as compared with PERC+ because of the remaining recombination paths. This problem is solved in a structure that includes POLO junctions for both polarities (POLO2), for whose realization we propose a lean process flow, and for which we experimentally demonstrate the most important building blocks. However, two experimental challenges—alignment tolerances and screen‐print metallization of p+ poly‐Si—are unsolved so far and reduced the efficiency of the "real" POLO2 cell as compared with an idealized scenario. As an intermediate step, we therefore work on a POLO IBC cell with POLO junctions for one polarity. It avoids the abovementioned challenges of the POLO2 structure, can be realized within a lean process flow, and has an efficiency benefit of 1.59%abs as compared with PERC—because not only contact recombination is suppressed but also the entire phosphorus emitter is replaced by an n+ POLO junction. [ABSTRACT FROM AUTHOR]

A unique approach for fabricating poly-Si thin-film transistors (TFTs) with self-aligned T-shaped gate (T-gate) structure is reported. A counter-doped poly-Si process comprises an in-situ doped ${n}^{+}$ poly-Si deposition followed by a subsequentshallow implantation of BF $_{{2}}^{+}$. Both high etching isotropy in ${n}^{+}$ poly-Si and high etching selectivity between ${n}^{+}$ poly-Si and B-doped poly-Si in a Cl2-based plasma process are the key enablers for the fabrication of our T-gate structures. Thanks to good control in the shape and deformation of our T-gate structure, sidewall air-gap spacers in combination with self-aligned Ni silicided gate and source/drain were established. High-performance sub-micron poly-Si TFTs are evidenced by superior transfer characteristics measured on TFTs with effective gate length of $0.15~\mu \text{m}$. The unique T-gate structure provides an effective way for possible production of poly-Si radio-frequency TFTs viable for emerging new applications. [ABSTRACT FROM AUTHOR]

The objectives of this study are to explore the activation ratios of implanted phosphorus dopants in polycrystalline silicon (poly-Si), and to reveal the role of grain boundary segregation in incomplete activation using atom probe tomography (APT) and differential Hall effect metrology (DHEM). After implantation and rapid thermal annealing, the results of APT revealed pronounced segregation toward grain boundaries that provides rapid diffusion paths for phosphorus. Peak concentrations of phosphorus segregations in the grain boundaries of the regrown and non-regrown regions were measured to be 4.38E21 and 2.17E21 atoms/cm³ that correspond to activation ratios of 6 % and 1 %, respectively. In contrast, phosphorus concentrations within grain interiors were found to be 6.86E20 and 1.72E19 atoms/cm³, corresponding to activation ratios of 39 % and nearly 100 % in the regrown and non-regrown regions, respectively. This research highlights a novel approach for evaluating site-specific activation ratios in poly-Si through the integrated use of DHEM and APT. [Display omitted] [ABSTRACT FROM AUTHOR]

For the first time, two-layer stacked nanowire gate-all-around (GAA) negative capacitance (NC) field-effect transistors (FETs) with an ultrasmall poly-Si channel that has a size of $5.3\times9$ nm2 and a metal-ferroelectric-metal-insulator-semiconductor (MFMIS) are experimentally demonstrated. FETs exhibit a remarkable Ion–Ioff ratio of more than 108. We demonstrated stacked channels, double layers, GAA NC-FET with a threshold voltage (${V}_{\textit {TH}}$) of 0.61 V, and a superior subthreshold behavior with an average and minimum sub- ${V}_{\textit {TH}}$ slope of 43.85 and 26.84 mV/dec, respectively. An additional ZrO2 seed layer was inserted under the Hf $_{{1-}{x}}$ ZrxO2 layer to improve ferroelectric crystallinity. Thus, the conventional crystallization annealing step can be omitted due to the presence of the orthorhombic phase (${o}$ -phase) before further post-metal annealing (PMA). [ABSTRACT FROM AUTHOR]

The junction properties of tunnel silicon oxide (SiO x) passivated contact (TOPCon) with n-type poly-Si on p-type c-Si wafer are characterized using current-voltage (J-V) and capacitance-voltage (C-V) measurements. The dark J-V curves show a standard diode characteristic with a turn-on voltage of ∼0.63 V, indicating a p-n junction is formed. While the C-V curve displays an irregular shape with features of 1) a slow C increase with the decrease of the magnitude of reverse bias voltage, being used to estimate the built-in potential (V bi), 2) a significant increase at a given positive bias voltage, corresponding to the geometric capacitance crossing the ultrathin SiO x , and 3) a sharp decrease to negative values, resulting from the charge tunneling through the SiO x layer. The C of depleting layer deviates from the normal linear curve in the 1/C 2 -V plot, which is caused by the diffusion of P dopants from the n-type poly-Si into the p-type c-Si wafer as confirmed by the electrochemical capacitance-voltage measurements. However, the 1/C 2+γ -V plots with γ > 0 leads to linear curves with a proper γ and the V bi can still be estimated. We find that the V bi is the range of 0.75–0.85 V, increases with the increase of the doping ratio during the poly-Si fabrication process, and correlates with the passivation quality as measured by the reverse saturated current and implied open circuit voltage extracted from transient photoconductivity decay. • The junction properties of TOPCon with n-poly-Si on p-c-Si wafer are characterized and correlated to the passivation quality. • The C-V displays an irregular shape and the 1/C2-V plot does not show the linear behavior. • The diffusion of P dopants from the n-poly-Si through the SiOx into the p-c-Si wafer causes the irregular C-V behavior. • The 1/Cα-V plots with α > 2 yields linear lines with a proper α and the V bi can still be estimated. • The V bi is estimated the range of 0.75–0.85 V, indicating the potential of high Voc n-TOPCon on p-type wafers. [ABSTRACT FROM AUTHOR]

A polycrystalline silicon (poly-Si) capacitorless one-transistor dynamic random-access memory (1T DRAM) has been successfully fabricated and characterized. The proposed 1T DRAM is based on the metal-oxide-semiconductor field-effect transistor with heavily-doped ${n}^{+}$ source and drain junctions, nearly intrinsic ${n}^{-}$ channel, 500-nm gate length (${L}_{{{\mathrm {G}}}}$), and 50-nm poly-Si body thickness (${T}_{{{\mathrm {body}}}}$). The floating-body for storing charges was schemed in the silicon-on-insulator (SOI)-like environment which was simply realized by deposited buried oxide and poly-Si layers for the high cost-effectiveness. The program and erase operations are performed by band-to-band tunneling and drift-diffusion mechanisms, respectively, and the retention is assisted by the grain boundaries capable of charge trapping, not solely depending on recombination in Si. The proposed cell achieved an initial sensing margin of $3.2~{\mu }\text{A}/{\mu }\text{m}$ and a long retention time of 1.2 s. The thin-body poly-Si 1T DRAM with full Si processing compatibility has the strong candidacy for the embedded DRAM in the advanced integrated systems. [ABSTRACT FROM AUTHOR]

In this paper, an analytical model has been developed to observe the recombination losses involved in a tunnel oxide passivated contact solar cell with a carrier-selective layer constituting polycrystalline silicon (poly-Si). The main focus of this paper is to observe the contribution of each component of recombination current density and its effect on open-circuit voltage, Voc. The effect of emitter saturation current density (Joe), surface recombination velocity, substrate thickness, and doping density of carrier-selective layer on Voc has been presented. The analysis indicates that Voc = 766 mV can be achieved for Joe = 2 fA/cm2, and a doping density of poly-Si > 1021cm−3 in a c-Si/SiO2/poly-Si contact for a 50- $\mu \text{m}$ -thick substrate in case of ideal surface passivation. For identical conditions, Voc attains a lower value of 750mV for a 180- $\mu \text{m}$ -thick substrate. The dependence of Voc on bandgap of tunnel layers has also been observed by considering other materials like Si3N4 and SiC. These results from the analyticalmodel have been compared with results froma simulation using automat FOR simulation of HETerostructures v2.5 and have been found to be in good agreement with each other. [ABSTRACT FROM AUTHOR]

Highlights • I D -V G characteristics and transient drain current behaviors are investigated in 3D NAND flash devices with various body thicknesses and grain sizes. • As the body thickness decreases with the same grain size, the transient current instability and on-state current are improved. • When the grain size is increased with the same body thickness, the transient current instability and on-state current are improved. Abstract In order to verify the effects of polycrystalline Si (poly-Si) body thickness scale-down on read operation in 3D NAND flash memory which has tube type thin body, TCAD simulations and the measurements of fabricated devices are performed. I D - V G characteristics and transient drain current behaviors are investigated in 3D NAND devices with various body thicknesses and grain sizes. It has been known that drain current undershoot/overshoot is observed in poly-Si channel devices by falling/rising step gate bias. These phenomena are strongly related with transient of potential barrier height due to slow capture/emission rate of poly-Si grain boundary traps. As the body thickness decreases with the same grain size, the transient current instability, on-state current, and subthreshold-swing are improved. When the grain size is increased with the same body thickness, the transient current instability, on-state current, and subthreshold-swing are improved. [ABSTRACT FROM AUTHOR]

As an upgraded version of passivated emitter and rear cell (PERC) solar cells, the performance of tunnel oxide passivating contacts (TOPCon) solar cells is very dependent on the silicon oxide layer and poly-Si layer. We found that different crystallization rates or doping of germanium, carbon and other elements in poly-Si can change the band gap of poly-Si, which has an impact on the efficiency (E ff) of TOPCon solar cells. Therefore, the appropriate band gap is particularly important. At the same time, the internal defect of poly-Si also have great influence on the performance of solar cells. The simulated band diagram, charge carrier concentration and recombination rate were used to deeply explore the defect in poly-Si and the influence of poly-Si with different band gap on the performance of TOPCon solar cells. • As the band gap increases, the performance of TOPCon solar cell improves. • After reaching the threshold value (1.34 eV), TOPCon solar cell performance no longer changes. • The performance of TOPCon solar cell decreases rapidly as the concentration of defect states in the acceptor-like defect states increases. • TOPCon solar cell performance decreases with increasing concentration of donor-like defect states, but the change is small. [ABSTRACT FROM AUTHOR]