Impact of Interface Trap Distribution on the Performance of LTPS TFT.

This article presents a multiple trapping and release model (MTR) based technology computer-aided design (TCAD) investigation of low-temperature poly-silicon (LTPS) thin film transistors (TFTs). To consider the role of localized and delocalized states in carrier transport, the proposed simulation framework considers the inclusion of interface traps in the TFTs, which effectively represent the defects present in the poly-Si/ gate dielectric interface and the grain boundaries (GBs). The device performance is reported for Gaussian and double-exponential deep and tail state trap distribution of acceptor-like and donor-like interface traps by varying the trap-distribution parameters such as peak trap concentration (N₀) and location of peak (E_mid). Electrical parameters such as on and off-state currents, threshold voltage and subthreshold swing are reported for the parametric investigation. As the trap distribution penetrates deeper into the bandgap from the band edges, the performance deteriorates, as evident from the increase in subthreshold swing and threshold voltage. The impact and results of the analyses infer that the proposed framework can be applied to predict and model LTPS TFTs through a design-and-simulation approach as proposed in the article. [ABSTRACT FROM AUTHOR]