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The effect of a linear accelerator’s (LINAC’s) microstructure (i.e., train of narrow pulses) on devices and the associated transient photocurrent models are investigated. The data indicate that the photocurrent response of Si-based RF bipolar junction transistors and RF p-i-n diodes is considerably higher when taking into account the microstructure effects. Similarly, the response of diamond, SiO2, and GaAs photoconductive detectors (standard radiation diagnostics) is higher when taking into account the microstructure. This has obvious hardness assurance implications when assessing the transient response of devices because the measured photocurrent and dose rate levels could be underestimated if microstructure effects are not captured. Indeed, the rate the energy is deposited in a material during the microstructure peaks is much higher than the filtered rate which is traditionally measured. In addition, photocurrent models developed with filtered LINAC data may be inherently inaccurate if a device is able to respond to the microstructure.

Total ionizing dose results are provided, showing the effects of different threshold adjust implant processes and irradiation bias conditions of 14-nm FinFETs. Minimal radiation-induced threshold voltage shift across a variety of transistor types is observed. Off-state leakage current of nMOSFET transistors exhibits a strong gate bias dependence, indicating electrostatic gate control of the sub-fin region and the corresponding parasitic conduction path are the largest concern for radiation hardness in FinFET technology. The high- $V_{\textit {th}}$ transistors exhibit the best irradiation performance across all bias conditions, showing a reasonably small change in off-state leakage current and $V_{\textit {th}}$ , while the low- $V_{\textit {th}}$ transistors exhibit a larger change in off-state leakage current. The “ worst-case” bias condition during irradiation for both pull-down and pass-gate nMOSFETs in static random access memory is determined to be the on-state ( $V_{\textit {gs}}=V_{\textit {dd}}$ ). We find the nMOSFET pull-down and pass-gate transistors of the SRAM bit-cell show less radiation-induced degradation due to transistor geometry and channel doping differences than the low- $V_{\textit {th}}$ transistor. Near-threshold operation is presented as a methodology for reducing radiation-induced increases in off-state device leakage current. In a 14-nm FinFET technology, the modeling indicates devices with high channel stop doping show the most robust response to TID allowing stable operation of ring oscillators and the SRAM bit-cell with minimal shift in critical operating characteristics.

The locations of conductive regions in TaO x memristors are spatially mapped using a microbeam and Nanoimplanter by rastering an ion beam across each device while monitoring its resistance. Microbeam irradiation with 800 keV Si ions revealed multiple sensitive regions along the edges of the bottom electrode. The rest of the active device area was found to be insensitive to the ion beam. Nanoimplanter irradiation with 200 keV Si ions demonstrated the ability to more accurately map the size of a sensitive area with a beam spot size of 40 nm by 40 nm. Isolated single spot sensitive regions and a larger sensitive region that extends approximately 300 nm were observed.

This work presents experimental Single Event Gate Rupture (SEGR) data for Metal–Insulator–Semiconductor (MIS) devices, where the gate dielectrics are made of stacked SiO2–Si3N4 structures. A semi-empirical model for predicting the critical gate voltage in these structures under heavy-ion exposure is first proposed. Then interrelationship between SEGR cross- section and heavy-ion induced energy deposition probability in thin dielectric layers is discussed. Qualitative connection between the energy deposition in the dielectric and the SEGR is proposed. peerReviewed

The effects of radiation on memristors created using tantalum oxide and titanium oxide are compared. Both technologies show changes in resistance when exposed to 800 keV Ta ion irradiation at fluences above 1010 cm-2. TaOx memristors show a gradual reduction in resistance at high fluences whereas TiO2 memristors show gradual increases in resistance with inconsistent decreases. After irradiation TaOx devices remain fully functional and can even recover resistance with repeated switching. TiO2 devices are more variable and exhibit significant increases and decreases in resistance when switching after irradiation. Irradiation with 28 MeV Si ions causes both technologies to switch from the off-state to the on-state when ionizing doses on the order of 60 Mrad(Si) or greater (as calculated by SRIM) are reached without applying current or voltage to the part. Irradiation with 10 keV X-rays up to doses of 18 Mrad(Si) in a single step show little effect on either technology. TaOx and TiO2 memristors both show high tolerance for displacement damage and ionization damage and are promising candidates for future radiation-hardened non-volatile memory applications.

A methodology for power MOSFET radiation hardness assurance is proposed. It is based on the statistical analysis of destructive events, such as gate oxide rupture. Examples of failure rate calculations are performed.

Techniques for removing the back substrate of SOI devices are described for both packaged devices and devices at the die level. The use of these techniques for microbeam, heavy-ion, and laser testing are illustrated.

Radiation effects are presented for the first time for vertically integrated 3 × 64-kb SOI SRAM circuits fabricated using the 3D process developed at MIT Lincoln Laboratory. Three fully-fabricated 2D circuit wafers are stacked using standard CMOS fabrication techniques including thin-film planarization, layer alignment and oxide bonding. Micron-scale dense 3D vias are fabricated to interconnect circuits between tiers. Ionizing dose and single event effects are discussed for proton irradiation with energies between 4.8 and 500 MeV. Results are compared with 14-MeV neutron irradiation. Single event upset cross section, tier-to-tier and angular effects are discussed. The interaction of 500-MeV protons with tungsten interconnects is investigated using Monte-Carlo simulations. Results show no tier-to-tier effects and comparable radiation effects on 2D and 3D SRAMs. 3DIC technology should be a good candidate for fabricating circuits for space applications.

The amounts of charge collection by single-photon absorption (SPA) and by two-photon absorption (TPA) laser testing techniques have been directly compared using specially made SOI diodes. For SPA measurements and some TPA measurements, the back substrates of the diodes were removed by etching with XeF2. With the back substrates removed, the amount of TPA induced charge collection can be correlated to the amount of SPA induced charge collection. There are significant differences, however, in the amount of TPA induced charge collection for diodes with and without substrates. For the SOI diodes of this study, this difference appears to arise from several contributions, including nonlinear-optical losses and distortions that occur as the pulse propagates through the substrate, as well as displacement currents that occur only when the back substrate is present. These results illustrate the complexity of interpreting TPA and SPA single-event upset measurements.

The effects of moisture on radiation-induced charge buildup in the oxides of a 0.35 μm SOI technology are explored. Data show no observable effects of moisture-related aging on radiation hardness. These results are in contrast to those of previous work performed on bulk MOS technologies fabricated in the 1980s. The cause of these differences do not appear to be due to differences in final chip passivation layers. Instead, other processing variables (including the use of different implant materials and thicker overlayers) may account for these differences. In any case, the SOI technology results indicate that not all advanced technologies exposed to moisture are necessarily susceptible to significant long-term radiation-induced aging effects.

The feasibility of developing an embeddable silicon-on-insulator (SOI) buried oxide MOS dosimeter (RadFET) has been demonstrated. This dosimeter takes advantage of the inherent properties for radiation-induced charge buildup in the buried oxides of commercial SOI wafers. Discrete SOI buried oxide RadFETs and fully-functional read-out circuitry have been fabricated in Sandia's CMOS7 radiation-hardened SOI technology. Discrete RadFETs have been irradiated under various radiation conditions and subjected to post-irradiation anneals. Data show only a small dose rate dependence and less than a 10% annealing or fade of the dosimeters output characteristics when irradiated with all pins shorted. These results show less fade than dual-dielectric RadFETs irradiated under the same bias conditions and support the use of SOI buried oxide RadFETs for low dose rate applications. Read-out circuitry has also been designed and fabricated to monitor changes in the ?off? state leakage current induced by radiation-induced charge buildup in the buried oxide dosimeter. The analog-to-digital output from the read-out circuit changes linearly with the ?off? state leakage current. Preliminary radiation characterizations of the read-out circuitry show no spurious effects of radiation-induced charge buildup in the read-out circuitry on the dosimeter output. These results indicate it is feasible to develop an embeddable SOI buried oxide RadFET as an attractive choice for many low power, low dose rate applications requiring real-time knowledge of total ionizing dose radiation levels.

Gate-all-around MOSFETs were fabricated from single-crystal silicon nanowires as small as 500 A? across. The response to x-rays was measured for transistors with various gate oxide thicknesses, a variety of physical designs, and several different electric fields during irradiation. While the devices are otherwise very well behaved, the total dose degradation is larger than expected and is attributable to thicker, non-uniform gate oxide grown on non-(100) Si surfaces of the nanowires.

The radiation response of lateral power MOSFETs in total dose and energetic particle environments is explored. Results indicate that lateral power MOSFETs can be quite susceptible to single-event burnout. Tradeoffs involved in developing radiation hardened lateral power MOSFETs for point-of-load applications are studied using experiments and device simulations. Both design and fabrication process techniques can be used to significantly improve the single-event effect performance of lateral power MOSFETs, but the trade space between electrical and radiation performance must be carefully considered to produce an optimized design for point-of-load applications.

Experimental results are presented on proton induced single-event-upsets (SEU) on a 65 nm silicon-on-insulator (SOI) SRAM. The low energy proton SEU results are very different for the 65 nm SRAM as compared with SRAMs fabricated in previous technology generations. Specifically, no upset threshold is observed as the proton energy is decreased down to 1 MeV; and a sharp rise in the upset cross-section is observed below 1 MeV. The increase below 1 MeV is attributed to upsets caused by direct ionization from the low energy protons. The implications of the low energy proton upsets are discussed for space applications of 65 nm SRAMs; and the implications for radiation assurance testing are also discussed.

It is shown that protons and neutrons can induce enhanced degradation in power MOSFETs, including both trench and planar geometry devices. Specifically, large shifts in current-voltage characteristics can be observed at extremely low proton total dose levels (as low as ~ 2 rad(SiO2)). These shifts can induce significant increases in device ldquooffrdquo state leakage current. Neutron irradiations show similar degradation at equivalent fluence levels, even though neutrons do not deposit dose due to direct ionization. These data suggest that the mechanism responsible for the enhanced degradation is a microdose effect associated with secondary particles produced through nuclear interactions between protons and neutrons and the materials in integrated circuits. The secondary particles deposit enough charge in the gate oxide to induce a parasitic drain to source leakage path in the transistor. Although the results are demonstrated here for only trench and planar geometry power MOSFETs, microdose effects can impact the radiation response of other integrated circuit types. Hardness assurances issues implications are discussed.

For the first time, NROM-style nonvolatile memory elements were fabricated in SOI and irradiated. Total dose characterizations of these transistors indicate that this new style of memory can be functional to at least 500 krad (SiO2).

Transistors and ICs built in several different captive and commercial facilities were exposed to moisture, irradiated, and annealed. The moisture exposures were performed using highly accelerated stress test (HAST) at 130degC and 85% relative humidity. Irradiation of n-channel transistors exposed to HAST followed by a long-term anneal resulted in some increase in interface-trap and oxide-trapped charge buildup. However, exposing p-channel transistors to HAST preirradiation resulted in extremely large and unexpected voltage shifts immediately following irradiation. They were observed for devices with either doped oxide or nitride final chip passivation. Because of this, nitride passivation may not be sufficient to prevent H2O from causing enhanced radiation-induced degradation over long time periods in some devices (e.g., commercial devices with nitride final chip passivation packaged in plastic packages). The smaller voltage shifts for the n-channel transistors may be related to the formation of phosphosilicate glass (PSG) overlying the sources and drains of the n-channel transistors impeding the diffusion of moisture to the gate oxides. It is shown that, the large radiation-induced voltage shifts for the p-channel transistors can lead to enhanced IC parametric degradation and functional failure at lower radiation levels. Large increases in radiation-induced field oxide leakage current were also observed for transistors exposed to HAST preirradiation. Transistors were also annealed (prior to irradiation) and irradiated in H2. Approximately the same level of radiation-induced degradation was observed for n- and p-channel transistors suggesting that the diffusion kinetics for H2 diffusion are considerably different than for H2O diffusion. These results raise the concern that exposure of devices to moisture or hydrogen can lead to long-term radiation-induced aging effects.

The generation and propagation of single event transients (SET) is measured and modeled in SOI inverter chains with different designs. SET propagation in inverter chains induces significant modifications of the transient width. In some cases, a "propagation-induced pulse broadening" (PIPB) effect is observed. Initially narrow transients, less than 200 ps at the struck node, are progressively broadened up to the nanosecond range, with the degree of broadening dependent on the transistor design and the length of propagation. The chain design (transistor size and load) is shown to have a major impact on the transient width modification.

International audience; Abstract—We characterized the responses of three erbium-doped fibers with slightly different concentrations of rare-earth ions (240–290 ppm) and Al2O3 (7–10 wt.%) during proton and gamma-ray exposures. We have simultaneously measured the radiation-induced attenuation (RIA) around the Er3+ ion pumping wavelength (980 nm) and the associated changes of the Er3+ emission around 1530 nm. The three erbium-doped fibers show similar radiation responses. All fibers exhibit RIA levels between 9 10-3 and 1.7 10-2 dB m-1 Gy-1 at 980 nm and between 4 10-3 and 1.1 10-2 dB m-1 Gy-1 at 1530 nm. Protons and gamma-rays lead to similar radiation damages, with small differences between the protons of different energies (50 MeV and 105 MeV). Furthermore, we have performed online measurements of the spectral dependence of RIA from 600 to 1600 nm and offline measurements from 1200 to 2400 nm. The three fibers exhibit the same spectral response. Losses decrease monotonically from the visible to the infrared part of the spectrum. We have performed spectral decomposition of these RIA curves with the help of absorption bands previously associated with radiation-induced point defects. Our analysis shows that the main part of the RIA (600–1700 nm) in erbium-doped glass can be explained by the generation of Al-related point defects. The other defects related to the germanium and phosphorus doping of the silica seem to have a lower contribution to the induced losses. The Er3+ ion properties seem to be mainly unaffected by proton exposure, suggesting a solvation shell around the Er3+ ion formed by Al2O3 species.

Transistors and ICs were irradiated at dose rates from 0.2 to 2times109 rad(SiO2)/s using a wide range of radiation sources. The mechanisms causing parametric IC failure varied with dose rate. At low dose rates from 0.2 to 100 rad(SiO2)/s, parametric IC failure in these devices was dominated by radiation-induced degradation of the gate oxide transistors. At dose rates from 1.8times103 to 106 rad(SiO2)/s, parametric IC degradation was dominated by large increases in radiation-induced parasitic field oxide leakage current. At very high dose rates of 2times109 rad(SiO2)/s, no parametric failure was observed due to debiasing effects caused by rail-span collapse. These differences in dose rate response can make hardness assurance testing for high dose rate environments very challenging. Simple ldquoovertestsrdquo at dose rates from 50 to 300 rad(SiO2)/s may greatly underestimate the radiation hardness of ICs in high dose rate environments. Because the failure mechanism may vary with dose rate, circuit design, and/or device technology, the best procedure for ensuring IC radiation hardness in greater than 300 rad(SiO2)/s environments is to use radiation sources that mimic the system environment.

We irradiated floating gate (FG) memories with nor and nand architecture by using different TID sources, including 2 MeV, 98 MeV, and 105 MeV protons, X-rays, and Upsi-rays. Two classes of phenomena are responsible for charge loss from programmed FGs: the first is charge generation, recombination, and transport in the dielectrics, while the second is the emission of electrons above the oxide band. Charge loss from programmed FGs irradiated with protons of different energy closely tracks results from Upsi-rays, whereas the use of X-rays results in dose enhancement effects.

The radiation hardness of nominally identical SRAM test chips fabricated in five commercial foundries is examined. Large variations in single-event latchup and total dose response are observed. The softest SRAMs fail functionally at ~200 krad(SiO2) and have a fairly large single-event latchup cross section. This is in contrast to the hardest foundry split which is nearly immune to single-event latchup at room temperature, and remains functional to a total dose of 400 krad(SiO 2). Three of the splits show a similar increase in radiation induced leakage current, which is dependent on both the characterization bias as well as the pattern written to the memory array. The other two splits show neither a pattern nor a bias dependence on the leakage current. Heavy-ion microbeam experiments confirm that the most latchup sensitive area of these SRAMs is the peripheral circuitry, not the memory array itself. Qualification and hardened-by-design integrated circuit implications are discussed

The type of final chip passivation layer used to fabricate linear bipolar circuits can have a major impact on the total dose hardness of some circuits. It is demonstrated that National Semiconductor Corporation linear bipolar devices fabricated with only an amorphous silicon carbide passivation layer do not exhibit enhanced low-dose-rate sensitivity (ELDRS), while devices from the same production lot fabricated with other types of passivation layers are ELDRS sensitive. SiC passivation possesses mechanical, electrical and chemical properties that make it compatible with linear device fabrication processes. These properties of SiC passivation layers, combined with the excellent radiation response of devices passivated with SiC, make SiC passivation layers a very attractive choice for devices packaged in either ceramic or plastic-encapsulated packages for use in space environments

The effect of total dose on SEU hardness is investigated as a function of temperature and power supply voltage to determine worst-case hardness assurance test conditions for space environments. SRAMs from six different vendors were characterized for single-event upset (SEU) hardness at proton energies from 20 to 500 MeV and at temperatures of 25 and 80degC after total dose irradiating the SRAMs with either protons, Co-60 gamma rays, or low-energy x-rays. It is shown that total dose irradiation and the memory pattern written to the memory array during total dose irradiation and SEU characterization can substantially affect SEU hardness for some SRAMs. For one SRAM, the memory pattern made more than two orders of magnitude difference in SEU cross section at the highest total dose level examined. For all SRAMs investigated, the memory pattern that led to the largest increase in SEU cross section was the same memory pattern that led to the maximum increase in total-dose induced power supply leakage current. In addition, it is shown that increasing the temperature during SEU characterization can also increase the effect of total dose on SEU hardness. As a result, worst-case SEU hardness assurance test conditions are the maximum total dose and temperature of the system environment, and the minimum operating voltage of the SRAM. Possible screens for determining whether or not the SEU cross section of an SRAM will vary with total dose, based on the magnitude of the increase in power supply leakage current with total dose or the variation in SEU cross section with power supply voltage, have been suggested. In contrast to previous works, our results using selective area x-ray irradiations show that the source of the effect of total dose on SEU hardness is radiation-induced leakage currents in the memory cells. The increase in SEU cross section with total dose appears to be consistent with radiation-induced currents originating in the memory cells affecting the output bias levels of bias level shift circuitry used to control the voltage levels to the memory cells and/or due to the lowering of the noise margin of individual memory cells caused by radiation-induced leakage currents

Complementary bipolar and MOS characterization techniques, specifically the gate sweep (GS) and sub-threshold sweep (SS), are used to estimate the radiation induced oxide charge (N/sub ot/) and interface trap (N/sub it/) buildup in gated bipolar test devices. The gate sweep and sub-threshold sweep data from recent TID testing of gated lateral PNP devices suggests an asymmetric energy distribution of interface traps after ionizing radiation exposure. Charge pumping (CP) experiments were done on the test devices to estimate the energy distribution of interface traps induced by radiation. The CP results are used in this paper to confirm the analytical findings from the GS and SS techniques and solidify the use of the complementary method as a simple way of determining radiation induced interface trap distribution in gated bipolar devices.

The total dose hardness of several commercial power MOSFET technologies is examined. After exposure to 20 krad(SiO/sub 2/) most of the n- and p-channel devices examined in this work show substantial (2 to 6 orders of magnitude) increases in off-state leakage current. For the n-channel devices, the increase in radiation-induced leakage current follows standard behavior for moderately thick gate oxides, i.e., the increase in leakage current is dominated by large negative threshold voltage shifts, which cause the transistor to be partially on even when no bias is applied to the gate electrode. N-channel devices biased during irradiation show a significantly larger leakage current increase than grounded devices. The increase in leakage current for the p-channel devices, however, was unexpected. For the p-channel devices, it is shown using electrical characterization and simulation that the radiation-induced leakage current increase is related to an increase in the reverse bias leakage characteristics of the gated diode which is formed by the drain epitaxial layer and the body. This mechanism does not significantly contribute to radiation-induced leakage current in typical p-channel MOS transistors. The p-channel leakage current increase is nearly identical for both biased and grounded irradiations and therefore has serious implications for long duration missions since even devices which are usually powered off could show significant degradation and potentially fail.

Under conditions that were predicted as "safe" by well-established TCAD packages, radiation hardness can still be significantly degraded by a few lucky arsenic ions reaching the gate oxide during self-aligned CMOS source/drain ion implantation. The most likely explanation is that both oxide traps and interface traps are created when ions penetrate and damage the gate oxide after channeling or traveling along polysilicon grain boundaries during the implantation process.

著者人数：15名, 資料番号: SA1002017000

This work investigates the charge collection mechanisms occurring in heavy ion irradiated metal oxide semiconductor (MOS) devices. The parasitic bipolar effect, inherent to the structure of SOI transistors, is shown to exist in bulk NMOS transistors as well. We experimentally show that the drain junction of an OFF-state bulk MOS transistor collects more charge than an identical junction isolated from neighboring elements. In other words, the proximity of the source junction and the triggering of the bipolar-like structure are responsible of charge amplification. A higher current peak on the drain is observed, and this enhancement effect is high enough to invalidate usual charge collection models based only on funnel and diffusion transport. Thus, the proximity of other junctions has to be considered to improve charge collection model in bulk technologies.

The post-irradiation annealing behavior of total dose degradation in LM139 comparators fabricated in National Semiconductor Corporation's (NSC) enhanced low-dose-rate sensitive (ELDRS) linear bipolar technology is examined. Data show that a large fraction of the radiation-induced increase in input bias current recovers after a 100/spl deg/C anneal. The recovery in input bias current is linked to a significant amount of interface-trap annealing at 100/spl deg/C. This is qualitatively consistent with previous data on interface-trap annealing and recent models for interface-trap annealing associated with hydrogen motion at the silicon/silcon dioxide interface. The annealing results have implications for hardness assurance testing. If the radiation induced charge that is responsible for ELDRS (whether it be interface or border traps) can anneal at 100/spl deg/C, these data suggest that elevated temperature irradiations sometimes used to bound the ELDRS response of ICs may also cause some annealing of radiation-induced charge. These data help explain why high-dose-rate irradiations at elevated temperatures in some cases underestimate low-dose-rate degradation. In addition, these data confirm that high-dose-rate irradiations followed by elevated temperature anneals do not mimic the mechanisms that cause enhanced degradation at low dose rates in devices with ELDRS.

Mechanisms for single-event gate rupture (SEGR) in MOS capacitors and linear integrated circuits (ICs ) are explored at ion energies greater than 1 GeV. We find that SEGR thresholds depend strongly on ion energy, but are independent of oxide defects, bias polarity, doping concentration, and ionizing dose. The number of SEGR strikes across a MOS capacitor was measured, and the SEGR response cross section distinctly shows an electric field threshold. The importance of having stiffening and speedup capacitors at the device is discussed.

The high and low dose rate responses of bipolar transistors in a bipolar linear circuit process technology have been studied with specially designed gated lateral pnp test transistors that allow for the extraction of the oxide trapped charge (N/sub ot/) and interface trap (N/sub it/) densities. The buildup of N/sub ot/ and N/sub it/ with total dose is investigated as a function of the irradiation gate voltage at 39 rad/s and 20 mrad/s for three variations of the final passivation layer (all variations had the same oxide covering the active region of the devices). The three variations in final passivation were selected to exhibit minimal degradation at high and low dose rate (no passivation), significant degradation at high and low dose rate (p-glass/nitride) and enhanced low dose rate sensitivity (ELDRS) (p-glass only). It is shown that the increase in base current is dominated by increased N/sub it/ and the "true" low dose rate enhancement in the ELDRS parts occurs for zero and negative gate voltage, but is eliminated for large positive gate voltage and elevated temperature irradiation. Implications for ELDRS models are discussed.

Implanting the buried oxide of silicon-on-insulator technologies can create electron traps throughout the buried oxide that can compensate the buildup of radiation-induced positive charge. These can be used as an effective method for total-dose hardening buried oxides in SOI devices. In this work, we show that implanting buried oxides can also create thermally activated metastable electron traps near the top Si/SiO2 border. These metastable electron traps can produce significant bias instabilities in the back-gate transistor characteristics and lead to threshold voltage instabilities in fully-depleted devices.

The radiation response and long term reliability of alternative gate dielectrics will play a critical role in determining the viability of these materials for use in future space applications. The total dose radiation responses of several near and long term alternative gate dielectrics to SiO 2 are discussed. Radiation results are presented for nitrided oxides, which show no change in interface trap density with dose and oxide trapped charge densities comparable to ultra thin thermal oxides. For aluminum oxide and hafnium oxide gate dielectric stacks, the density of oxide trapped charge is shown to depend strongly on the film thickness and processing conditions. The alternative gate dielectrics discussed here are shown to have effective trapping efficiencies that are up to ∼15 to 20 times larger than thermal SiO 2 of equivalent electrical thickness. A discussion of single event effects in devices and ICs is also provided. It is shown that some alternative gate dielectrics exhibit excellent tolerance to heavy ion induced gate dielectric breakdown. However, it is not yet known how irradiation with energetic particles will affect the long term reliability of MOS devices with high- κ gate dielectrics in a space environment.

Silicon-on-insulator (SOI) technologies, have been developed for radiation-hardened applications for many years and are rapidly becoming a main-stream commercial technology. The total dose response of SOI devices is more complex than for bulk-silicon devices due to the buried oxide. Radiation-induced trapped charge in the buried oxide can increase the leakage current of partially-depleted transistors and decrease the threshold voltage and increase the leakage current of fully-depleted transistors. We review process and design techniques that have been developed to reduce the net amount of radiation-induced positive charge trapped in the buried oxide or to mitigate the effects of trapped charge in the buried oxide, respectively. We also compare the total dose response of devices operated in single-gate (SO) and double-gate (DG) mode as a function of silicon film thickness. DG-MOSFETs are systematically less sensitive to radiation-induced trapped charge and interface trap.

We examine the total-dose radiation response of capacitors and transistors with stacked Al/sub 2/O/sub 3/ on oxynitride gate dielectrics with Al and poly-Si gates after irradiation with 10 keV X-rays. The midgap voltage shift increases monotonically with dose and depends strongly on both Al/sub 2/O/sub 3/ and SiO/sub x/N/sub y/ thickness. The thinnest dielectrics, of most interest to industry, are extremely hard to ionizing irradiation, exhibiting only /spl sim/50 mV of shift at a total dose of 10 Mrad(SiO/sub 2/) for the worst case bias condition. Oxygen anneals are found to improve the total dose radiation response by /spl sim/50% and induce a small amount of capacitance-voltage hysteresis. Al/sub 2/O/sub 3//SiO/sub x/N/sub y/ dielectrics which receive a /spl sim/1000/spl deg/C dopant activation anneal trap /spl sim/12% more of the initial charge than films annealed at 550/spl deg/C. Charge pumping measurements show that the interface trap density decreases with dose up to 500 krad(SiO/sub 2/). This surprising result is discussed with respect to hydrogen effects in alternative dielectric materials, and may be the result of radiation-induced hydrogen passivation of some of the near-interfacial defects in these gate dielectrics.

This paper analyzes the collected charge in heavy ion irradiated MOS structures. The charge generated in the substrate induces a displacement effect which strongly depends on the capacitor structure. Networks of capacitors are particularly sensitive to charge sharing effects. This has important implications for the reliability of SOI and DRAMs which use isolation oxides as a key elementary structure. The buried oxide of present day and future SOI technologies is thick enough to avoid a significant collection from displacement effects. On the other hand, the retention capacitors of trench DRAMs are particularly sensitive to charge release in the substrate. Charge collection on retention capacitors participate to the MBU sensitivity of DRAM.

It is shown that final chip passivation layers can have a significant impact on total dose hardness. A number of final chip passivation layers are evaluated to identify films that mitigate enhanced low-dose-rate sensitivity (ELDRS) in National Semiconductor Corporation's linear bipolar technologies. It is shown that devices fabricated with either a low temperature oxide or a tetraethyl ortho silicate passivation do not exhibit significant ELDRS effects up to 100 krad(SiO/sub 2/). Passivation studies on CMOS SRAMs suggest that it is unlikely that the passivation layers (or processing tools) are acting as a new source of hydrogen, which could drift or diffuse into the oxide and increase ELDRS sensitivity. Instead, it is possible that the passivation layers affect the mechanical stress in the oxide, which may affect oxide trap properties and possibly the release and mobility of hydrogen. Correlations between mechanical stress induced by the passivation layers and radiation degradation are discussed.

Focused ion microbeam and broadbeam heavy-ion experiments on capacitors and SRAMs are used to investigate increased saturation upset cross sections recently observed in some silicon-on-insulator (SOI) integrated circuits (ICs). Experiments performed on capacitors show a very strong bias and oxide thickness dependence for charge collection. In combination with three-dimensional (3-D) simulations, these data suggest that the mechanism for charge collection in capacitors is due to perturbation of the substrate electric fields by charge deposition in the substrate. For substrates biased in depletion, these perturbations induce displacement currents through the oxide. Charge collection by displacement currents can be substantially reduced or mitigated by using heavily doped substrates. Experiments performed on SRAMs also show enhanced charge collection from displacement currents. However, experimental data and 3-D simulations show that for SRAMs, a second mechanism also contributes to charge collection. The 3-D simulations suggest that the charge collection results from drain and body-tie heavy-ion strikes within a few tenths of a micron of the body-to-drain junctions. These charge collection mechanisms can substantially reduce the SEU hardness and soft-error reliability of commercial SOI ICs.

Final chip passivation layers are shown to have a major impact on the total dose hardness of bipolar linear technologies. It is found that devices fabricated without passivation layers do not exhibit enhanced low-dose-rate sensitivity (ELDRS) or pre-irradiation elevated-temperature stress (PETS) sensitivity, whereas devices from the same production lot fabricated with either oxide/nitride or doped-glass passivation layers are ELDRS and PETS sensitive. In addition, removing the passivation layers after fabrication can mitigate ELDRS and PETS effects. ELDRS and PETS effects do not appear to be inherently related to circuit design or layout, but are related to mechanical stress effects, hydrogen in the device, or a combination of the two. These results suggest that proper engineering of the final chip passivation layer might eliminate ELDRS and PETS effects in bipolar integrated circuits.

High-energy ion-irradiated 3.3-nm oxynitride film and 2.2-nm SiO/sub 2/-film MOS capacitors show premature breakdown during subsequent electrical stress. This degradation in breakdown increases with increasing ion linear energy transfer (LET), increasing ion fluence, and decreasing oxide thickness. The reliability degradation due to high-energy ion-induced latent defects is explained by a simple percolation model of conduction through SiO/sub 2/ layers with irradiation and/or electrical stress-induced defects. Monitoring the gate-leakage current reveals the presence of latent defects in the dielectric films. These results may be significant to future single-event effects and single-event gate rupture tests for MOS devices and ICs with ultrathin gate oxides.

A radiation-tolerant bipolar-voltage comparator experienced severe degradation of radiation hardness when layout of the part was redrawn and the process moved from a 4-in wafer to a 6-in wafer line. The reasons for the loss in hardness are identified, and it is shown that modifications to the design layout eliminate the problem.

Silicon-on-insulator (SOI) and bulk-silicon transistors were irradiated using X-ray, Co-60 gamma, and proton radiation sources. Co-60 gamma irradiation generates larger radiation-induced threshold voltage shifts (by a factor of two) in SOI buried oxides and in parasitic field oxides under low-field conditions than X-ray or proton irradiation. For all devices examined, the radiation-induced threshold voltage shifts generated by X-ray irradiation were equal to, within experimental uncertainty, the radiation-induced threshold voltage shifts generated by proton irradiation. The differences in threshold voltage shifts for the different radiation sources are attributed to differences in stopping power and consequently charge yield. The results suggest that for simulating proton-rich space environments, X-ray laboratory radiation sources are better suited for hardness assurance testing than Co-60 gamma radiation sources. Using Co-60 gamma sources for hardness assurance testing will result in more conservative estimates of device failure levels. Thus, our results do not preclude the use of Co-60 gamma radiation sources for hardness assurance testing for proton-rich environments. For electron-rich space environments, Co-60 gamma radiation sources may be better suited for hardness assurance testing.

The effects of substrate and epitaxial-layer thickness on the single-event upset and single-event latchup response of integrated circuits are studied using experiments and three-dimensional device simulations. Reducing substrate thickness can be an effective method for improving single-event upset and latchup immunity, but only if devices are thinned beyond their epitaxial-layer thickness. Increases in overall single-event upset threshold linear energy transfer of more than a factor of two are predicted after thinning to a wafer thickness of 0.5 /spl mu/m. Simulations predict that the single-event latchup performance of a thinned integrated circuit will be similar to that of the same integrated circuit fabricated on an epitaxial substrate of equivalent thickness. By combining wafer thinning with backside contact formation, more significant improvements in the single-event latchup threshold can be obtained.

Submicron nonvolatile memory transistors were fabricated by exposing silicon-on-insulator (SOI) buried oxides to hydrogen at elevated temperatures to generate mobile protons in the buried oxides. By switching the polarity of the bias to the SOI substrate, the mobile protons in the buried oxide were transported to either the top or bottom Si–buried oxide interface, switching the leakage current of top gate transistors from an ON to an OFF state.

Silicon-on-insulator (SOI) technology exhibits three main advantages over bulk silicon technology for use in radiation environments. (1) SOI devices are immune to latchup, (2) the volume of the sensitive region (body) and hence total charge collection per transient irradiation is much reduced in SOI devices and (3) the insulating layer blocks charge collection from the substrate (i.e., no funneling effect). This effectively raises the single event upset (SEU) threshold for the SOI device. However, despite their small active volume SOI devices are still vulnerable to single event effects (SEE). Inherent in the SOI transistor design is a parasitic npn bipolar junction transistor (BJT), where the source-body-drain acts as an emitter-base-collector BJT. An ion strike to a floating (not referenced to a specific potential) body creates a condition where the excess minority carriers in the drain-body cause the parasitic BJT to turn on and inject more charge into the drain than was deposited in the device by the ion. In extreme cases the floating body effect (FBE) can trigger a high-current state called single-event snapback (SES) where channel conduction is sustained indefinitely through regenerative electron-impact ionization near the drain junction. Tying the body to the source limits the emitter-base current and reduces the sensitivity of the device to single ion strikes. Unfortunately, the body-tie loses effectiveness with distance due to resistivity, and in regions far enough from the tie the BJT is still in effect. Using the Sandia nuclear microprobe we have created charge collection maps on Sandia CMOS6rs SOI FETs of varying channel widths. These devices have body ties at both ends of the channel region. Results clearly demonstrate that distance of the ion strike from the body tie has an inverse effect upon charge collection and SES sensitivity due to the resistivity of the channel. Experimental results compare well with DAVINCI simulations and electrically induced snapback thresholds. In addition, an interesting saturation effect of SES versus the amount of injected charge is observed.

Large differences in charge buildup in SOI buried oxides are observed for X-ray and Co-60 irradiations of SIMOX and Unibond transistors. The Co-60 response is typically worse than the X-ray response. These results are consistent with expectations derived from previous work on the relative charge yield versus field in thick oxides. The effects of bias configuration and substrate type on charge buildup and hardness assurance issues are explored via experiments and simulation. The worst-case bias condition is found to be either the off-state or transmission gate configuration. Simulations of the buried oxide electric field in the various bias configurations are used to illustrate the factors that affect charge transport and trapping in the buried oxides. Hardness assurance implications are discussed.

The characteristics of ion-induced charge collection and single-event upset are studied in silicon-on-insulator (SOI) transistors and circuits with various body tie structures. Impact ionization effects, including single-event snapback, are shown to be very important. Focused ion microbeam experiments are used to find single-event snapback drain voltage thresholds in n-channel SOI transistors as a function of device width. Three-dimensional device simulations are used to determine single-event upset and snapback thresholds in SOI SRAMs, and to study design tradeoffs for various body-tie structures. A window of vulnerability to single-event snapback is shown to exist below the single-event upset threshold. The presence of single-event snapback in commercial SOI SRAMs is confirmed through broadbeam ion testing, and implications for hardness assurance testing of SOI integrated circuits are discussed.

The worst case bias during total dose irradiation of partially depleted SOI transistors from two technologies is correlated to the device architecture. Experiments and simulations are used to analyze SOI back transistor threshold voltage shift and charge trapping in the buried oxide.

A pre-irradiation elevated-temperature stress is shown to have a significant impact on the radiation response of a linear bipolar circuit. Thermal cycling can lead to part-to-part variability in the radiation response of circuits packaged from the same wafer. In addition, it is demonstrated that a pre-irradiation elevated-temperature stress can significantly impact the enhanced low dose rate sensitivity (ELDRS) of the LM111 voltage comparator. Thermal stress moderates and, in some cases, eliminates ELDRS. The data are consistent with space charge models. These results suggest that there may be a connection between the mechanisms responsible for thermal-stress effects and ELDRS in linear circuits. Implications of these results for hardness assurance testing and mechanisms are discussed.