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In this work, we study and characterize the layout-induced device strain and its impact on RF performance of 22-nm-ultrathin body and buried oxide fully depleted silicon-on-insulator (UTBB FDSOI) P-channel field-effect transistor (PFET). This will help in boosting and optimizing the RF performance for the targeted application. With shrinking device dimensions, conventional stress liners and embedded stressors used in strain-engineered CMOS devices become less effective. Therefore, intrinsically strained materials, such as compressively strained SiGe, are widely used to boost the holes’ mobility in the channel. The stress level depends on both the manufacturing process and device geometry, and the optimization of these leads to improved dc and RF performances of PFET devices. We hereby study various layout parameters, such as width and length of the active region, contacted poly pitch, number of fingers, and source/drain contact, to maximize the channel uniaxial strain parallel to the current flow direction and, thus, improve the electrical performances. The studied layout parameters are then applied on sliced-active (RX) structures, which enables to achieve up to 30% improvement of both ${f}_{T}$ and ${f}_{\text {MAX}}$ parameters of SiGe PFET with respect to a reference device. This also allows reducing the parasitic capacitance without significantly degrading the dc performance. The device strain modeling and physical characterization were conducted through the finite-element method (FEM) and nanobeam electron diffraction (NBED) in the transmission electron microscopy (TEM), respectively.

In this work buried channel devices were successfully integrated in HKMG. Analog, noise and reliability performance have been reported and compared to a surface device. The devices were processed to have the same V Tsat for the nominal geometry of a corresponding surface device. Advantages and drawbacks of the two integrations are discussed and explained with the support of calibrated TCAD simulations.

This paper proposes three methods of reducing device gate resistance and parasitic capacitance while boosting transconductance of MOSFET on 22FDX®. The f MAX can be improved by 50% and up to 75% for NFET and PFET with respect to a standard 2.0µm finger width layout, respectively.

In this work we revisited the 22nm FDSOI technology for lowest power IoT, RF and mmWave applications. Ultra-low leakage and power devices are described, as part of the 22FDX® portfolio. Transistors performance is presented. N-FET (p-FET) drive current of 910μA/μm (856μA/μm) at 0.8V and 100pA/μm Ioff are reported fulfilling the requirements for ultra-low power and leakage design space. Excellent low noise is shown due to the suppressed RDF coming from the un-doped silicon channel. Superior fT and fmax have been measured on CMOS and LDMOS devices. 347GHz n-FET fT and 371GHz fmax were achieved on thin oxide CMOS devices. Simple PA circuit results are reported to highlight the benefit of 22FDX® technology for RF and mmWave applications. In conclusion, an outlook of the scalability as well as novel process integrations are discussed.

We report for the first time the implementation of SiGe buried stressors in a foundry production process at 28 nm and the observation of an additional benefit of improved short channel behavior (reduced DIBL) that results in at least 15% improvement in Idlin-Ioff independent of any benefit obtained from tensile strain. For RF applications, fT is projected to improve by at least 40% in n-MOSFETs with SiGe buried stressor.

We propose an original Technology/Design Co-optimization of standard cells mixing devices of different threshold voltages (V T -flavors) within a cell. It is successfully applied with nMOS Low-V T (LVT) and pMOS Super-Low-V T (SLVT) in Ultra-Low-Voltage (ULV) Fully Depleted Silicon-On-Insulator (FDSOI) LETI standard cells using diffusion breaks. It enables adjusting the V T of pMOS subject to SiGe-channel-induced Local Layout Effect (LLE); leading experimentally to a 23% frequency gain on 22nm FDSOI technology for a 2-finger inverter Ring Oscillator (IVSX2 RO) vs. reference LVT at the same static leakage and V DD =0.4V supply voltage; which corresponds to the Minimum Energy Point (MEP). This solution is combined with Forward Body Biasing (FBB), which brings +253% frequency at V DD =0.4V and FBB=1.6V and improves the energy efficiency with a −13% minimum Energy Delay Product (EDP) along with a 50mV V DD reduction at the minimum EDP.

Strained silicon channels are one of the most important Technology Boosters for further Si CMOS developments. The mobility enhancement obtained by applying appropriate strain provides higher carrier velocity in MOS channels, resulting in higher current drive under a fixed supply voltage and gate oxide thickness. The physical mechanism of mobility enhancement, methods of strain generation and their application for advanced VLSI devices is reviewed.

Different gate stack optimizations and substrate dependent strain interactions have been studied and implemented in a cost-effective 28nm VLSI ultra low power technology. Drive current improvements for NFET ID,SAT = 870μA/μm and PFET ID,SAT = 465μA/μm at IOFF = 1nA/μm and VDS = 1V can be demonstrated by using compressive and tensile contact layers on (100)/ substrates. Work function optimizations result in a proper threshold voltage adjustment and improved reliability behavior for 28nm ultra low power technologies. SOC level test design implementations show consistent yield as well as improved performance.

This 3-D TCAD study demonstrates a new stress element by strained isolation oxide for Tri-Gate and similar FinFET structures. The simulation shows an uniform improvement of N- and PMOS drive current (10 %) by using a tensile strained isolation material between the fins processed on standard (100) bulk wafer with channel direction. Therefore it is a simple low-cost stress method for Tri-Gate and FinFET structures of 22nm technologies and beyond. The main stress direction is located along the channel width with a maximum near the pn-junctions. The stress effect can be improved further with reduced gate length which shows the compatibility of strained isolation oxide to future transistor generations.

In this paper we present, an overview of partial depleted Silicon on Insulator (PD SOI) CMOS transistor technologies for high performance microprocessors. To achieve a “high performance per watt” figure of merit, transistor technology elements like PD SOI, strained Si, aggressive junction scaling, asymmetric devices need hand-in-hand development with multiple core- and power efficient designs. These techniques have been developed, applied and optimized for 65/45nm volume manufacturing at GLOBALFOUNDRIES in Dresden. To enable further transistor scaling to 32nm design rules, High K Metal Gate (HKMG) technology is key. Different HKMG integrations as well as future strained Si technologies like strained silicon directly bonded on SOI and embedded Si:C are discussed.

The influence of line edge and gate interface roughness on SOI-MOSFET performance is studied by simulation. Both types of roughness were implemented in the device simulator SIMBA through the Fourier synthesis approach and the simulations were performed with the drift diffusion and the quantum drift diffusion models. Scaled transistors showed more sensitivity to rough interfaces with shallow junctions.

Two distinct stress memorization phenomena in advanced SOI CMOS are reported in this work. Both require a capping layer and anneal, but can be categorized as techniques 1) requiring an amorphized source/drain region and low temperature anneal, and 2) requiring a high temperature anneal, independent of the crystalline state of the Si. Both improve NMOS drive current, and the resulting improvements are additive to >27% NMOS IDSAT improvement. The first phenomenon is previously unreported. It has been identified to be localized in the source/drains, and yields more improvement with multiple offset implantation prior to capping and annealing.

The influence of technological parameters on the capacitive gate insulator thickness and the electrical transistor behavior of different technology nodes were simulated. Starting from calibrated PD- SOI-Transistors, designed for the 130 nm technology, scaled 45 nm technology transistors were examined. The inverter propagation delay time and corresponding saturation drive currents of different technologies with varying gate insulator thicknesses were compared under the aspect of manufacturability. Further improvements due to the implementation of metal gates were estimated.