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A method for two-dimensional carrier profiling is presented, based on tunneling from a conducting atomic-force microscope (AFM) probe tip to a semiconductor sample. Current–voltage data are taken during the AFM scan on a cross-sectioned sample consisting of epitaxial InP multilayers. The results show a clear dependence of the current–voltage characteristics on the carrier concentration and different behavior for n-and p-type InP. Modeling of the data enables one to use this method as a quantitative tool for high-resolution two-dimensional dopant profiling.

Determining the cross-sectional doping profile of very small metal–oxide–semiconductor field effect transistors and specifically the direct measurement of their channel length is necessary for true channel engineering to be possible. Scanning capacitance microscopy (SCM) has generated unprecedented images of the cross-sectional doping profiles of very small transistors. The bias voltage dependence of these images has motivated us to investigate the SCM technique in greater detail. Using electrical simulations, we have focused on the pn junction to establish the qualitative and quantitative relationship between the bias voltage and the pn junction location. The ability to confidently interpret the images produced with SCM will allow us to improve simulation models, trouble-shoot process flow, and determine the effective channel length of semiconductor devices.

We have achieved extremely high drive current performance and ballistic (T>0.8) transport using ultra-thin (

As MOSFET channel lengths are scaled to below 100 nm, the determination of the effective channel length, L/sub 0/ becomes increasingly important. We have studied cross-sectioned MOSFETs with gate lengths down to 90 nm using scanning capacitance microscopy (SCM), and show the first images of these state-of-the-art devices. Using a device simulator we have quantitatively established the relation between L/sub 0/ and the SCM response in the channel region, allowing us to determine L/sub 0/ from the SCM measurements. We have explored the ultimate resolution attainable using this technique; experimentally, using very sharp probe tips and with numerical simulations.

With the increased scaling down of MOSFET dimensions, delineation of the p-n junction becomes increasingly important. We have studied cross-sectioned 0.15 micron process MOSFETs using a newly developed technique, scanning capacitance microscopy (SCM), and report the first direct measurement of the channel length for these state-of-the-art devices. Using a device simulator we have quantitatively established the connection between the dopant profile and the SCM response while scanning across a p-n junction. This allows us to determine the position of the p-n junction from the SCM measurements.

We present the first p-channel Vertical Replacement-Gate (VRG) MOSFETs. Like the VRG-nMOSFETs demonstrated last year, these devices show promise as a successor to planar MOSFETs for highly-scaled ULSI. Our pMOSFETs retain the key features of the nMOSFETs and add channel doping by ion implantation and raised source/drain extensions (SDEs). We have significantly improved the core VRG process to provide high-performance devices with gate lengths of 100 nm and below. Since both sides of the device pillar drive in parallel, the drive current per /spl mu/m of coded width can far exceed that of planar MOSFETs. Our 100 nm VRG-pMOSFETs with t/sub ox/=25 /spl Aring/ drive 615 /spl mu/A//spl mu/m at 1.5 V with I/sub OFF/=8 nA//spl mu/m-80% more drive than specified in the 1999 ITRS Roadmap at the same I/sub OFF/. We demonstrate 50 nm VRG-pMOSFETs with t/sub ox/=25 /spl Aring/ that approach the 1.0 V roadmap target of I/sub ON/=350 /spl mu/A//spl mu/m at I/sub OFF/=20 nA//spl mu/m without the need for a hyperthin (

We have observed superconductivity in thin films of (La1−xSrx)2CuOy which are fabricated by implanting evaporated La/Cu multilayer films with Sr and annealing in oxygen. The films are insulating and partially transparent as-implanted, but they darken and become conducting at annealing temperatures as low as 500°C. The resistive behavior is very sensitive to the annealing conditions and the superconducting layer appears to be buried beneath the surface. Similarly, implantation of F, O, and Ne into single crystals and high quality (χmin

Low leakage tunnel junctions have been prepared on (001) oriented YBCO thin films. The junctions were made by evaporating Pb counterelectrodes on chemically etched surfaces of YBCO thin films. The tunneling conductance as a function of voltage shows structure which is reproducible from junction. This structure is very similar to that obtained with etched junctions on single crystal YBCO.

An ultrahigh vacuum system has been constructed which permits deposition of thin films onto 4.2-K substrates. The evaporation mechanism is contained within a small cylindrical vessel which is totally immersed in liquid (4)He. This device has been used to study superconductivity in PbBi and Ga, PdH and PdD, and most recently, transport properties of ultrathin films.

Recent progress in the growth of thin epitaxial silicides on silicon has resulted in films of very high quality with especially smooth interfaces. Using a completely different technique, high dose implantation followed by annealing, we have succeeded in creating buried single-crystal layers of CoSi2, NiSi2, and CrSi2 in crystalline silicon. The CoSi2 and NiSi2 layers grow in both the (100) and (111) orientations--those in (111) have better crystallinity, but those in (100) are of higher electrical quality. The CrSi2, on the other hand, only grows in the (111) orientation where its hexagonal structure has an almost perfect lattice match to silicon. We call this new internal growth process “mesotaxy” by analogy with epitaxy which refers to single-crystal growth on surfaces.

We have prepared low leakage tunnel junctions on epitaxial YBa2Cu3O7 (YBCO) films grown on SrTiO3(001) by evaporating Pb counterelectrodes onto chemically etched YBCO surfaces. Structure in the voltage dependence of the tunneling conductance is reproducible and strongly resembles what has been obtained in similarly etched junctions on YBCO single crystals.

Metal-Insulator-Semiconductor Tunneling Microscopy is a new technique for creating a 2 dimensional map of the carrier concentration in a semiconductor. This is done by measuring the tunneling current between a conducting Atomic Force Microscope tip and a semiconductor sample. Here we present the application of this method to InP. By exploring the current voltage characteristics of p- and n-type InP over a large range of voltages and carrier concentrations we find they are well-described by Metal-Insulator-Semiconductor theory. A fitting procedure of this model to the data gave a maximum deviation of 5%.

It is now possible using scanning capacitance microscopy to directly obtain a two-dimensional profile of the doping in MOSFETs with gate lengths greater than 60 nm. We have accomplished this using highly doped, ultrasharp silicon cantilevers with a tip diameter of less than 10 nm. These tips provide images with very little voltage dependence (over a 1-2 V range), and improved resolution ( 30-50 nm resolution.

The narrowest feature of an integrated circuit is the silicon dioxide gate dielectric (3–5 nm). The viability of future CMOS technology is contingent upon thinning the oxide further to improve drive performance, while maintaining reliability. Practical limitations due to direct tunneling through the gate oxide may preclude the use of silicon dioxide as the gate dielectric for thicknesses less than 1.3 nm, however.

We have studied cross-sectioned n- and p-metal-oxide-semiconductor field effect transistors with gate lengths approaching 60 nm using a scanning capacitance microscope (SCM). In a homogeneous semiconductor, the SCM measures the depletion length, determining the dopant concentration. When imaging a real device there is an interaction between the probe tip and the built-in depletion of the p-n junction. With the help of a device simulator, we can understand the relation between the SCM images and the position of the p-n junction, making the SCM a quantitative tool for junction delineation and direct measurement of the electrical channel length.