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A novel system-on-a-chip compatible one-transistor one-capacitor ferroelectric random-access memory array (1T1C FeRAM) based on ferroelectric Hf0.5Zr0.5O2 with a capacitor under bitline (CUB) structure was experimentally demonstrated. The CUB structure facilitates the application of post-metallization annealing on metal/ferroelectric/metal capacitors above 500 °C because they are fabricated before the back-end-of-line process. A large remanent polarization of 2Pr $ {>}40~\mu \text{C}$ /cm2, projected endurance ${>}10^{11}$ cycles, and ten years of data retention at 85 °C were obtained at 500 °C, after metallization using a single large capacitor. Furthermore, a large memory window of the 64 kbit 1T1C FeRAM array with 500 °C post-metallization was comprehensively demonstrated without degradation of the underlying CMOS logic transistors. The operation voltage and speed dependence were extensively investigated using a dedicated sense amplifier for the 1T1C FeRAM. Furthermore, the perfect bit functionality at an operation voltage of 2.5 V and a read/write speed < 10 ns were obtained. Therefore, superior properties of CUB-structured 1T1C FeRAM can be achieved by flexible process engineering of crystallization annealing for metal/ferroelectric/metal fabrication.

We have developed and integrated a mobility-enhanced FET and a wakeup-free ferroelectric (FE) capacitor using Sn-doped InGaZnO (IGZTO) and demonstrated 1T1C FeRAM cell operation for 3-D embedded RAM application. IGZTO FET can achieve >20 cm²/V · s mobility with an ultrathin channel, which is 2x higher than InGaZnO (IGZO) FET. The physics of mobility enhancement in oxide semiconductor FET with IGZTO channel is investigated by both experimental and simulation methods. The FE capacitor with large remanent polarization and low-temperature process at 400 °C is achieved. We have also studied the impact of thin-film access transistors on 1T1C cell operation with gate voltage dependence and capacitor size dependence. SPICE simulation is used for an extremely scaled device that achieves ~ns operation. The proposed memory technology will enable high-density and energy-efficient computing by the proximity of processor core and memory in monolithic 3-D integration.

Study of magnetoelectric coupling in Type II multiferroics is indeed a fascinating area of research in next-generation nonvolatile data memory devices. To facilitate memory device applications, it is necessary to find a single phase material with substantial magnetoelectric coupling at room temperature. A room temperature nonvolatile memory device in aluminium doped Sr3Co2Fe24O41 is demonstrated here. Aluminium doping in Sr3Co2Fe24O41 not only enhances magnetoelectric coupling but also allows for easy tuning of memory states in the device. Maximum Magnetoelectric coefficient (α) of 59.44 mV/cm-Oe is observed for x = 0.04 in Sr3Co2(Fe1-xAlx)24O41. α could be stored and maintained for memory use for a broad period of time; additionally, the memory states of the device could be switched and tuned with electric pulses, which is an additional benefit of the memory device. This kind of magnetoelectric memory can be beneficial due to its non-destructive read operations, which is the main challenge in FERAM. This conveniently integrable single phase, robust memory system with increased memory density will undoubtedly pave the way for future memory applications.

The HfZrO x (HZO) ferroelectric material is a promising material for ferroelectric memory and is compatible with the semiconductor process for ferroelectric random access memory (FeRAM) and negative capacitance field effect transistor. However, defects often exist in the grain boundary to influence the performance or reliability of devices. In addition, uniformity between devices must be considered when they are mass-produced. Therefore, the grain size will become important in determining the performance and reliability. In this study, we use electrical measurements of current–voltage, capacitance–voltage, and polarization–voltage measurements to test high- and low-temperature deposition devices, with a transmission electron microscope (TEM) image to confirm the grain size. Finally, we propose a model to explain the phenomenon and provide a method to obtain better ferroelectric memory.

To scale the ferroelectric random access memory (FeRAM) technology toward 28 nm or beyond, it is critical to develop stacked capacitor (with sufficient surface area) to allow good sense margin for the 1-transistor- 1-capacitor (1T1C) bit cell. Therefore, to enable 3-D integration in back-end-of-line (BEOL) process, it is essential to optimize the fabrication recipes in low-thermal budget ( 50 s) in low temperature (\sim 350 °C), the ferroelectric properties of HZO could be fully manifested. No degradation is shown in the remnant polarization ( ${P}_{r}$ ) under the optimized low-temperature process. Furthermore, the retention/endurance characteristics with different ${P}_{r}$ states were measured to determine the minimally required write voltage. Finally, the SPICE simulation is conducted to evaluate the sense margin of the projected 28-nm 1T1C array with stacked cylindrical capacitors using the measured ${P}_{r}$ drift behavior over time.

Ferroelectric random access memory cell (FeRAM) consists of one selection transistor with high switching performance and one memory transistor with large hysteresis. The simple fabrication method for the selection transistor with high mobility and the memory transistor with large hysteresis within one cell has been a challenge and not adequately explored. We demonstrated the selective etching of dielectric polymer buffer layer for the organic ferroelectric memory cell. The dielectric buffer layer of polymethylmethacrylate (PMMA) is formed on the ferroelectric gate insulator of poly(vinylidenefluoride-co-trifluoroethylene) [P(VDF-TrFE)] to enhance mobility of selection transistors. The UV ozone was partially treated on the PMMA/P(VDF-TrFE) bilayer which enables the top PMMA layer to be selectively etched due to the large process margin because the UV ozone etch rate of PMMA to P(VDF-TrFE) is more than 50 times. While the selection transistor with the PMMA buffer layer shows an enhanced mobility of 0.2 cm2 V−1 s−1, the memory transistor undergoing UV ozone etching process with post-annealing exhibits conventional ferroelectric memory properties such as large hysteresis and good memory retention characteristics. In our ferroelectric memory cell, the memory transistor is electrically isolated completely from the high negative bias in the bit-line during switching-off of the selection transistor. Our polymer selective etching for a ferroelectric memory cell is a useful technique in developing nonvolatile polymer FeRAM. In this work, we proposed a selective etching process to implement a selection transistor and a memory transistor in a ferroelectric memory cell. The difference of etch rates of P(VDF-TrFE) and PMMA by UV ozone (UVO) treatment was investigated, and the effect of the UVO etching and post-annealing on the surface morphology and ferroelectricity of PMMA/P(VDF-TrFE) bilayer were examined. While the OFET with the bilayer shows high on-off current ratio, the selective etched bilayer exhibits good ferroelectric retention characteristics. Finally, we implemented the ferroelectric memory cell without crosstalk between neighboring cells.

When scaling the lateral size of a ferroelectric random access memory (FeRAM) device down to the nanometer range, the polarization switching-induced displacement current becomes small and challenging to detect, which greatly limits the storage density of FeRAM. Here, we report the observation of significantly enhanced injection currents, much larger than typical switching currents, induced by polarization switching in BiFeO3 thin films via conductive atomic force microscopy. Interestingly, this injected current can be effectively modulated by applying mechanical force. As the loading force increases from ∼50 to ∼750 nN, the magnitude of the injected current increases and the critical voltage to trigger the current injection decreases. Notably, changing the loading force by an order of magnitude increases the peak current by 2-3 orders of magnitude. The mechanically boosted injected current could be useful for the development of high-density FeRAM devices. The mechanical modulation of the injected current may be attributed to the mechanical force-induced changes in the barrier height and interfacial layer width.

The discovery of ferroelectricity in hafnium zirconium oxide (HZO) thin films has attracted wide attention from academia to industry due to the application in ferroelectric non-volatile random access memories (FeRAM) with prominent performance in scalability and CMOS process compatibility. Dielectric behavior of ferroelectric HZO thin films is a key factor affecting the dynamic effect, piezoelectric and electrostrictive effect. Interface between HZO and capping electrodes plays an important role in regulating the dielectric properties. In this paper, the impedance frequency response and dielectric spectrum of ferroelectric HZO thin films were analyzed. Parameters of the interface were extracted to analyze the regulating effect on the dielectric properties based on an impedance model with constant phase element (CPE). Besides, dielectric spectrums at elevated temperatures were identified to verify this analysis.

In order to improve the performance of memory semiconductors, devices are miniaturized and the degree of integration is increasing. In response to this, fields such as FTJ, Fe-FET, and FeRAM using ferroelectrics are attracting attention. Among them, the hafnia-based ferroelectric has emerged as the core material of the next generation semiconductor memory using ferroelectric due to its advantages such as thickness and CMOS process compatibility. In order for the hafnia material to be mass-produced and commercialized in the industry, electrical properties must be evaluated in various environments. In order to contribute to this, this study observes the temperature-dependent change of hafnia based capacitor, and reports its mechanism.

This paper presents a flexible ferroelectric random access memory (FeRAM) cell with a one-transistor-one-transistor structure. The FeRAM cell was composed of a control transistor (CT) and an omega-shaped ferroelectric memory transistor (MT). An inkjet-printed single-walled carbon nanotube (SWCNT) were utilized as a semiconducting channel layers of both transistors. An omega-shaped ferroelectric gate was formed through inkjet-printing of poly(vinylidene fluoride-co-trifluoroethylene) (P(VDF-TrFE)) onto the SWCNT channel of the MT. The gate electrode of the CT was electrically connected to the drain electrode of the MT, while the gate electrode of the MT was connected to the source electrode of the CT. The 1T1T architecture enabled the separation of the writing and reading operations, which afforded nondestructive readout capability. The desired multi-level conductance states could be deterministically controlled by tuning the dipole polarization in the ferroelectric P(VDF-TrFE) layer of the MT. The resulting FeRAM cell showed excellent device performances such as five-level data storage, a high programming/erasing current ratio (>105), a retention time (>104 s), and operational stability (>1000 cycles). The 1T1T FeRAM cell fabricated by inkjet printing technique opens up new opportunities for realizing future large-area flexible memory cells.

Bismuth Layer-Structured Ferroelectrics materials (BLSFs) are widely used for many applications like resonators, filters, sensors, actuators and are appropriate for non-volatile Ferroelectric Random Access Memory (FeRAM) applications. The additional advantage of BLSF materials is that in electrical applications in they work at high temperatures. In the case of resonator applications, piezoelectric components are used as inductors. Usually BLSF materials typically have higher Curie temperature than PZT materials, so instead of PZT materials, BLSFs are used for high temperature piezoelectric sensor applications. SrBi4Ti4O15 (SBT) compound is a member of Aurivillius family Bismuth layered structured Ferroelectrics. The dielectric properties of Sodium and Praseodymium doped SBT, Sr0.2Na0.4Pr0.4Bi4Ti4O15 (SNPBT), prepared by solid state double sintering method using planetary ball mill, and is studied in the present work. Single phase is confirmed from XRD and microstructure is studied from SEM. The temperature dependence of dielectric constant and dielectric loss are studied at different frequencies. The Curie temperature increased by doping SBT with Na1+and Pr3+. Thus this piezoelectric ceramic is suitable for high temperature sensor applications.

A new concept of read-out method for ferroelectric random-access memory (FeRAM) using a graphene layer as the channel material of bottom-gated field effect transistor structure is demonstrated experimentally. The transconductance of the graphene channel is found to change its sign depending on the direction of spontaneous polarization (SP) in the underlying ferroelectric layer. This indicates that the memory state of FeRAM, specified by the SP direction of the ferroelectric layer, can be sensed unambiguously with transconductance measurements. With the proposed read-out method, it is possible to construct an array of ferroelectric memory cells in the form of a cross-point structure where the transconductance of a crossing cell can be measured selectively without any additional selector. This type of FeRAM can be a plausible solution for fabricating high speed, ultra-low power, long lifetime, and high density 3D stackable non-volatile memory.

The behavior of ferroelectric thin film capacitors under radiation environments is significant for the development of rad-hard ferroelectric random access memory (FeRAM). Here, we fabricated the ferroelectric thin film capacitors with 12-nm-thick HfxZr1−xO2 (HZO) and investigated the total ionizing dose (TID) effects of 60Co γ-rays radiation on them. It is found that after 60Co γ rays radiation with a total dose as high as 10 Mrad (Si), the hysteresis loops of the HZO ferroelectric thin film capacitors slightly shift to the positive bias direction, and the remanent polarization decreases by 5%. Besides, negligible changes in surface morphology, leakage current density, relative dielectric constant, dielectric loss, endurance and retention characteristics are observed. These results suggest that the HZO ferroelectric thin film capacitors have great potential in the application for highly rad-hard FeRAM.

The recent demand for analogue devices for neuromorphic applications requires modulation of multiple nonvolatile states. Ferroelectricity with multiple polarization states enables neuromorphic appl...

Hf 0.5 Zr 0.5 O 2 (HZO) ferroelectric random access memory (FeRAM) has been demonstrated in 130nm node with 1T1C structure. To scale FeRAM to 28nm or beyond, a high-aspect ratio embedded DRAM-like 3D cylinder capacitor is expected to ensure sufficient cell capacitance and sense margin. In this work, we investigate an alternative approach with 2T1C structure that takes advantages of a back-end-of-line (BEOL) oxide channel writing transistor, a small planar ferroelectric capacitor, and a silicon logic reading transistor. Firstly, the proof-of-concept of 2T1C bit cell was experimentally demonstrated. Then, the scalability towards 28nm was simulated with array-level parasitics. Thanks to the transconductance reading out mechanism, a 784 nm2 ferroelectric capacitor in 2T1C could significantly reduce energy consumption 6.5–11× compared to the traditional 1T1C FeRAM with similar cell area at 28nm.

A novel 64 kbit one-transistor one-capacitor (1T1C) ferroelectric random access memory (FeRAM) array based on ferroelectric Hf 0.5 Zr 0.5 O 2 (HZO) was proposed in a prior report. However, this array requires a low operation voltage for integration into advanced technology nodes, and its practical endurance remains unclear. To address these limitations, this study experimentally demonstrates the improved characteristics of a ferroelectric HfO 2 -based 1T1C FeRAM array. Thickness scaling of the ferroelectric HZO contributes to low-voltage operation of 1T1C FeRAMs, yielding 100% bit functionality at an operation voltage of 2.0 V and operating speed of 16 ns. Furthermore, the endurance performance of the 1T1C FeRAM memory array was investigated for the first time. Excellent cycling endurance (>108 cycles) at an accelerated stress voltage of 3.5 V at 85°C was experimentally observed. The 1 ppm RBER at 2.0 V, 100 ns, and 85°C operation was predicted to be >1018 cycles, based on the dependence of time to breakdown on the stress voltage. This technology matches the requirements of last-level cache and low-power systems on chips for Internet of things applications.

Advanced non-volatile memory concepts such as the 1T1C ferroelectric (FE) random-access memory (FeRAM) and the 1T1C FE field-effect transistor (FeFET) can be realized by connecting a metal-ferroelectric-metal (MFM) capacitor placed in the back end of line (BEoL) of a microchip to the drain and gate contacts of a standard logic device, respectively. With the vertical distributed select devices in the front-end of line (FEoL) and the storage elements in the BEoL, both concepts increase the effective memory density of a microchip without introducing major changes in the FEoL fabrication technology. However, for advanced neuromorphic computing architectures, the 1T1C FeFET is the device of choice, since it provides non-destructive readout. The most promising material for the integration of FE non-volatile memory functionalities into the BEoL is Zr doped HfO 2 (HZO). It crystallizes at low temperatures in the orthorhombic phase (the one with FE properties) and with a polycrystalline structure. The latter is important to enable analogue like switching in synaptic devices. Herein, the above-mentioned memory concepts are introduced and key steps to optimize the HZO films for the BEoL integration and for the neuromorphic computing use case are described.

Since the first floating gate memory was introduced in 1968, Non-Volatile Memory (NVM) has been widely investigated and developed for permanent data storage. The progress of metal oxide semiconductor field-effect transistor (MOSFET) technology even makes the memory scalable. The scale-down of the memories faces other issues. The thinner oxide layer induces a higher leakage current and worse electrical characteristics. There are promising NVMs such as ferroelectric (FeRAM), phase-change (PCRAM), magneto-resistive (MRAM), and resistive (RRAM).In this study, RRAM devices with a metal-insulator-metal (MIM) structure are investigated. Amorphous indium gallium zinc oxide (a-IGZO) is deposited with atmosphere pressure-plasma enhanced chemical vapor deposition (AP-PECVD). The resistivity of an a-IGZO insulator is dominated by oxygen vacancy, and the electrical characteristics of RRAM devices are crucially influenced by the insulator layer. Magnesium (Mg) is doped into an a-IGZO insulator layer to modulate the RRAM device's electrical characteristics. The results show that 1% of Mg doping makes the stability progress on devices set and read process. If more Mg is doped into a-IGZO insulator layer, Mg occupies more oxygen vacancies, and RRAM devices become more unstable and unreliable.

Ferroelectric random-access memory (FeRAM) is one of the promising candidates for future nonvolatile memory devices. High density FeRAM requires more robust electrode material for capacitor reliability to replace Pt or Ir electrodes, especially in the case of small feature. In this study, DC sputtered Sn-doped In 2 O 3 (ITO) was employed for bottom and top electrodes of (Pb,La)(Zr,Ti)O 3 (PLZT) capacitor. The ferroelectric properties of PLZT capacitors with ITO electrodes by sputtering with difficult temperature/O 2 content and subsequent O 2 annealing. The fatigue degradation characteristics were improved by fully oxidized ITO bottom electrode.

A century ago ferroelectricity was discovered by J. Valasek[1] which can be used in non-volatile memory applications based on two energetically stable distinct electric polarization states. The conventional perovskite based ferroelectric materials suffer from CMOS incompatibility and scalability issues, hence cannot be used in state of the art scaled CMOS technologies. In 2011, ferroelectricity was reported in CMOS compatible scaled doped HfO2 films [2-3], which can solve the integration issues of perovskites based ferroelectrics. Among the HfO2 based ferroelectric materials, the mixed oxide of HfO2 and ZrO2 (Hf0.5Zr0.5O2) exhibits good ferroelectric properties with a wide process window and CMOS back-end compatible thermal budget.

This paper experimentally demonstrates fundamental memory array operation of a ferroelectric HfO2-based 1 T1 C FeRAM. Metal/ferroelectric/metal (MFM) capacitors consisting of a TiN/ $\mathrm{Hf}_{0.5}\mathrm{Zr}_{0.5}\mathrm{O}_{2}(\mathrm{HZO}$ )/TiN stack were optimized for a sub 500°C process. Structures revealed excellent performance such as remanent polarization $2\mathrm{P}_{\mathrm{r}} > 4\vert \mu\mathrm{C}/\mathrm{cm}^{2}$ , endurance> 1011 cycles, and 10 years data retention at 85°C. Furthermore, the MFM capacitors were successfully integrated into a 64 kbit 1T1C FeRAM array including our dedicated circuit for array operation. Back-end-of-line (BEOL) wiring showed no degradation of the underlying CMOS logic. Program and read operation were properly controlled resulting in 100 % bit functionality at an operation voltage of2.5 Vand operating speed at 14 ns. This technology matches requirements of last level cash (LLC) and embedded non-volatile-memory (NVM) in low power System-on-a-Chip (SoC) for IoT applications.

We report on the scalability of ferroelectric TiN/HfO2-based/TiN capacitors by integrating them in the Back-End-Of-Line of 130nm CMOS technology. Excellent performance is reported on those scaled bitcells, such as remanent polarization 2•PR > 40µC/cm2, endurance > 1011 cycles, switching speeds < 100ns, operating voltages < 4V, and data retention at 125°C. This demonstration suggests that ultra-low power (< 10fJ/bit) FeRAM memories, so far using PZT material that limits integration to 130nm node, could be attractive at 130nm node and beyond thanks to CMOS compatible ferroelectric HfO2.

Ferroelectric nanostructures have received much attention because they can be used for the next generation of ferroelectric random-access memory (FeRAM) in flexible electronic devices. Manipulation of domain reversal in ferroelectric nanostructures is extremely important, but rarely studied. Herein, we present generic and reusable fabrication of 2D-confined P(VDF-TrFE) nanodots with an integration density of up to 4 Gbit per inch2, and then investigate the structural maps and the corresponding domain switching kinetics of P(VDF-TrFE) nanodots by atomic force microscope-based (AFM-based) technology. Meanwhile, their storage features, such as precise programmability and data stability, are well characterized by piezoresponse force microscopy (PFM). Remarkably, the ferroelectric crystals in single-confined P(VDF-TrFE) nanodots simultaneously aligned in a plane over the whole patterned region. 2D-confined P(VDF-TrFE) 50 : 50 nanodots has high-temperature ferroelectric (HT FE) phase with all-trans conformations, which endows them with excellent memory characteristics, such as a low operating voltage of 3 V, a short domain nucleation of 100 ms (by V = 10 V), a fast domain growth, an excellent writing–erasing repeatability, and a long retention time. Compared with normal ferroelectric materials, like P(VDF-TrFE) 70 : 30, approximately 150% ratio of energy loss and a 5-fold duration for domain nucleation can be saved. Especially, written domains were well confined in the P(VDF-TrFE) 50 : 50 nanodots, which attains precise programmability on a single nanodot. Our systematic study provides an alternative route for the fabrication of ferroelectric nanostructures that are worth considering for the next generation of flexible FeRAM in all-organic nanoelectronic devices.

A 2T2C ferroelectric memory cell consisting of a select transistor, a read transistor and two ferroelectric capacitors that can be operated either in FeRAM mode or in memristive ferroelectric tunnel junction mode is proposed. The two memory devices can be programmed individually. By performing a combined readout operation, the two stored bits of the memory cells can be combined to perform in-memory logic operation. Moreover, additional input logic signals that are applied as external readout voltage pulses can be used to perform logic operation together with the stored logic states of the ferroelectric capacitors. Electrical characterization results of the logic-in-memory (LiM) functionality is presented.

In this work, metal–ferroelectric–semiconductor field-effect transistors (MFSFETs) have been fabricated for the first time using poly(vinylidene fluoride) (PVDF) and polyvinylidene fluoride trifluoroethylene [P(VDF-TrFE)] thin films as ferroelectric layer. PVDF and P(VDF-TrFE) thin films were fabricated by sol–gel method on Si(100) wafers. The drain current–gate voltage (ID–VG) characteristics of the fabricated MFSFETs with PVDF and P(VDF-TrFE) thin films exhibited very good ferroelectric hysteretic curves with counterclockwise loop same to those of other ferroelectric materials. It also demonstrates a realizable possibility of one-transistor type (1T-type) ferroelectric memory without a buffer layer using thin organic material. The absence of a buffer layer presents many advantages such as the elimination of the depolarization field, leakage current influence of the thin buffer layer, reduction of the process steps, low-operational voltage, and low-power consumption. The MFSFETs using PVDF and P(VDF-TrFE) thin films as ferroelectric layer have promising potential for use in low-voltage operable and flexible 1T-type ferroelectric random access memory (FeRAM) using organic material. On the other hand, it also has been attempted to make ferroelectric field-effect transistors (FeFETs) with blended PVDF/P(VDF-TrFE) films in order to compare the P(VDF-TrFE) films. The ferroelectric films for metal–ferroelectric-metal (MFM) capacitors have been fabricated using the blended PVDF/P(VDF-TrFE) solutions with different concentrations by sol–gel method. Ferroelectric field-effect transistors using poly(3-hexylthiopene) (P3HT) channel layer have also been fabricated on TiN substrates in order to compare the device characteristics of the pure P(VDF-TrFE) and blended PVDF/P(VDF-TrFE) thin films in this study.

Ferroelectrics are theoretically an ideal solution for low write power nonvolatile memories. However, the complexity of ferroelectric perovskites has hindered the scaling of such devices to competitive feature sizes. The discovery of ferroelectricity in hafnium oxide solved this issue. Ferroelectric memories in three variants, capacitor based ferroelectric RAM, ferroelectric field effect transistors and ferroelectric tunneling junctions have become competitors for future memory solutions again. In this paper, the basics and current status of hafnium oxide based ferroelectric memory devices is described and recent results are shown.

Purpose Development of (1T-type) ferroelectric random access memory (FeRAM) has most actively progressed since 1995 and motivated by the physical limits and technological drawbacks of the flash memory. 1T-type FeRAM implements ferroelectric layer at the field effect transistor (FET) gate. During the course of the investigation, it was very difficult to form a thermodynamically stable ferroelectric-semiconductor interface at the FET gate, leading to the introduction of one insulating buffer layer between the ferroelectric and the silicon substrate to overcome this problem. In this study, Al2O3 a high-k buffer layer deposited by plasma enhanced atomic layer deposition (PEALD) is sandwiched between the ferroelectric layer and silicon substrate. Design/methodology/approach Ferroelectric/high-k gate stack were fabricated on the silicon substrate and pt electrode. Structural characteristics of the ferroelectric (PZT) and high-k (Al2O3) thin film deposited by RF sputtering and PEALD, respectively, were optimized and investigated for different process parameters. Metal/PZT/Metal, Metal/PZT/Silicon, Metal/PZT/Al2O3/Silicon structures were fabricated and electrically characterized to obtain the memory window, leakage current, hysteresis, PUND, endurance and breakdown characteristics. Findings XRD pattern shows the ferroelectric perovskite thin Pb[Zr0.35Ti0.65]O3 film with (101) tetragonal orientation deposited by sputtering and PEALD Al2O3 with (312) orientation showing amorphous nature. Multiple angle analysis shows that the refractive index of PZT varies from 2.248 to 2.569, and PEALD Al2O3 varies from 1.6560 to 1.6957 with post-deposition annealing temperature. Increase in memory window from 2.3 to 8.4 V for the Metal-Ferroelectric-Silicon (MFS) and Metal-Ferroelectric-Insulator-Semiconductor (MFIS) structure has been observed at the annealing temperature of 500°C. MFIS structure with 10 nm buffer layer shows excellent endurance of 3 × 109 read-write cycles and the breakdown voltage of 33 V. Originality/value This paper shows the feature, principle and improvement in the electrical properties of the fabricated gate stack for 1T-type nonvolatile FeFET. The insulating buffer layer sandwiched between ferroelectric and silicon substrate acts as a barrier to ferroelectric–silicon interdiffusion improves the leakage current, memory window, endurance and breakdown voltage. This is perhaps the first time that the combination of sputtered PZT on the PEALD Al2O3 layer is being reported.

The properties and applications of materials with non-volatile memory based on HfO2 were briefly considered. In addition, an overview of the obtained results was given. On the basis of these results, the possibility of use of the structures TiN/ Hf0.5Zr0.5O2/ TiN/ SiO2/ Si and TiN/ HfxAl1-xOy/ Pt/ SiO2/ Si for the non-volatile memory of FeRAM and ReRAM types obtained by the atomic-layer deposition was shown. In addition, the scalability of these elements and opportunity to create promising submicron integrated circuits for ferroelectric and resistive memory were demonstrated.

In this letter, we propose one-transistor ferroelectric NOR type (Fe-NOR) non-volatile memory based on HfZrOx ferroelectric FETs (FeFETs). The enhanced drain-channel coupling in ultra-short channel FeFETs is utilized to dynamically modulate the memory window of storage cells, thereby resulting in simple erase-, program-, and read-operations. The simulation analysis predicts sub-1V program/erase voltages in the proposed Fe-NOR memory array and, therefore, presents a significantly lower power alternative to conventional FeRAM and NOR flash memories.

A 10.5 nm silicon doped HfO2 film is deposited and examined on three different bottom electrodes: a TiN electrode such as would be found in capacitive FeRAM, a lightly doped p-Si substrate as would be present in an FeFET, and an n+ Si electrode. The HfO2 stack deposited on n+ silicon is shown to have a coercive voltage of 2.9 V compared to 1.9 V for the film deposited on TiN. This is shown to be due to a 1.2 nm oxide present at the HfO2/Si interface dropping 36% of the voltage that is applied to the ferroelectric film stack. An FeFET fabricated with the film shows a 0.55 V threshold voltage shift due to ferroelectric polarization charge for a maximum applied gate bias of 5 V. After accounting for non-zero flat-band voltages, a 5 V bias on the transistor gate is shown to correspond to a 5.3 (μC/cm2) remnant polarization in the ferroelectric film. This corresponds with a theoretical maximum threshold voltage shift of 9.46 V, indicating that there is significant room for growth in FeFET performance if materials and processing challenges can be overcome.

The discovery of ferroelectricity in HfO2 thin film, which is compatible with the CMOS process, has revived interest in ferroelectric memory devices. HfO2 has been found to exhibit high ferroelectricity at a few nanometers thickness, and studies have rapidly progressed in the past decade. Ferroelectricity can be induced in HfO2 by various deposition methods and heat treatment processes. By combining ferroelectric materials with field-effect transistors, devices that combine logic and memory functions can be implemented. Ferroelectric HfO2-based devices show high potential, but there are some challenges to overcome in endurance and characterization. In this paper, we discuss the fabrication and characteristics of ferroelectric HfO2 film and various applications, including negative capacitance (NC)), Ferroelectric random-access memory (FeRAM), Ferroelectric tunnel junction (FTJ), and Ferroelectric Field-effect Transistor (FeFET).

We fabricated ferroelectric non-volatile random access memory (FeRAM) based on a field effect transistor (FET) consisting of a monolayer MoS2 channel and a ferroelectric PbTiO3 (PTO) thin film of gate insulator. An epitaxial PTO thin film was deposited on a Nb-doped SrTiO3 (Nb:STO) substrate via pulsed laser deposition. A monolayer MoS2 sheet was exfoliated from a bulk crystal and transferred to the surface of the PTO/Nb:STO. Structural and surface properties of the PTO thin film were characterized by X-ray diffraction and atomic force microscopy, respectively. Raman spectroscopy analysis was performed to identify the single-layer MoS2 sheet on the PTO/Nb:STO. We obtained mobility value (327 cm2/V·s) of the MoS2 channel at room temperature. The MoS2-PTO FeRAM FET showed a wide memory window with 17 kΩ of resistance variation which was attributed to high remnant polarization of the epitaxially grown PTO thin film. According to the fatigue resistance test for the FeRAM FET, however, the resistance states gradually varied during the switching cycles of 109.

The quest for non-volatile memories has attracted tremendous attention, especially in mature ferroelectric random access memory (FeRAM) with properties of high read/write speed and low power consumption. Strain engineering of multiferroic BiFeO 3 (BFO) has recently become the subject of broad research interest because of its intriguing properties. In this study, we demonstrate the switchable diode characteristics in highly strained BFO thin films. Using a unique in situ electrical transmission electron microscopy (TEM), we verify the correlation between ferroelectric resistive switching with multilevel states and polarization reversal. Structural investigation confirms that the phase transition from mixed phase to pure T-like phase, accompanying with the polarization reversal by external bias, is the origin of the multilevel states. The switchable diode with multilevel resistive switching can be explained in terms of the variation of the barrier height, governed by ferroelectric polarization and polarity of the external bias. This research model, i.e. , engineering of the room inside, can offer an approach toward high-density memories.

In this letter, HfO2-based ferroelectric random access memory (FeRAM) with metal–insulator–metal structure is studied for the first time under radiation conditions. Y-doped HfO2-based FeRAM devices show high immunity to 60Co $\gamma $ ray radiation. Basic FeRAM parameters, such as leakage current, permittivity, remanent polarization, endurance, and fatigue, show almost no degradation after $\gamma $ ray radiation with a total dose as high as 12.96 Mrad (SI). Furthermore, the ferroelectric hysteresis loops show no distortion after radiation. The high stability of Y-doped HfO2 FeRAM devices under radiation demonstrates their great potential for nuclear and aerospace applications.

Hysteresis in the current–voltage characteristics of a ZnO thin-film transistor (TFT) has been studied. Electric dipoles at the interface of the dielectric and the channel have been proposed as the agents responsible for the hysteresis. From experimental results and theoretical analysis, the water diffusing into the active layer is found as the main origin of the hysteresis. Based on this finding, devices free of hysteresis were obtained by using heat treatment and a passivation layer to control water diffusion in the fabrication process. Conversely, the hysteresis characteristics can be engineered so as to benefit the application of electronic memory. The function of the TFT device that serves as a memory element was also investigated and demonstrated in this paper. Owing to its low temperature process and simplified structure (compared with the FeRAM), 3-D stacked or even transparent nonvolatile memory would be its potential application.

International audience; We demonstrate successful scalability of conventional 100µm diameter TiN/HZO/TiN capacitors down to 300nm by successfully co-integrating them for the first time in the Back-End-Of-Line of 130nm CMOS technology. Excellent performance are reported on those scaled bitcells, such as remnant polarization 2.PR > 40µC/cm², endurance > 10 11 cycles, switching speeds < 100ns, operating voltages < 4V, and data retention at 125°C. Presented results pave the way to < 10fJ/bit ultra-low power FeRAM for IoT applications.

In recent years electron devices based on ferroelectric materials have attracted a lot of interest well beyond FeRAM memories. Negative capacitance transistors (NC-FETs) have been investigated as steep slope transistors [1], [2], and Ferroelectric FETs (Fe-FETs) are under intense scrutiny also as synaptic devices for neuromorphc computing, where the minor loops in ferroelectrics can allow to achieve multiple values of conductance in read mode [3], [4], [5]. Furthermore, the persistence of ferroelectricity in ultra-thin ferroelectric layers paved the way to ferroelectric tunnelling junctions [6], where a polarization dependent tunneling current can be exploited to realize high impedance memristors, amenable for ultra power-efficient and thus massive parallel computation.

This paper reports on a new switching and frequency hopping mechanism of electromechanical transduction in ferroelectric capacitor (FeCAP) based CMOS-MEMS resonators implemented in Texas Instruments (TI) FeRAM technology. In this work, poling parameters are investigated to demonstrate bias-dependent pole/zero transitions accompanied by 180° phase shift in multiple mechanical modes of the device. To explain this behavior, the resonator Butterworth-Van Dyke (BVD) model is modified to account for nonlinear capacitance in the FeCAPs. The cancellation of motional branch current and feedthrough current between the Pb(Zr, Ti)O 3 (PZT) thin layers with bias voltage enables switching of electromechanical transduction. These switchable, CMOS-integrated FeCAP resonators are solidly confined with no release step using Back-End-of-Line (BEOL) acoustic waveguiding. This study highlights the unique benefits of ferroelectric transducers for nonlinear, tunable MEMS devices, and offers a promising new RF building block for monolithic programmable radio front ends.

International audience; A clear comparison between Atomic Layer Deposition and Ion Implantation Si doping techniques is established. Comparable remnant polarization and coercive fields are obtained at lower Si content (%Si) for Ion Implantation, with a slight decrease of endurance performance. Switching signal engineering demonstrates a wide range of performance achievable with HfO2:Si ferroelectric layer.

This paper studies a composite device composed of ferroelectric random access memory (FeRAM) and metal-oxide-semiconductor field effect transistor. The relationship between the hysteresis characteristics and VG is reported, and the on/off ratios under different writing voltages are presented. The gm–VG curve of the forward and reverse sweeping shows that under forward sweep a very clear instability appears while voltage increases. The reasons for this can be explained according to the voltage divider rule, the ID formula, and gm formula of transistors, which show that there is polarization of the ferroelectric material. Accordingly, a method is proposed to determine the critical point of the ferroelectric capacitor polarization in this 1T1C structure, which is advantageous because it identifies the appropriate reading voltage necessary for an effective program state of the 1T1C device. This method was shown in three 1T1C and three FeRAMs devices with different ferroelectric areas. Finally, this method was verified by the P–V loop of FeRAMs.

In order to reveal the temperature evolutionary characteristics of typical ferroelectric RAM (Random Access Memory) irradiated by femtosecond pulsed laser, a physical model of a typical ferroelectric RAM is established. The idea of using a continuous laser instead of a high-energy pulsed laser of the same energy on the laser transmission path was theoretically derived. The physical expression and thermal conduction model of the laser at different positions on the transmission path were simulated by Comsol Multiphysics simulation software. The melting and heat conduction process of the pulsed laser irradiating ferroelectric RAM are simulated, and the laser with different irradiation time is obtained. The temperature field distribution, melting and thermal conduction simulation parameters of the multi-layer target of the ferroelectric RAM are simulated by the femtosecond pulsed laser under the simulation conditions. The results show that the COMSOL Multiphysics simulation can accurately simulate the temperature field evolution of femtosecond pulsed laser irradiating ferroelectric RAM in the simulation experiment of single event effects. Heat radiation of the periphery of the ferroelectric RAM and the bottom of the heat transfer dominates. Thermal radiation transfers less energy to the pins and the periphery. After 5 s under the laser interaction, the temperature distribution of the ferroelectric RAM is stable. The heat conductivity, melting and convection characteristics of the ferroelectric RAM are basically consistent with the experimental results.

Lead hafnate titanate (PHT) thin film was deposited by pulse laser deposition, characterized for the usage as a ferroelectric capacitor in view of Ferroelectric Random Access Memory (FeRAM) devices, and compared with a lead zirconate titanate (PZT) reference, which was fabricated in the same conditions. Results indicate that the 126 nm-thickness PHT thin film with a low temperature self-buffer layer has a single (111)-orientation. The following electric measurements were performed to investigate the possibility of this thin film to use in the FeRAM applications by contrast to a PZT reference. This PHT sample demonstrates a good ferroelectric property with the remanent polarization of 51 μC/cm2. The remanent polarization with no obvious degradation has been observed after 2 × 109 fatigue reversals, which indicate that the PHT thin film a promising candidate in view of FeRAM applications.

The implementation and operation of the nonvolatile ferroelectric memory (NVM) tunnel field effect transistors with silicon-doped HfO2 is proposed and theoretically examined for the first time, showing that ferroelectric nonvolatile tunnel field effect transistor (Fe-TFET) can operate as ultra-low power nonvolatile memory even in aggressively scaled dimensions. A Fe-TFET analytical model is derived by combining the pseudo 2-D Poisson equation and Maxwell’s equation. The model describes the Fe-TFET behavior when a time-dependent voltage is applied to the device with hysteretic output characteristic due to the ferroelectric’s dipole switching. The theoretical results provide unique insights into how device geometry and ferroelectric properties affect the Fe-TFET transfer characteristic. The recently explored ferroelectric, silicon-doped HfO2 is employed as the gate ferroelectric. With the ability to engineer ferroelectricity in HfO2 thin films, a high-K dielectric well established in memory devices, the silicon-doped HfO2 opens a new route for improved manufacturability and scalability of future 1-T ferroelectric memories. In the current research, a Si:HfO2 based Fe-TFET with large memory window and low power dissipation is designed and simulated. Utilizing our presented model, the device characteristics of a Fe-TFET that takes full benefits from Si:HfO2 is compared with the same devices using well-known perovskite ferroelectrics. Finally, the Fe-TFET is compared with a conventional ferroelectric memory transistor highlighting the advantages of using tunneling memory devices.

Multilevel data ferroelectric storage memory is a breakthrough for addressing low density in ferroelectric random access memories. However, the application of the multilevel data ferroelectric storage memory is limited by high cost and difficulty to prepare high quality epitaxial films. Herein, we create a multilevel data ferroelectric storage memory with a non-epitaxial ferroelectric ultrathin film to overcome these issues. Through controlling the polarization switching and oxygen vacancy migration with the voltage pulses, we demonstrated that voltage-controlled barrier heights yield a memristive behavior with resistance variations. Moreover, we achieved eight logic states, which are written and read easily. Our results suggest new opportunities for ferroelectrics as high density non-volatile memories.

This work investigates the effect of process temperature on one-transistor-one-capacitor ferroelectric random access memory (1T1C FeRAM) cells fabricated with a HfZrOx ultrathin film applied as the 1T1C capacitor. Traditionally, the capacitor in 1T1C devices is grown on the drain, and such a structure is a type of dynamic memory. Such a structure, however, is prone to the leakage current phenomenon, which causes the amount of charge stored in the capacitor to be insufficient, leading to inaccurate data reading. To solve this problem, an alternative 1T1C structure placing the capacitor on the gate terminal has been proposed. For these alternative 1T1C FeRAM devices, our experimental results indicate that the deposition temperature of the ferroelectric layer has a significant effect on the basic electrical properties. To clarify this phenomenon, we propose a physical model which is based on the effect of the deposition temperature on the HfZrOx grain size.

2D ferroelectric-gated field-effect transistors are promising for future non-volatile memory and low-power logic applications, to combine the advantage of both 2D semiconductors and ferroelectric insulators [1]–[3]. However, the non-ideal 2D semiconductor/3D insulator interface results in interface traps which degrade the device performance, variability and reliability. To integrate 2D semiconductor together with 2D ferroelectric insulator as 2D van der Waals heterostructure ferroelectric field-effect transistors (Fe-FETs) can eliminate the interface trap issue and achieve ideal insulator/semiconductor interface in principle. Copper indium thiophosphate $(\mathrm{CuInP}_{2}\mathrm{S}_{6}$ , CIPS) is a novel two-dimensional (2D) ferroelectric material with layered single crystal structure and decent ambient stability [4]–[6]. Furthermore, it illustrates not only clear room temperature ferroelectric property with Curie point around 315 K, but also ferroelectric resistive switching characteristic.

Comprehensive summary of classification, feature, preparation of ferroelectric thin films are explained. Electron devices using ferroelectric thin films such as nonvolatile memories FeRAM and FeFET, ultrasonic sensor, infrared sensor and energy harvester are introduced. Recent topics on ferroelectric thin films and their electron devices are also added

Ferroelectricity is a material property were a remanent polarization exists under zero electrical field that can be reversed by applying an electrical field [1]. As consequence, two nonvolatile states exist that can be switched by an electrical field. This feature makes ferroelectrics ideally suited for nonvolatile memories with low write energy. Therefore, already in the 1950s first attempts have been made to realize ferroelectric nonvolatile memories based on ferroelectric barium titanate (BTO) crystals having evaporated electrodes on both sides [2]. The success of this approach was hindered by disturb issues that could be solved in the early 1990s by adding a transistor device as a selector [3]. Such a memory is referred to as a ferroelectric random access memory (FeRAM). Since reading of the ferroelectric polarization from a capacitor requires switching of the ferroelectric [1], the information will be destroyed and a write back is necessary. This can be avoided if the ferroelectric is placed inside of the gate stack of a MOS transistor resulting in a ferroelectric field effect transistor (FeFET) [1]. Conventional ferroelectric materials like BTO or lead- zirconium titanate (PZT) cannot be placed directly on silicon since unwanted interface reactions will occur. The necessary interface layer together with the space charge region of the transistor device leads to a rather low capacitance in series with the ferroelectric dielectric and consequently results in a strong depolarization field that has destroyed the nonvolatility of the FeFET device for many years and hinters scaling as well [4]. Today FeRAM devices are established on the market [3,5], but are limited to niche application since scaling is hindered by many integration problems associated to materials like PZT.